Scribd
Upload
37 views3 pages

Lab 4

Learning about clocks

Uploaded by

Adhi Suruli
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
37 views3 pages

Lab 4

Learning about clocks

Uploaded by

Adhi Suruli
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

Neuromorphic Engineering II Lab 4, Spring 2011 1

Lab 4 March 15, 2011

Layout Design Rule Check

Today you will start to learn to use the DRC tool in L-Edit, and to design layout following
the process design rules.

You will fix an incomplete and wrong layout of a a first-order lowpass filter, and instance
multiple copies of the cells to create a delay line. The goals are to

Understand native micron-based design rules.

Understand the reasons for antenna rules, density rules, and latch-up rules.

Find out and fix the DRC errors present in the layout.

Design new layout components complying with the design rules, and iteratively fixing
new errors.

To lay out the thinnest cell that you can, given the constraints on the circuit design
(transistor geometries).

To compose into a delay line using the basic cell.

To label nets for later documentation.

4.1 Instructions

You will use the files in the /projects/class/NE2/exercise4 folder. There you will find an
existing layout file (.tdb) containing the layout of a unity gain follower. Your task is to
correct the DRC errors, purposely introduced, and complete the design to create a follower-
integrator circuit, analogous to the one you did in lab2

4.1.1 DRC

Open the exercise4.tdb file, and open the follower cell. Run the design-rule checks and
correct all layout rules, trying to minimize the total area usage, given the transistor features
(i.e. make the layout as small as possible, without changing the transistor W and L sizes).
Neuromorphic Engineering II Lab 4, Spring 2011 2

Make sure you understand what the errors are and use the dimensions provided in the hand-
outs. You might also work with the Online DRC feature of L-Edit, which checks some of
the simpler spacing and overlap rules as you draw.

Learn how to navigate from error to error using the DRC Error Navigator dialog window.

Make sure that your circuit will work correctly and that the layout of the follower has no
additional errors that the DRC cannot check (e.g. note that some bulk connections are
missing).

In editing the layout, experiment with L-Edits editing features (hint: read the manual).
Particularly handy features are:

Cursor snapping to object vertices, edges, etc. speeds drawing

Multiple object editing

Edit-in-place directly to any object in the hierarchy

Edge, corner, arc, and stretch editing

4.1.2 Follower-Integrator

Open the FollInt and you will see your version of the follower cell in it. Now add a
Poly-Poly2 capacitor to turn it into a follower-integrator circuit. Use the process parame-
ters provided in the process parameters printout (as you did in the first layout exercise) to
design a capacitor of 100 fF. Draw the layout of the capacitor as a single rectangle in a way
to minimize mismatch, and keep the layout of the cell as compact as possible, given the
constraints on the size of the capacitor.

4.1.3 Delay line

Open the Delay-line cell and modify it to get a correct delay line of three elements. The
easiest approach is to delete all the cells inside and start again from scratch.

Insert the FollInt cell and create an array of 1 3 cells.

Make sure all global signals (power supplies and biases) are connected, and that the output
of one cell is properly connected to the input of the other cell. Modify the FollInt and the
follower cell using the L-Edit Edit-in-place feature.

Check and correct errors that you might introduce using the DRC tools also in this cell and
make sure all signals are properly labeled.
Neuromorphic Engineering II Lab 4, Spring 2011 3

4.2 Postlab

In L-Edit open the ToolsDRC Setup dialog window, and click on the Edit button. Study
the METAL1 rules (7.1 to 7.4) and learn how to change them. This can be useful for creating
your own design kit, given the foundry specifications, improving the current setup, and
creating new rules that are not provided with the current design-kit. Hand in a printout of
part of a .cal DRC command file with modified METAL1 rules where the minimal spacing
is 0.6 um.

4.3 What we expect you to remember

What are design rules? Who provides them? What is a DRC? What tools can be used
to check design rule correctness? What can be checked and what cannot be checked with
DRC tools? What is an antenna rule and why is it necessary? What is a density rule and
what process step necessitates it? How can latch-up occur? Specifically by which parasitic
bipolar circuit and non-ideality in bulk connections. What are poly stringers and why do
they cause problems in double-poly processes?

4.4 Next Week

Layout vs. Schematic (LVS): learning to compare two SPICE net lists to determine if they
contain equivalent circuit descriptions.

You might also like