ECE 274 - Digital Logic: Controller Datapath
ECE 274 - Digital Logic: Controller Datapath
Controller Datapath
Lecture 8
Data Inputs
Parallel Load Register
Shift Registers
Multifunction Registers
Multifunction Register Design Process
Control Outputs
Control Inputs
Data Outputs
1 2
3 4
Basic parallel load register example. Basic register example: (a) timing diagram, and (b) the contents of each register.
5 6
Digital Design Digital Design
Datapath Components: Design Example: Weight Sampler Datapath Components: Design Example: Weight Sampler
Weight Sampler:
Functional Description:
9 10
8
From the cars
T I0 8-bit
mirror display
To the above-
A 8 4x1 8
I1 D
I 8 D
I2
? M 8
I3 s1 s0
x y
Well des ign
this later
button
11 12
Digital Design Digital Design
Datapath Components: Design Example: Above Mirror Display Datapath Components: Electronic Checkerboard
Circuit
Circuit
User
Input
13 14
Right shift example: (a) sample contents before and after a right shift, and
Checkerboard after loading registers for initial checker positions. (b) bit-by-bit view of the shift.
17 18
Digital Design Digital Design
Datapath Components: Computer Components: Shift Registers Datapath Components: Computer Components: Rotator
Shift register: (a) implementation, (b) paths when shr=1, and (c) block symbol.
19 20
Operation Table
23 24
Digital Design Digital Design
Datapath Components: Computer Components: Multifunction Registers Datapath Components: Computer Components: Multifunction Registers
25 26
A small combinational circuit maps the control inputs ld, shr, and shl to the mux Truth tables describing operations of a register with left/right shift and parallel load along
select inputs s1 and s0. with the mapping of the register control inputs to the internal 4x1 mux select lines: (a)
complete operation table defining the mapping of ld, shr, and shl to s1 and s0, and
(b) a compact version of the operation table.
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29 30
Digital Design Digital Design
Datapath Components: Using Multifunction Design Process Datapath Components: Using Multifunction Design Process
31 32
s2 = clr*set
s1 = clr + clr*set*ld*shl
s0 = clr + clr*set*ld
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Digital Design
Datapath Components: Using Multifunction Design Process
clr*set=>
clr, set,
clr + clr*set*ld*shl=>
ld, shl
clr + clr*set*ld=>
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