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Experiment - 09: Aim: Tools: Methodology: Theory: Ring Counter

The document describes an experiment to design and simulate 4-bit ring and Johnson counters using Xilinx ISE design software. It provides the theory of operation for each counter, their circuit diagrams, Verilog code, RTL schematics, test benches, and output waveforms. The ring counter connects the output of the last register to the first register input, while the Johnson counter inverts the output before connecting it to the input. Both counters were successfully designed and their functionality was verified through simulation.

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524 views6 pages

Experiment - 09: Aim: Tools: Methodology: Theory: Ring Counter

The document describes an experiment to design and simulate 4-bit ring and Johnson counters using Xilinx ISE design software. It provides the theory of operation for each counter, their circuit diagrams, Verilog code, RTL schematics, test benches, and output waveforms. The ring counter connects the output of the last register to the first register input, while the Johnson counter inverts the output before connecting it to the input. Both counters were successfully designed and their functionality was verified through simulation.

Uploaded by

atul
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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EXPERIMENT - 09

AIM: Design and simulation of ring and Johnson counter

TOOLS: Xilinx ISE Design Software

METHODOLOGY: Behavioral

THEORY: RING COUNTER-A ring counter is a type of counter composed of a type of


circular shift register. The output of the last shift register is fed to the input of the first register.
The Hamming distance of an Overbeck counter is 2, the Hamming distance of a Johnson counter
is 1. A straight ring counter or Overbeck counter connects the output of the last shift register to
the first shift register input and circulates a single one (or zero) bit around the ring. For example,
in a 4-register one-hot counter, with initial register values of 1000, the repeating pattern is: 1000,
0100, 0010, 0001, 1000... . Note that one of the registers must be pre-loaded with a 1 (or 0) in
order to operate properly.

JOGNSON COUNTER-A twisted ring counter, also called switch-tail ring counter, walking ring
counter, Johnson counter.A Johnson counter is a different sort of ring counter, where the inverted
output of the shift register is fed back to the input. The MOD of the Johnson counter is 2n if n
flip-flops are used. The main advantage of the Johnson counter counter is that it only needs half
the number of flip-flops compared to the standard ring counter for the same MOD.

CIRCUIT DIAGRAM :

RING COUNTER-

Fig 9.1 block diagram of 4 bit ring counter

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JOHNSON COUNTER-

Fig 9.2 block diagram of 4 bit Johnson counter

VERILOG CODE:

1-RING COUNTER-
module ring( input clk,input rst,output q0, output q1, output q2, output q3);

df d1(q0,clk,rst,q3);

df d2(q3,clk,rst,q2);

df d3(q2,clk,rst,q1);

df2 d4(q1,clk,rst,q0);

endmodule

module df(input d,input clk1,input rst1,output reg q);

initial

begin q<=1'b0; end

always @(posedge clk1,posedge rst1)

if(rst1==1)

begin q=1'b0; end

else

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begin q=d; end

endmodule

module df2(input d,input clk1,input rst2,output reg q);

initial

begin q<=1'b0; end

always @(posedge clk1,posedge rst2)

if(rst2==1)

begin q=1'b1; end

else

begin q=d; end

endmodule

RTL:

Fig 9.3 RTL of 4 bit ring counter

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TEST BENCH:
initial begin

rst = 0;#100;

rst = 1;#100;

rst = 0;#100;

end

initial clk=1'b0;

always

#100 clk=~clk;

endmodule

OUTPUT WAVEFORM:

Fig 9.4 Output of 4 bit ring counter

VERILOG CODE:

JOHNSON COUNTER-
module john(input clk,input rst,output q0,output q1,output q2,output q3);

dff d1(~q3,clk,rst,q0);

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dff d2(q0,clk,rst,q1);

dff d3(q1,clk,rst,q2);

dff d4(q2,clk,rst,q3);

endmodule

module dff(input d,input clk1,input rst1,output reg q);

initial

begin q<=1'b0; end

always @(posedge clk1,posedge rst1)

if(rst1==1)

begin q=1'b0; end

else

begin q=d; end

endmodule

RTL:

Fig 9.5 RTL of Johnson counter

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TEST BENCH:
initial begin

// Initialize Inputs

rst = 0;#100;

rst = 1;#100;

rst = 0;#100;

end

initial clk=1'b0;

always

#100 clk=~clk;

endmodule

OUTPUT :

Fig 9.6 Output of 4 bit johnson counter

RESULT: 4 bit ring and Johnson counter are successfully designed using Xilinx.

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