Scribd Logo
Upload

Welcome to Scribd!

  • 74 views

    Pune - University - Vlsi Book - Study - Plan Xerox

    Uploaded by

    anshu4u06
    This document outlines the lecture topics, books, and page numbers for 6 units covering VHDL modeling and design flow, finite state machines and sequential logic principles, programmable logic devices, system on chip, CMOS VLSI, and testability. The units cover topics such as VHDL modeling styles, design flows, FSM design and case studies, PLD and FPGA architectures, SOC design principles, CMOS design techniques, and approaches for designing testable circuits. Reference books include titles focused on digital design, VHDL, CMOS design, and testability.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd

    Pune - University - Vlsi Book - Study - Plan Xerox

    Uploaded by

    anshu4u06
    74 views4 pages
    This document outlines the lecture topics, books, and page numbers for 6 units covering VHDL modeling and design flow, finite state machines and sequential logic principles, programmable logic devices, system on chip, CMOS VLSI, and testability. The units cover topics such as VHDL modeling styles, design flows, FSM design and case studies, PLD and FPGA architectures, SOC design principles, CMOS design techniques, and approaches for designing testable circuits. Reference books include titles focused on digital design, VHDL, CMOS design, and testability.

    Original Description:

    vlsi_pune_university_study_plan

    Original Title

    Pune_university_Vlsi Book_study_plan Xerox

    Copyright

    © © All Rights Reserved

    Available Formats

    DOC, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document outlines the lecture topics, books, and page numbers for 6 units covering VHDL modeling and design flow, finite state machines and sequential logic principles, programmable logic devices, system on chip, CMOS VLSI, and testability. The units cover topics such as VHDL modeling styles, design flows, FSM design and case studies, PLD and FPGA architectures, SOC design principles, CMOS design techniques, and approaches for designing testable circuits. Reference books include titles focused on digital design, VHDL, CMOS design, and testability.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    74 views4 pages

    Pune - University - Vlsi Book - Study - Plan Xerox

    Uploaded by

    anshu4u06
    This document outlines the lecture topics, books, and page numbers for 6 units covering VHDL modeling and design flow, finite state machines and sequential logic principles, programmable logic devices, system on chip, CMOS VLSI, and testability. The units cover topics such as VHDL modeling styles, design flows, FSM design and case studies, PLD and FPGA architectures, SOC design principles, CMOS design techniques, and approaches for designing testable circuits. Reference books include titles focused on digital design, VHDL, CMOS design, and testability.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    of 4

    UNIT: I

    VHDL Modeling and Design Flow


    Lecture no. Topic Name Book Page No.
    1 Introduction to VLSI T1 264-267
    2 complete VLSI design flow T1 266-268
    (with reference to an EDA R1 274
    tool)
    3 Sequential, Data flow, and T1 268-301
    Structural Modeling
    R1 15-70
    4 Functions, Procedures, R1 109-143 &
    attributes 205-224
    5 Test benches, R1 330-349
    Synthesizable, and non
    synthesizable statements
    6 packages and R1 173-180
    configurations Modeling in
    VHDL with examples of
    circuits such as counters
    7 shift registers, bidirectional R4 378-388
    bus examples

    Unit-II
    FSM And Sequential Logic Principles
    Lecture Topic Name Book Page No.
    no.
    8 Sequential Circuits T1 708-709
    R4 429-433
    9 Meta-stability Synchronization T1 764-773
    R4 639-644
    10 Design of Finite State Machines, and State R4 470-480
    minimization
    11 FSM CASE STUDIES - Traffic Light control R2 104-107
    12 Lift Control R2 373-387
    13 UART STA and DTA R2 28-34 &
    373-387

    Unit-III
    Programmable Logic Devices
    Lecture no. Topic Name Book &
    Page No.
    14 Introduction to the PLDs Available in Xilinx, Actel,
    Altera data sheets
    15 Study of architecture of Available in Xilinx, Actel,
    CPLD Altera data sheets
    16 Study of the Architecture Available in Xilinx, Actel,
    of FPGA Altera data sheets
    17 Study of the Architecture Available in Xilinx, Actel,
    of FPGA Altera data sheets

    Unit IV
    System On Chip
    Lecture no. Topic Name Book Page No.
    18 One, two phase clock, Clock T3 263-265 &376
    distribution
    Power distribution, Power T3 373-398 &229
    optimization
    SRC and DRC
    19 Design validation T3 299
    Global routing, Switch box T3 370-372
    routing
    20 Off chip connections T3 383-391
    21 I/O Architectures T3 383-391
    22 Wire parasitic T3 65
    23 EMI immune design concept T2
    24 Study of memory-Basics of T2 563-579 &
    memory includes types of 585-588
    memory cells and memory
    architectures
    25 Types of memory, based on T2 563-579, 582 &
    architecture specific and 585-588
    application specific viz. SRAM,
    DRAM, SDRAM, FLASH, FIFO.
    Unit V
    CMOS VLSI
    Lecture no. Topic Name Book Page No.
    26 CMOS parasitics T2 58-59
    equivalent circuit T2 51-58
    27 body effect T2 51
    Technology Scaling T2 250-255
    28 parameter T2 250-255
    29 Detail study of Inverter T2 61-72
    Characteristics
    30 power dissipation, power T2 231-237
    delay product
    31 CMOS combinational R8 275-306
    logic design and W/L
    calculations
    32 Transmission gates R8 307
    Introduction to CMOS T2 142-156
    layout

    Unit VI
    Testability
    Lecture no. Topic Name Book Page No.
    33 Need of Design for testability R4 665-668
    Introduction to Fault T2 475
    Coverage
    Testability R4 654-668
    34 Design-for-Testability, R4 654-668
    Controllability and
    Observability T2 474-475

    35 Stuck-at Fault Model, Stuck- R4 654-655


    Open and Stuck-Short faults
    Boundary Scan check R2 351-357
    R4 676
    36 JTAG technology T1 350
    37 TAP Controller and TAP R2 361
    Controller State Diagram.
    Scan path, Full and

    38 TAP Controller Partial scan, T2 495-498 & 501


    BIST

    Books:
    T1. John F. Wakerly, Digital Design, Principles and Practices, Prentice
    Hall Publication
    T2. Neil H. E Weste and Kamran Eshraghian, Principles of CMOS
    VLSI Design.
    T3. Wyane Wolf, Modern VLSI Design
    Reference Books:
    R1. Perry VHDL.
    R2. Charles Roth, Digital System Design using VHDL, McGraw hill.
    R3. Stephen Brown and Zvonko Vranesic, Fundamentals of Digital
    logic with VHDL Design.
    R4. Sung-Mo(Steve) kang, Yusuf Leblebici, CMOS Digital Integrated
    Circuits.

    You might also like