IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 26, NO.

3, JULY 2011 1999

A Hybrid Framework for Fault Detection,

Classification, and LocationPart II:
Implementation and Test Results
Joe-Air Jiang, Member, IEEE, Cheng-Long Chuang, Member, IEEE, Yung-Chung Wang, Chih-Hung Hung,
Jiing-Yi Wang, Chien-Hsing Lee, Senior Member, IEEE, and Ying-Tung Hsiao, Member, IEEE

AbstractThis paper is the second part of a series of two papers insulation, and short circuits resulting from attacks of birds or
addressing a hybrid framework for achieving fault detection, other objects. Modern digital relay technologies have provided
classification, and location, simultaneously. The proposed frame- various solutions to prevent power grids from major blackouts.
work is formed by a variety of analysis techniques, including
symmetrical component analysis, wavelet transforms, principal Due to the large geographical sizes and network complexities,
component analysis, support vector machines, and adaptive struc- modern power systems are still subject to threats of faults
ture neural networks. In our previous paper, the mathematical induced by natural and/or external interferences. In order to
foundation of this framework with numerical results obtained improve the overall quality of power supply, power companies
by computer-based simulations has been presented. This paper need to install adequate monitoring devices to quickly detect
is devoted to discuss the field-programmable gate-array imple-
mentation and experimental results acquired by using real-world the occurrence of faults and isolate the faulty region from the
scenarios. The hardware implementation of the runtime training power system. With accurate fault detection, classification, and
technique in the proposed framework is an evolvable hardware location systems, the restoration process can be expedited only
tested by the power signals used in a power company transmis- if the fault has been precisely located.
sion network for performance evaluation. The runtime training In this series of two papers, Part I [1] presents the theoret-
technique allows the FPGA to have learning and re-training capa-
bilities. The main purpose of this paper is to show the applicability ical foundation of the proposed hybrid framework, which pro-
of the proposed framework on a hardware platform and test the vides a generic solution for fault detection, classification, and
frameworks robustness and evolvability against noises from the location. Since this work is formulated as a data-driven system
system and measurements. equipped with a runtime training technique, fault locating in a
Index TermsEvolvable hardware, fault classification, fault de- power system is not affected by changing conditions, such as
tection, fault location, field-programmable gate array (FPGA). nonhomogeneity of lines, fault resistance, as well as load and
phase unbalance. The computer-based simulation results have
shown the effectiveness of the proposed framework in simple
I. INTRODUCTION and complex power systems.
HE reliability of electrical energy is essential for The proposed framework contains several arithmetical algo-
T economies and industrial users. Fault detection, clas-
sification, and location systems have played crucial roles to
rithms, including negative-sequence component (NSC), wavelet
transform (WT), principal component analysis (PCA), support
ensure the availability and continuity of power generation and vector machines (SVMs), and adaptive structural neural net-
transmission. However, the power transmission lines are vul- works (ASNNs). Since the runtime training technique of the
nerable to the faults caused by typhoons, earthquakes, aging of ASNNs requires a highly parallel mechanism, the ultimate per-
formance of real-time emulation of the proposed framework re-
lies on the capabilities of the underlying hardware. With ad-
Manuscript received November 16, 2010; revised February 23, 2011; ac- vanced semiconductor technologies, field-programmable gate
cepted March 15, 2011. Date of publication May 31, 2011; date of current ver-
sion June 24, 2011. This work was supported by the National Science Council arrays (FPGAs) offer a convenient and low-cost platform for
of Republic of China under Contract NSC 96-2628-E-002-252-MY3. Paper no. engineers to develop speed-up, custom-made applications with
TPWRD-00880-2010. parallel-processing capability. FPGA allows multiple compu-
J.-A. Jiang, C.-L. Chuang, C.-H. Hung, and J.-Y. Wang are with the Depart-
ment of Bio-Industrial Mechatronics Engineering, National Taiwan University, tation tasks to be simultaneously executed. Therefore, FPGA
Taipei 106, Taiwan (e-mail: [email protected]; [email protected]; ). is the most suitable device to implement the proposed hybrid
Y.-C. Wang is with Department of Electrical Engineering, National Taipei
University of Technology, Taipei 106, Taiwan (e-mail: [email protected].
framework.
tw). In this paper, we focus on the implementation aspect of the
C.-H. Lee is with the Department of Systems and Naval Mechatronic proposed hybrid framework on the FPGA platform. An FPGA-
Engineering, National Cheng Kung University, Tainan 701, Taiwan (e-mail:
[email protected]).
based experimental platform is constructed with two indepen-
Y.-T. Hsiao is with Department of Digital Technology Design, Na- dent systems as follows.
tional Taipei University of Education, Taipei 106, Taiwan (e-mail: yth- 1) Real-time power system simulator: In order to evaluate the
[email protected]). performance of the implementation of the proposed frame-
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. work, an FPGA-based real-time power system simulator
Digital Object Identifier 10.1109/TPWRD.2011.2141158 is developed to produce analog three-phase voltage and
0885-8977/$26.00 2011 IEEE
2000 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 26, NO. 3, JULY 2011

current signals obtained from MATLAB/Simulink. The

analog signals outputted by the simulator may contain an
uncertain level of noises caused by the system and signal
transmission cables. With these features, we may examine
the robustness of the proposed method against the noises.
2) Real-time fault diagnosis system: The real-time fault
diagnosis system is designed for implementing the hybrid
framework presented in the previous paper. To analyze the
fault signals in real-time fashion, the system is based on
paralleled hardware architecture with simultaneous com-
putation capabilities. The system accepts the analog signal
inputsincluding three-phase voltage and current sig- Fig. 1. Conceptual diagram of the fault diagnosis system, which comprises a
signal measurement module, a fault diagnosis module, and a graphical display
nals generated from the aforementioned real-time power module.
system simulatorusing an analog-to-digital converter
(ADC). Incorporated with a runtime training technique,
the ASNNs make this system an evolvable hardware. This
feature can progressively improve the fault-location accu-
racy of the system. A digital touch liquid-crystal display
(LCD) panel is dedicated to display the diagnosis results
(i.e., fault occurrence, fault types, and fault location) after
the proposed framework completes the analysis.
The real-time power system simulator and the real-time fault
diagnosis system are implemented by using Alteras Cyclone-II
and Stratix-III FPGAs. The computations of both systems are
based on fixed-point number representation with the purpose
of simplifying the implementations of the systems. The voltage
and current signals of a Taipower transmission network are sim- Fig. 2. Configuration of the signal measurement module. The analog signals
ulated in real time to evaluate the performance of the proposed measured from external cables are converted to digital signals by using the 14-b
framework. unsigned representation. In this module, a floating number converter is devel-
oped to transform the 14-b unsigned values to the standard double-precision
The rest of this paper is organized as follows. Section II ex- floating number according to the definition given by IEEE-754.
plains the skeletal hardware structure of the FPGA-based real-
time fault diagnosis system. Section III describes the implemen-
tation and operation details of the real-time power system simu- regarding the implementation of these modules are given in the
lator by integrating software-based MATLAB/Simulink with an following subsections.
external evolvable FPGA. Section IV provides simulation re-
sults of the two systems. The real-time simulated signals are A. Signal Measurement Module
captured by an oscilloscope to compare with the simulation In this module, three 14-b ADCs are utilized to measure sig-
results produced by MATLAB/Simulink. The fault diagnosis nals from external cables at a sampling rate of 3840 (60 cy-
system is also evaluated using the signals obtained by the afore- cles/s 64 samples/cycle) samples per second. The hardware
mentioned simulator. Conclusions are given in Section V. configuration of the signal measurement module is shown in
Fig. 2. The signal measurement module is responsible for ac-
cepting the three-phase voltage and current signals. However,
II. IMPLEMENTATION OF THE FAULT DIAGNOSIS SYSTEM
the development board (DK-DSP-3SL150N) [4] that holds the
The hardware implementation of the fault diagnosis system Stratix-III series FPGA only provides two high-speed mezza-
comprises three major modules: 1) signal measurement module, nine card (HSMC) [5] interfaces. Because of this reason, we
2) fault diagnosis module, and 3) graphical display module. The install two data conversion cards that provide four 14-b ADCs
conceptual architecture of this system is depicted in Fig. 1. The in total. Furthermore, a switch index is used to measure the
signal measurement module is built by using three integrated three-phase voltage and current signals. First, is set at 1,
14-b ADCs (AD9248) [2] produced by Analog Devices, Inc. and then the signal measurement module converts the one-cycle
The fault diagnosis module is formed by three submodules pre- three-phase voltage signals. After that, is set at 0 to mea-
sented in the previous paper, including fault detection, fault clas- sure the one-cycle three-phase current signals.
sification, and fault-location submodules. The implementation The analog signals are converted to digital signals using 14-b
of the fault diagnosis module can be achieved by completing representation as depicted in Fig. 3(a). Due to the limitation
the circuitry design of NSC, WT, PCA, SVM, and ASNN in a of the 14-b representation (i.e., the limited dynamic range),
Stratix-III series FPGA (EP3SL150F1152C4) [3] produced by such a representation is not useful in arithmetic computations.
Altera, Inc. A graphical user interface (GUI) displayed on a dig- The IEEE standard for floating-point number representation
ital touch LCD panel allows users to manipulate the system and (IEEE-754) [6], however, is the most widely used standard
shows the result of fault diagnosis. The detailed explanations for floating-point computation, followed by many hardware
JIANG et al.: HYBRID FRAMEWORK FOR FAULT DETECTION, CLASSIFICATION, AND LOCATIONPART II 2001

Fig. 3. Two simplified representations of unsigned floating numbers. (a) Four-

teen-bit representation used in the HSMC interface. (b) Sixteen-bit half-preci-
sion floating-point representation defined by the IEEE standard.

and software implementations. In this module, a converter is

designed to transform 14-b representation values into IEEE-754 Fig. 4. Schematic of the hardware implementation of the NSC. Multiplica-
tion operators in red color are complex number multipliers that encompass four
readings. The IEEE-754 standard defines various types of basic mult/div FPUs and two add/sub FPUs.
binary formats for floating-point number representation. In
order to make floating-point units (FPUs) simple, the half-pre-
cision format is utilized as illustrated in Fig. 3(b). The FPUs operation is then implemented by using four mult/div FPUs
for 16-b half-precision format have similar resolution to the and two add/sub FPUs in total.
14-b representation, and they are relatively less complex than The NSC module generates the negative sequence of the
the ordinary ones in reducing the number of utilized logic input voltages and currents. The module determines that a fault
elements. The implementation of FPU in FPGA is described in is currently occurring in transmission lines if the values of the
a supplementary document [7]. The measured data are stored in joint fault detector, calculated from differential negative-se-
an external memory module, and a unique memory address is quence voltages and currents exceed a
assigned to each set of samples. Therefore, one sampling clock threshold, which is 1 as explained in [1]. The values of and
in the HSMC interface triggers one dynamic random-access are summed together and stabilized to yield the joint fault
memory (DRAM) writing cycle via the dual-in-line memory indicator .
module (DIMM) interface. According to the ADCs speci- 2) Wavelet Analysis: In general, the wavelet transform
fication, the sampling rate of the ADCs is set to 10 million consists of two versions: continuous and discrete ones. Since
samples/s in order to maintain the dynamic of the ADCs. the continuous wavelet transform is not applicable to be imple-
Since the proposed framework requires only 64 samples/cycle, mented in an FPGA, the multilevel discrete wavelet transform
the memory address controller obtains the magnitudes of (ML-DWT) [9] is the only solution to perform wavelet anal-
, and with a sampling ysis used in the proposed framework. The coefficients of the
rate of 3840 samples/s. Following the completion of these ML-DWT can be calculated recursively as a series of convo-
measurement processes, three-phase voltages and currents are lutions and decimations in a straightforward form by using
stored in DRAM. These waveforms are then analyzed by the the well-known Mallats pyramid algorithm [10]. Based on
fault diagnosis module presented in the following subsection. this algorithm, the wavelet coefficients of the level can be
computed from the wavelet coefficients of the previous level
B. Fault Diagnosis Module by using the following equations:
1) Negative-Sequence Components: After the values of
three-phase voltages and currents are stored in the memory (1)
of the system, symmetrical component analysis is utilized to
detect transient phenomena that cause unbalanced three-phase (2)
quantities in voltage and current signals. Since NSC [8] is only
used in the fault detection module, the architecture of the NSC (3)
hardware is relatively simple as depicted in Fig. 4. Specifically,
the NSC module involves the computation of complex numbers. (4)
It is not a simple task to implement complex number math in
an FPGA. In order to comply with the rules of complex number
math, the adders that are involve in complex number math are where and are the wavelet low-pass and high-pass
implemented by using two add/sub FPUs. There are two filter coefficients obtained from the wavelet, and
types of multipliers used in this module: one is to multiply a are the approximation and detail wavelet coefficients
real number to a complex number, and the other is to multiply of voltages at the th level, and and are the
two complex numbers together. The first type can be imple- approximation and detail wavelet coefficients of currents at the
mented simply by using two mult/div FPUs for computations th level. At the output of every level, there is a downsampling
of the real and imaginary part of the results, respectively. If the operation which appears as the factor of 2 in the argument of
multiplication operation involves two complex numbers, the the filter coefficients and .
2002 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 26, NO. 3, JULY 2011

Fig. 6. Hardware architecture of implementing the PCA.

Fig. 5. Architecture of the serial-in parallel-out ML-DWT.

channel for the corresponding SIPO shift register, and the
wavelet coefficients in the SIPO shift register shift. The control
According to [1], since only the 1st and 2nd level signals of the multiplexer and the demultiplexer are generated
wavelet detail coefficients of voltages and currents (i.e., by counters with discrete logic circuits to control the sequence
, and ) are used for further of operations. Since the sampling rates of and are
analysis, we present a fast and efficient method to perform relatively lower than the operating frequency of the FPGA,
ML-DWT based on Mallats recursive pyramid algorithm. the proposed system can perform ML-DWT in real time. The
In principle, in order to implement ML-DWT at a maximum FPUs are used in the filter block only; there are four mult/div
speed, a serial-in parallel-out (SIPO) architecture, as illustrated FPUs and three add/sub FPUs used in this block. The filter
in Fig. 5, is used to compute the WT coefficients. has fixed coefficients; consequently, these coefficients can be
A pipeline structure is used in this design. The new input data easily implemented using fixed wires.
values and are loaded into the deepest place of 3) Principal Component Analysis: In the proposed frame-
the corresponding shift register at every time period. The length work, PCA is used to reduce the dimensionality of the wavelet
of the shift registers is 4 words, which is the same as the length coefficients produced by ML-DWT. For the hardware designs
of the Daubechies-4 orthogonal wavelets. Data are fed to the of PCA, the most computationally intensive part of PCA is to
wavelet high-pass filter according to a sequence as perform eigenvector calculations and sorting. In fact, the calcu-
lation of eigenvectors is sequential and hard to parallelize. To
implement PCA in the FPGA, a multistage pipeline structure is
presented and depicted in Fig. 6.
First, the wavelet coefficients
produced in the
most recent cycle are used in the PCA. In order to compute
eigenvalues and eigenvectors, the size of these wavelet
coefficients is equalized to 64 samples using a simple linear
interpolation technique. The wavelet coefficients are then
organized into three matrices according to their phases ,
and . The mean centered coefficient matrices , and
are fed to the computation module of the PCA in a
sequence controlled by a multiplexer. The module is
designated to solve eigenvalues and eigenvectors by linear
algebra. The most significant eigenvalue and its corresponding
eigenvector are used to project the wavelet coefficients onto
the vectors in a new feature space (i.e., , and .A
demultiplexer is responsible for storing the results into the
corresponding registers for further analysis.
The computation of PCA is implemented via a series of com-
plex and iterative processes. Although there are many levels of
parallelism used to exploit the process of PCA, a multistage
pipeline structures is still required to reduce the size of the cir-
A multiplexer is utilized to control the sequence of taking input cuit. The parallelism used in PCA can be found in many steps in
coefficients from the SIPO shift registers ( , Fig. 6. For example, the calculation of the mean value of a vector
and ). The output of the wavelet high-pass filter is of size (e.g., and ) can be accomplished
passed through a demultiplexer to the appropriate output with an adder tree that scales with the depth of the adder tree
JIANG et al.: HYBRID FRAMEWORK FOR FAULT DETECTION, CLASSIFICATION, AND LOCATIONPART II 2003

TABLE I
PIPELINE STAGES BREAKDOWN IN THE PROCESS OF PCA

Fig. 7. Architecture for the calculation of the feedforward classification stage

of the SVM classifiers.
. Subtracting the mean value of a vector from itself
in the centering process is performed in parallel. Furthermore, if
the vector has a size of (e.g., ), then subtracting op- by one of the aforementioned SVMs. Once an SVM iden-
erations are performed in parallel to generate . In this study, tified a fault, its corresponding ASNN is then activated to
the value of is 64, the sampling rate per cycle. The number of estimate the fault location using features of the fault signal
the pipeline stages for each operation in PCA is summarized in , and
Table I. extracted by PCA. The benefit of using ASNNs is that the
From a hardware perspective, the implementation of PCA re- dynamic structuring mechanism allows the neural networks to
quires a large number of pipeline stages to reduce the latency reinforce their learning capacity when needed.
of the analysis. In addition, the PCA module used 48 982 logic The design of neuron in the ASNN has reconfigurable neural
elements in the Stratix-III FPGA. The maximum operational links, and the number of neurons connected to the network is
frequency is 76 MHz, which benefits from the large number of variable. Due to limited hardware resources, it is impossible to
pipeline stages. implement these adaptive features in FPGA only using hard-
4) Support Vector Machine: The SVM [11] used in this study ware resources. To overcome this difficulty, a scheduling-based
includes two stages: machine learning stage and feedforward computing mechanism is designed to achieve the functions of
classification stage. In the machine learning stage, support vec- ASNNs using embedded memory blocks and minimal hard-
tors are determined with a nonzero value and a bias term ware resources. In our implementation, weights and biases
by using the method described in our previous paper [1], where are mapped onto the memory blocks (also known as TriMa-
and represent the phase indicator and the index of the support trix Blocks in Stratix-III FPGA). The Stratix-III FPGA used
vector, respectively. Since it is not necessary to iteratively train in this study has 72 M144K blocks (2K 72), which allows
the SVM, the calculations of and for each support vector storing 18 432 half-precision floating-point numbers. In our
are performed in a computer in order to reduce the complexity of implementation, the maximum number of incoming links for
the proposed system. After the machine-learning stage is com- each neuron is 10, and each neuron is accompanied with three
pleted, the values of and for each support vector are stored free connectors that are able to seek new connections between
in the memory block of the FPGA. two neurons. Therefore, 22 parameters (13 weights on 10
In the second stage, the first two coordinates of the principal neural connections and three free connectors, 1 bias, coordi-
component scores that describe the feature of the fault signals nates of the neurons, and coordinates of three free connectors)
( , and ) are required to express the characteristics of each neuron. The
are inputted to the SVM for fault classification. The overall ar- activation functions of the neurons in the ASNNs are imple-
chitecture for the calculation of the feedforward classification mented using lookup tables. The variables used for updating
stage of the SVM classifiers is illustrated in Fig. 7. The decision weights and biases of the neural connections are stored in
boundaries in each SVM are used to determine whether the fea- FPGA using registers. The fault-location module is built using
ture of the fault signals suits the regions formed by the decision six ASNNs, and the maximum number of neurons is 50 for
boundaries. The output provides each ASNN.
the confidence of the fault classification results on each type of In order to realize the runtime training technique in ASNNs, a
fault event. hardware implementation of ASNN is conducted in the FPGA.
The hardware implementation of the feedforward classifica- The hardware module that models the behaviors of 50 neurons is
tion stage of the SVM classifiers can be accomplished by using shared by the six ASNNs in the fault-location module. Once an
the 10-stage pipeline architecture. The operating frequency of ASNN is activated by a corresponding SVM, the fault-location
this module can reach to 82 MHz with 10 583 logic elements module loads all parameters and input vectors to the hardware
used in total. of ASNN, and then elaborates the function of ASNN to produce
5) Adaptive Structure Neural Networks: There are six the output that indicates the location of the currently occurring
ASNNs [12] used in the proposed system for the purpose fault in the transmission line. If the runtime training technique
of performing fault location when a fault event is classified is activated, using prior knowledge of the training patterns, the
2004 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 26, NO. 3, JULY 2011

Fig. 8. GUI interface of the proposed system on a touch LCD panel. The LCD
panel is mounted on an Altera development board (DE2-70) that is responsible
for displaying the output screen on the LCD panel. The GUI interface is also
used to detect the touch signals from the LCD panel and transmits the signals to
the Stratix-III FPGA board for further use.

circuit computes the adjusted values for weights, biases, and co-
ordinates of the neurons and the free connectors and then up-
dates the values of these parameters in the memory blocks of
the FPGA.
6) Displaying Diagnosis Results: A graphical user interface
(GUI) is designed to display all diagnosis results of the power
waveform measured from the simulated power cable. The GUI
provides a convenient way to visualize the diagnosis results of
the proposed system using a touch LCD panel, as shown in
Fig. 8. With the proposed system, system diagnosis engineers Fig. 9. Topology of a real 345-kV Taipower power transmission network
are able to acquire all important information regarding a fault system encountered in Taiwan.
(i.e., fault occurrence, fault type, and fault location).

III. IMPLEMENTATION OF THE REAL-TIME waveforms. The analog signals are sampled by using a 14-b
POWER SYSTEM SIMULATOR ADC, and the sampled power waveform is stored in the memory
module, and then the waveforms are normalized to their original
In this section, a real-time power system simulator that in-
amplitude range based on the rms power of the signal precalcu-
corporates an FPGA evaluation board and a computer are intro-
lated in MATLAB/Simulink. In this way, noise is introduced by
duced. The presented simulator is used to simulate power wave-
the analog-to-digital measurement and the quantization process
forms using a power system network simulated by MATLAB/
is taken into account while evaluating the performance of the
Simulink. A real Taipower 345-kV power transmission network
fault diagnosis system presented in the previous section.
established by Taipower in Taiwan is adapted to model the sim-
ulated power system network. The loads connected at each bus
are around 2000 MW in total, the base current . IV. EXPERIMENTAL RESULTS
The topology of the power system is illustrated in Fig. 9. There The setup of the proposed systems is shown in Fig. 11. The
are seven generators (three hydropower plants, two fossil-fu- overall hardware resources used in the Stratix-III FPGA are
elled power plants, and two nuclear power plants) and seven 92.8% (105 427/113 600) ALUTs, 4608 registers, 48 memory
power substations. They are connected by 39 transmission lines blocks, and 618 pins. The operation frequency of the Stratix-III
and 24 buses. The lengths and parameters of the transmission FPGA is 72.46 MHz, benefitted by the pipeline designs of the
lines are summarized in Table II. The total length of the power internal components. The entire analysis process of the pro-
transmission lines is 939.61 km, and the measurement units are posed system is completed in 0.0001 s after the ADC mea-
deployed to all buses in the power system. sures a new sample from the external cables. For each trans-
The schematic of the real-time power system simulator is de- mission line in the simulated power system, different faults are
picted in Fig. 10. The three-phase power waveforms are digi- randomly given to produce training and test samples to evaluate
tally simulated by MATLAB/Simulink. The power waveforms the performance of the proposed diagnosis system. Each sample
are normalized into the range of and 1, and then they are is generated for a different type of fault at a random fault loca-
sent to the memory module of the real-time power system sim- tion (from 0 to 1 p.u.) and random fault inception angles (0 to
ulator via the universal serial bus connector and the JTAG port 359 ). There are 240 000 power waveforms generated (10 000
on the development board (DK-DSP-3SL150N). The samples samples per type of fault and 120 000 samples for a normal
of the digital waveforms are consecutively transmitted to the condition) via MATLAB/Simulink. We train the parameters of
14-b DAC via the HSMC interface to simulate analog power SVMs and ASNNs on a computer using half of the samples
JIANG et al.: HYBRID FRAMEWORK FOR FAULT DETECTION, CLASSIFICATION, AND LOCATIONPART II 2005

TABLE II
PROFILE OF THE 345-kV TAIPOWER POWER TRANSMISSION NETWORK SYSTEM USED IN THIS STUDY

Fig. 10. Schematic of the real-time power system simulator.

Fig. 11. Setup of the proposed systems. (a) Setup of the proposed system by
integrating a Stratix-III FPGA evaluation board (DK-DSP-3SL150N) and a Cy-
clone-II FPGA development board (DE2-70) that is responsible for displaying
measured by the 14-b ADC in order to take measurement errors diagnosis results. (b) Setup of the Stratix-III FPGA board.
into account. Each training dataset consists of 5 000 fault wave-
forms and 5 000 normal waveforms. After the training process is
completed, all parameters are transmitted to the memory module ples are used to test the performance of the proposed diagnosis
of the FPGA board. For validation purposes, half of the sam- system.
2006 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 26, NO. 3, JULY 2011

TABLE III
EVALUATION RESULTS OF THE PROPOSED DIAGNOSIS SYSTEM USING THE WAVEFORMS GENERATED BY THE REAL-TIME POWER SYSTEM SIMULATOR

In order to evaluate the performance of the proposed diag- with 5000 fault waveforms and 5000 normal waveforms is gen-
nosis system, three performance indices are defined erated for retraining of the proposed diagnosis system via the
runtime training technique in ASNN. The averaged location er-
Sensitivity % (5) rors are further reduced to 0.43%.
Specificity % (6) The performances of the proposed diagnosis system in all
Location Error (7) transmission lines in the power system are summarized in
Table IV. The proposed system performs well in fault detection;
where TP, FP, TN, and FN represent the numbers of true posi- the averaged detection accuracy is 99.9%. Regarding the fault
tives, false positives, true negatives, and false negatives, respec- classification, the averaged sensitivity and specificity of the
tively. and are the location errors yielded by the proposed system over the entire power system are 99.78% and
two measurement units closest to the real fault location in the 99.87%, respectively. The averaged fault-location error is around
system, which can be formulated as 0.47%. The response time of detecting a fault is around 0.0005 s,
and the proposed system requires a one-cycle time period to
% (8) identify and locate the fault. The hardware implementation of
the proposed fault diagnosis system thus provides a promising
where represents the location error yielded by the mea- performance in fault detection, classification, and location.
surement unit location at terminal is true fault location, and
is the estimated fault location yielded by the proposed frame- V. CONCLUSION
work. In addition, the proposed framework in both measurement This paper is the second part of the two paper series. The major
units must simultaneously detect and correctly classify the fault; contribution of this paper is to present a hardware implementa-
otherwise, the result would be treated as a false negative. tion of the methodologies proposed in the first part of the series.
The proposed diagnosis system is initialized with 6 ASNNs A fault diagnosis system and a real-time power system simulator
that contains 50 neurons each (300 neurons in total). After the are designed and implemented using a Stratix-III FPGA evalua-
proposed diagnosis system is properly trained by the training tion board. A Cyclone-II development board is also incorporated
dataset, we validate the proposed system by applying it to the to provide a graphical user interface (GUI) on a touch LCD
test dataset. The experimental results over all transmission lines panel that shows the diagnosis results yielded by the presented
are summarized in Table III. The results show that the perfor- system. The proposed system consists of several algorithms (i.e.,
mance of the proposed diagnosis system is comparable with symmetrical component analysis, multilevel wavelet transforms,
the computational results presented in Part I of the two paper principal component analysis, support vector machine, and adap-
series [1]. The proposed system is able to detect, classify, and tive structure neural networks). The overall hardware resources
locate faults under various types of fault conditions. The aver- used in the Stratix-III FPGA are 92.8% (105,427/113,600)
aged detection accuracy of the proposed system is 99.9%. The ALUTs, 4608 registers, 48 memory blocks, and 618 pins.
averaged sensitivity and specificity of the proposed diagnosis The performance of the proposed system is evaluated by
system are 99.75% and 99.86%, respectively. The averaged lo- using the waveforms simulated based on a real 345-kV Taipower
cation error is close to 0.61%. Furthermore, 10 000 power wave- power system. The proposed system is able to directly mea-
forms are generated after giving random types of faults to each sure external analog signals to perform fault diagnosis. The
transmission line in the power system; of 50% among all sam- response time of detecting a fault is around 0.0003 s, and the
ples are fault waveforms, and the rest are waveforms in the proposed system requires one-cycle time period to identify and
normal condition. Furthermore, an additional training dataset locate the fault. The detection accuracy, sensitivity, specificity,
JIANG et al.: HYBRID FRAMEWORK FOR FAULT DETECTION, CLASSIFICATION, AND LOCATIONPART II 2007

TABLE IV
EVALUATION RESULTS OF THE PROPOSED DIAGNOSIS SYSTEM IN EACH TRANSMISSION LINE OF THE SIMULATED POWER SYSTEM

and location error of the diagnosis system are 99.9%, 99.7%, [4] Altera Corporation. (2008, Nov.). , Stratix III DSP development kit
99.8%, and 0.5%, respectively. datasheet. [Online]. Available: http://www.altera.com/products/de-
vkits/altera/kit-st3-dsp.html
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sion lines is presented. The evaluation results presented in Part I [6] IEEE Standard for Floating-Point Arithmetic, (Standards style), IEEE
of the series show that the proposed system is suitable to simple Std. 754, 2008.
[7] J. A. Jiang, C. L. Chuang, Y. C. Wang, C. H. Hung, J. Y. Wang, C. H.
and complex power systems. In Part II, we have shown that the Lee, and Y. T. Hsiao, Supplementary document for a hybrid frame-
proposed system and its runtime training technique also work work for fault detection, classification, and locationPart II: Imple-
well in real-world scenarios using the simulated power wave- mentation and test results, Feb. 2011. [Online]. Available: http://bem.
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2008 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 26, NO. 3, JULY 2011

Joe-Air Jiang (M01) was born in Tainan, Taiwan, Chih-Hung Hung received the B.S. degree in elec-
in 1963. He received the M.S. and Ph.D. degrees trical engineering from National Taipei University of
in electrical engineering from National Taiwan Technology, Taipei, Taiwan, in 2008 and the M.S. de-
University (NTU), Taipei, Taiwan, in 1990 and 1999, gree in bioindustrial mechatronics engineering from
respectively. National Taiwan University, Taipei, in 2010.
From 1990 to 2001, he was with Kuang-Wu His research interest is in the area of integrated-cir-
Institute of Technology, Taipei. Currently, he is cuit design, power systems, mechatronics, and wire-
a Professor of Bioindustrial Mechatronics Engi- less sensor networks.
neering, NTU, where he is an active researcher.
His specialties in power transmission systems are
computer relaying, solar generation systems, fault
detection, fault classification, fault location, power-quality event analysis, and
smart-grid systems. His areas of interest are diverse and cover wireless sensor
network (WSN) technology, biomechatronics, neuroengineering, bioeffects of
electromagnetic wave, automatic systems for agroecological monitoring with Jiing-Yi Wang received the B.S. degree in electrical
WSN, and low-level laser therapy. engineering from Chung Yuan Christian University,
Dr. Jiang was the recipient of the Best Paper Award (entitled Jan Ten-You Taoyang, Taiwan, in 2008 and the M.S. degree
Paper Award) from the Chinese Institute of Engineers in 2002, the Best Young in bioindustrial mechatronics engineering from
Researcher Award from the Power Engineering Division of the National Sci- National Taiwan University, Taipei, Taiwan, in 2010.
ence Council (NSC) in 2002, the Prize Paper Award from IEEE/Power Engi- His research interest is in the area of integrated-
neering Society Transmission and Distribution Conference and Exhibition in circuit design, electromagnetism, mechatronics, and
2002, the NTU Excellent Teaching Award in 2004, the Best Paper Award from wireless sensor networks
the Journal of Formosan Entomology, Taiwan Entomological Society, in 2007,
the Best Paper Award from the International Seminar on Agricultural Structure
and Agricultural Engineering in 2007 (IS-ASAE 2007), the Best Paper Award
from theWorkshop on Consumer Electronics in 2008 (WCE 2008), the Annual
Best Paper Award from Taiwan Society of Naval Architects and Marine Engi-
neers in 2010, and the Academic AchievementAward from the Chinese Institute
Chien-Hsing Lee (S93-M98-SM06) was born in
of Agricultural Machinery in 2010. Currently, he is the Principal Investigator of
Pingtung, Taiwan, on June 13, 1967. He received the
several large-scale integration projects funded by the NSC and the Council of
B.S. degree in electrical engineering from Arizona
Agriculture of the Executive Yuan, Taiwan.
State University, Tempe, in 1993 and the M.S.E.E.
and Ph.D. degrees from the Georgia Institute of Tech-
nology, Atlanta, in 1995 and 1998, respectively.
Currently, he is an Associate Professor at National
Cheng-Long Chuang (S04-M11) received two Cheng Kung University, Taipei, Taiwan. His research
B.S. degrees in electrical engineering and com- interests are power system grounding analysis, power
puter science and information engineering from system transient modeling, power quality, and appli-
Tamkang University, Taipei, Taiwan, in 2003, the cations of wavelet theory in power systems.
M.S. degree in electrical engineering from Tamkang
University, Taipei, Taiwan, in 2005, and two Ph.D.
degrees in biomedical engineering and bioindustrial
mechatronics engineering from National Taiwan
Ying-Tung Hsiao (M92) received the B.S. degree
University, Taipei, in 2010.
in electrical engineering from National Taiwan In-
Currently, he is a Postdoctoral Research Fellow
stitute of Technology, Taipei, Taiwan, in 1986 and
with the Department of Bioindustrial Mechatronics
the M.S. and Ph.D. degrees in electrical engineering
Engineering, National Taiwan University. He is also an Adjunct Assistant
from National Taiwan University in 1989 and 1993,
Professor in the Department of Computer Science, National Taipei University
respectively.
of Education, Taipei. His research interests are in the areas of power systems,
Subsequently, he joined the faculty of St. Johns
multiagent systems, cryptography, optimal theory, wireless communications,
and St. Marys Institute of Technology and was a Pro-
integrated-circuit design, cognitive psychology, artificial intelligence, as well
fessor of Electrical Engineering at Tamkang Univer-
as bioinformatics and neuroscience.
sity, Taiwan. Currently. he is a Professor and Chair
in the Department of Digital Technology Design and
a joint Professor in the Department of Computer Science and Information, Na-
tion Taipei University of Education. His research interests include power system
Yung-Chung Wang received the M.S. and Ph.D. de- analysis, optimal theory, and motor control.
grees in electrical engineering from National Tsing
Hua University, Hsinchu, Taiwan, in 1990 and 2000,
respectively.
From 1990 to 2001, he was a Research Engineer
with the Chung-Hwa Telecommunication Labo-
ratory, where he was engaged in research on the
development of ATM switching systems and IP
switch router systems. Since 2001, he has been with
the Department of Electrical Engineering, National
Taipei University of Technology (NTUT), Taipei,
Taiwan, where he is a Full Professor. His research interests include wireless
networks, optical networks, and queuing theory and performance evaluation of
communication networks.