AIM OF THE EXPERIMENT:-Binary To Decimal, Gray Code Apparatus Required

AIM OF THE EXPERIMENT:- Binary to decimal, gray code
hexadecimal, and gray code to binary using Spartan 3E board.

APPARATUS REQUIRED:-
1. XILINX ISE DESIGN SUITE 14.7
2. SPARTAN 3E BOARD
THEORY:- The Spartan-3E Starter Kit board highlights the
unique features of the Spartan-3E FPGA family and provides a
convenient development board for embedded processing
applications. This board is logic Optimized:-
For applications where logic densities matter more than I/O
count
Ideal for logic integration, DSP co-processing and
embedded control, requiring significant processing and
narrow or few interfaces.
The board has 4 slide switches which are programmed to send
binary input to the board. Depending on the combination of
on/off switches the respective binary input is send to the
program.
The push button switches are used as a case selector to choose
either binary to decimal, or binary to hexadecimal, gray code or
gray code to binary.
Each decimal or hexadecimal number is displayed on the lcd
display mounted on the board and each binary or gray code
representation of the input is showed in the LEDs off the
board.
PROGRAM:-
binaryconv.vhd
--------------------------------------------------------------------------
--------
-- Company:
-- Engineer:
--
-- Create Date: 22:34:41 04/10/2017
-- Design Name:
-- Module Name: binaryconv - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------
--------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity binaryconv is
port(BTN_EAST : in STD_LOGIC;
CLK_50MHZ : in STD_LOGIC;
BTN_NORTH : in STD_LOGIC;
BTN_SOUTH : in STD_LOGIC;
LCD_E: in STD_LOGIC;
LCD_RS: in STD_LOGIC;
LCD_RW : in STD_LOGIC;
BTN_WEST : in STD_LOGIC;
SW: IN STD_LOGIC_VECTOR(3 DOWNTO 0);--SWITCH "INPUT"
SF_D:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
LED:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end binaryconv;
architecture Behavioral of binaryconv is

signal S :STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S1 :STD_LOGIC_VECTOR(7 DOWNTO 0);
signal S2 :STD_LOGIC_VECTOR(3 DOWNTO 0);
begin
process (CLK_50MHZ)
begin
if BTN_NORTH='1' AND BTN_SOUTH='0' AND BTN_EAST='0' AND BTN_WEST='0' then
--BINARY TO GREY
LED(3) <= SW(3);
LED(2) <= SW(3) xor SW(2);
LED(1) <= SW(2) xor SW(1);
LED(0) <= SW(1) xor SW(0);
LED(7 DOWNTO 4)<="0000";
else
end if;
if BTN_NORTH='0' AND BTN_SOUTH='1' AND BTN_EAST='0' AND BTN_WEST='0'
then--BINARY TO DECIMAL
SF_D<="00101000";
S1<="0010" & SW;
SF_D<=S1;
else
end if;
then--GRAY TO BINARY
if (SW="0000") then
LED <= "00000000";
elsif (SW="0001") then
LED <= "00000001";
LED <= "00000011";
LED <= "00000010";
LED <= "00000111";
LED <= "00000110";
LED <= "00000100";
LED <= "00000101";
LED <= "00001111";
LED <= "00001110";
LED <= "00001100";
LED <= "00001101";
LED <= "00001000";
LED <= "00001001";
LED <= "00001011";
else
LED <= "00001010";
end if;
ELSE
END IF;
then-- BINARY TO HEXADECIMAL
IF SW<="1001" THEN
SF_D<="00100011";
S1<="0010" & SW;
SF_D<=S1;
ELSE
if SW>="1001" THEN
if (SW="1010") then
SF_D <= "00010100";
SF_D <= "01000001";
SF_D <= "00010100";
SF_D <= "01000010";
SF_D <= "00010100";
SF_D <= "01000011";
SF_D <= "00010100";
SF_D <= "01000100";
SF_D <= "00010100";
SF_D <= "01000101";
SF_D <= "00010100";
SF_D <= "01000110";
end if;
END IF;
end if;
end if;
end process;
end Behavioral;
constraints.ucf
#rotation button
NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
#switches
NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
#character lcd
NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW =
SLOW ;
NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
;
NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
;
# The LCD four-bit data interface is shared with the StrataFlash.
NET "SF_D<4>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW =
SLOW ;
NET "SF_D<5>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW =
SLOW ;
NET "SF_D<6>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW =
SLOW ;
NET "SF_D<7>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW =
SLOW ;
#clk
NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
#LED
NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
Test Bench:-
--------------------------------------------------------------------------
------
-- Company:
-- Engineer:
--
-- Create Date: 00:19:55 04/11/2017
-- Design Name:
-- Module Name: D:/vlsi/vlsiproject/binaryconvtest.vhd
-- Project Name: vlsiproject
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: binaryconv
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic
and
-- std_logic_vector for the ports of the unit under test. Xilinx
recommends
-- that these types always be used for the top-level I/O of a design in
order
-- to guarantee that the testbench will bind correctly to the post-
implementation
-- simulation model.
--------------------------------------------------------------------------
------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY binaryconvtest IS
END binaryconvtest;
ARCHITECTURE behavior OF binaryconvtest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT binaryconv
PORT(
BTN_EAST : IN std_logic;
CLK_50MHZ : IN std_logic;
BTN_NORTH : IN std_logic;
BTN_SOUTH : IN std_logic;
LCD_E : IN std_logic;
LCD_RS : IN std_logic;
LCD_RW : IN std_logic;
BTN_WEST : IN std_logic;
SW : IN std_logic_vector(3 downto 0);
SF_D : OUT std_logic_vector(7 downto 0);
LED : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal BTN_EAST : std_logic := '0';
signal CLK_50MHZ : std_logic := '0';
signal BTN_NORTH : std_logic := '0';
signal BTN_SOUTH : std_logic := '0';
signal LCD_E : std_logic := '0';
signal LCD_RS : std_logic := '0';
signal LCD_RW : std_logic := '0';
signal BTN_WEST : std_logic := '0';
signal SW : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal SF_D : std_logic_vector(7 downto 0);
signal LED : std_logic_vector(7 downto 0);
-- Clock period definitions

constant CLK_50MHZ_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)

uut: binaryconv PORT MAP (
BTN_EAST => BTN_EAST,
CLK_50MHZ => CLK_50MHZ,
BTN_NORTH => BTN_NORTH,
BTN_SOUTH => BTN_SOUTH,
LCD_E => LCD_E,
LCD_RS => LCD_RS,
LCD_RW => LCD_RW,
BTN_WEST => BTN_WEST,
SW => SW,
SF_D => SF_D,
LED => LED
);
-- Clock process definitions

CLK_50MHZ_process :process
begin
CLK_50MHZ <= '0';
wait for CLK_50MHZ_period/2;
CLK_50MHZ <= '1';
wait for CLK_50MHZ_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_50MHZ_period*10;
-- insert stimulus here

BTN_NORTH<='1';
BTN_SOUTH<='0';
BTN_EAST<='0';
BTN_WEST<='0';
sw<="1000";
wait for 100 ns;
BTN_NORTH<='0';
BTN_SOUTH<='1';
BTN_EAST<='0';
BTN_WEST<='0';
sw<="1000";
wait for 100 ns;
BTN_NORTH<='0';
BTN_SOUTH<='0';
BTN_EAST<='1';
BTN_WEST<='0';
SW<="1000";
wait for 100 ns;
BTN_NORTH<='0';
BTN_SOUTH<='0';
BTN_EAST<='0';
BTN_WEST<='1';
SW<="1000";
wait;
end process;
END;

AIM OF THE EXPERIMENT:-Binary To Decimal, Gray Code Apparatus Required

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AIM OF THE EXPERIMENT:-Binary To Decimal, Gray Code Apparatus Required

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AIM OF THE EXPERIMENT:- Binary to decimal, gray code

hexadecimal, and gray code to binary using Spartan 3E board.

-- Uncomment the following library declaration if using

-- Uncomment the following library declaration if instantiating

architecture Behavioral of binaryconv is

-- Uncomment the following library declaration if using

ARCHITECTURE behavior OF binaryconvtest IS

-- Component Declaration for the Unit Under Test (UUT)

-- Clock period definitions

-- Instantiate the Unit Under Test (UUT)

-- Clock process definitions

-- insert stimulus here

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