ARTICLE

PCB Design Techniques

for DDR, DDR2 & DDR3
(Part 1)
by Barry Olney a) Technology Rules
In-Circuit Design Pty Ltd, Australia The technology rules are based on the
minimum pitch of the BGA components em-
ployed and are basically the largest trace, clear-
SUMMARY ance and via allowable while minimizing PCB
fabrication costs. Technology of 4/4 MIL (trace/
In the first part of this two-part article on PCB clearance) and vias of 20/8 MIL (pad/hole) are
design techniques for DDR, DDR2 and DDR3, generally required.
we will look at the pre-layout setup of typical Once these rules have been established,
DDRx designs considering the multilayer PCB calculate the stackup required for the desired
stackup, technology rules and how they should characteristic impedance (Zo) and the differ-
be selected, and the power distribution net- ential impedance (Zdiff). These are Zo = 50
work and associated decoupling, and introduce and Zdiff = 100 for DDRx (DDR has Zo =
the design rules for DDR and DDR2 layout. 60). Keep in mind that lower impedance will
increase the dI/dt and dramatically increase
the current drawn (not good for the PDN) and
higher impedance will emit more EMI and also
Multilayer PCB Stackup make the design more susceptible to outside
Before starting the PCB design it is impor- interference. So, a good range of Zo is 50 to
tant to plan the PCB stackup. To achieve the 60.
best results, the following points need to be Also, keep in mind that USB differential sig-
taken into account: nals may be used on the board. These require a
Zdiff of 90. So, the trace width and clearance
a) Technology Rulestrace width, need to be adjusted for these signals.
clearancecharacteristic and differential How do you calculate the Zo and Zdiff of
impedance. the entire stackup using the established design
b) The Power Distribution Network rules?
(PDN) which power planes are Well, this one I have made easy for you.
required? In-Circuit Design Pty Ltd has developed the
c) Bypass and Decoupling. ICD Stackup Planner which is ideal for this.
d) Return Paths of Matched Length Signals You can download an evaluation copy from
one point that is generally missed. www.icd.com.au.

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 THE CORE DC SUPPLIES MUST FIRST BE IDENTIFIED AND FOR EACH OF THESE
SUPPLIES CALCULATE THE MAXIMUM DC CURRENT (SINK) REQUIRED.

b) The Power Distribution Network (PDN) signal. Current flow is a round trip. If it takes
As you may be aware, there are many one signal longer for the return current to get
different power supply requirements for the back to the driver (around a gap in the plane
DDRx controllers, FPGA or CPUs. The core DC for instance) then there will be skew between
supplies must first be identified and for each the critical timing signals.
of these supplies calculate the maximum DC So, when you plan your stackup, be aware
current (sink) required. For instance, 5 amps of which plane(s) (either power or ground)
may be required, for a 20 degree rise in tem- will be the return path for your critical signals
perature of the substrate, so the design rules and make sure there is an unobstructed return
need to be set to reflect this requirement. The path.
ICD Stackup Planner can also be used to obtain
these calculations. DDRx Specifications and Design Rules
Then, finding a way to deliver the supplies The DDRx Specs can be downloaded from
to the BGAs is the next drama. It will usually www.jedec.org. These are at first quite daunt-
be necessary to split the power planes to ac- ing with many pages of requirements for tim-
commodate all of these supplies. This can be ing budgets, matched length, differential pair
done providing the power plane isnt used for and de-rating of setup and hold times.
the return path of the DDRx signals. It is pref-
erable to locate these core fills directly under DDRx JEDEC Specifications
the controller. DDR JESD 79F
DDR2 JESD79-2E
c) Bypass and Decoupling DDR3 JESD79-3D
A bypass capacitor acts by dampening the
AC or noise on the supply. As simultaneous These devices are SDRAM that use Double
switching signals draw high current, the DC Data Rate (DDR) architecture to achieve high-
supply tends to have noise imposed onto it. speed operation by transferring two data words
And to make it worse, the latest ICs are very per clock cycle at the I/O pins.
sensitive to noise due to the lowering of supply
voltages and the presence of a large number of DDR Design GuidelinesCritical
potential noise generators. Constraints:
Decoupling capacitors supply instanta-
neous current (at different frequencies) to the chipbetween 2 to 6 depending on
drivers until the power supply can respond. In load. There may need to be a series
other words, it takes a finite time for current terminator depending on the load and
to flow from the power supply circuit (whether net length.
on board or remote) due to the inductance of
the trace and/or wires to the drivers. 0.4 to 1.2
It is best to follow the chip manufacturers
recommendations on the numbers, values and the VTT Termination0.5 to 2
position of these capacitors, although it is quite
daunting to be asked to place three or four de- be minimized to reduce the skew within
caps on each supply pin. This will be discussed groups (or lanes) and across groups. 15
in more detail in the placement section. MIL within groups and 15 MIL across
groups.
d) Return Paths and Matched Length Signals
One point that always amazes me: Design- Other constraints to consider:
ers generally take great care to ensure that
matched length signals are routed exactly to
length from the driver to the DRRx device between the driver and first DIMM or
pin, but take no care of the return path of the chip.

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PCB Design Techniques for DDR, DDR2 & DDR3 (Part 1) continues

Note: DIMMs also have a series resistor daisy chained with a VTT pull-up for
after the connector. termination.

series termination and are daisy chained Also other constraints to consider:
with a VTT pull-up for termination.
. routed differentially.

between the driver and first DIMM or
chip.
Note: DIMMs also have a series resistor
after the connector.

(ODT) built into the controller and
SDRAM. The configurations are 50, 75
Figure 1: Address
Address, Data and Command nets and 150, so VTT pull-up is not
may need series and VTT termination. necessary.
. Zdiff is 100.
The value and placement of the series
resistors and VTT pull-ups for data, address
and command nets depends on the distances
between the loads, number of loads and the
stackup of the board, and are best determined
by simulation. The series terminator may not
be required if a single SDRAM is used and the
trace length is short.
Also, the routing layers should be selected Figure 2: DQ (data) has no VTT termination
termination.
such that each net has a common reference
plane(s), for the return path of the signal, and The second and last part of the article will
routed internally (where possible) to reduce look at the comparison of DDR2 to DDR3;
EMI. Stitching vias or capacitors can be used to DDR3 design guidelines; pre-layout analysis;
connect reference planes. With any high-speed critical placement; an example of design rules;
board, crosstalk should be analyzed to reduce and finally, the post-layout analysis. PCB
interference.
References:
DDR2 Design GuidelinesCritical Advanced Design for SMTBarry Olney,
Constraints: In-Circuit Design Pty Ltd.
JEDEC Specifications JESD 79F, JESD79-2E
chipbetween 1.9 to 4.5 depending & JESD79-3D.
on load Altera Board Layout Guidelines, EMI_Plan_
Board.
0.425
Ba
Barry Olney is Managing Director
the VTT Termination0.2 to 0.55 of In-Circuit Design Pty Ltd (ICD),
A
Australia, a PCB Design Service Bureau
be minimized to reduce the skew within an
and Board Level Simulation Specialist.
groups (or lanes) and across groups. 50 A
Among many other awards through
MIL within groups and 500 MIL across th
the years, ICD was awarded Top
groups. 20
2005 Asian Distributor Marketing
d Top
and T
T 2005 Worldwide Distributor Marketing

by Mentor Graphics, Board System Division.
200 MIL. Address and command nets are

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