1.

Analog-to-Digital Conversion
Sampling and Filtering
An anti-aliasing filter and a sample-and-hold circuit
are two functions typically found in a digital signal
processing system.
Sampling is the process of taking a sufficient number
of discrete values at points on a waveform that will
define the shape of the waveform. The more samples
you take, the more accurately you can define a
waveform. Sampling converts an analog signal into a
series of impulses, each representing the amplitude
of the signal at a given instant in time.
 The sampling theorem states that, in order to represent an analog signal, the sampling frequency,
, must be at least twice the highest frequency component () of the analog signal.

The frequency () is known as the Nyquist frequency.

> ()

All analog signals (except a pure sine wave) contain a

spectrum of component frequencies. For a pure sine wave,
these frequencies appear in multiples called harmonics.

The harmonics of an analog signal are sine waves of different

frequencies and amplitudes. When the harmonics of a given
periodic waveform are added, the result is the original signal.
 Low-pass filtering is necessary to remove all frequency components (harmonics) of the analog signal that exceed
the Nyquist frequency.
Aliasing is an unwanted condition occurs If there are any frequency components in the analog signal that exceed
the Nyquist frequency.
An alias is a signal produced when the sampling frequency is not at least twice the signal frequency.
An alias signal has a frequency that is less than the highest frequency in the analog signal being sampled and
therefore falls within the spectrum or frequency band of the input analog signal causing distortion.
Another way to view aliasing is by considering that the sampling
pulses produce a spectrum of harmonic frequencies above and
below the sample frequency
If the analog signal contains frequencies above the Nyquist
frequency, these frequencies overlap into the spectrum of the
sample waveform as shown and interference occurs.
The lower frequency components of the sampling waveform
become mixed in with the frequency spectra of the analog
waveform, resulting in an aliasing error.
A low-pass anti-aliasing filter must be used to limit the frequency
spectrum of the analog signal for a given sample frequency.
To avoid an aliasing error, the filter must at least eliminate all analog
frequencies above the minimum frequency in the sampling
spectrum.
This is a sinusoidal analog signal with
() = 90 cycle/second sampled at
= 1000 samples/second.

=
()

Equivalently, there are 11.1 samples

taken over a complete cycle of the
sinusoid.
These samples represent accurately the
sinusoid because there is no other
sinusoid that can produce the same
samples because 1000 > 2 90
Here () = 310 cycle/second
sampled at
= 1000 samples/second.

= = .

This results into 3.2 samples per sine wave cycle.
The samples are so sparse they dont appear to
follow the analog wave.
Strange as it seems, it can be proven that no other
sine wave can produce the same type of samples.
Since the samples represent accurately the
sinusoid they constitute a proper sampling
because 1000 > 2 310
Here () = 950 cycle/second
sampled at
= 1000 samples/second.

= = .

This results into 1.05 samples per sine wave cycle.
Clearly, this is an improper sampling of the signal
because another sine wave that can produce the
same samples and here < ()
The original sine misrepresents itself as another
sine. This
phenomenon is called aliasing. (The original sine
has hidden its
true identity!)
 An example of the application of sampling is in digital audio equipment.
The sampling rates used are 32 kHz, 44.1 kHz, or 48 kHz (the number of samples per
second).
The 48 kHz rate is the most common, but the 44.1 kHz rate is used for audio CDs and
prerecorded tapes.
According to the Nyquist rate, the sampling frequency must be at least twice the audio
signal. Therefore, the CD sampling rate of 44.1 kHz captures frequencies up to about 22
kHz, which exceeds the 20 kHz specification that is common for most audio equipment.
Many applications do not require a wide frequency range to obtain reproduced sound
that is acceptable. For example, human speech contains some frequencies near 10 kHz
and, therefore, requires a sampling rate of at least 20 kHz.
The effect of aliasing will become noticeable with background noise and distortion.
 Holding the Sampled Value

The holding operation is the second part of the sample-and-hold function.

After filtering and sampling, the sampled level must be held constant until the next sample occurs.
This operation is necessary for TWO reasons:
A. It is necessary for the ADC to have time to process the sampled value.
B. It keeps the amplitude of the analog input signal constant between sample pulses; therefore, the
analog-to-digital conversion can be done using a constant value rather than having the analog
signal change during a conversion interval, which is the time between sample pulses.
This sample-and-hold operation results in a stair-step waveform that approximates the analog input
waveform
 Analog-to-Digital Conversion

Analog-to-digital conversion is the process of converting the output of the sample-and-hold circuit to a
series of binary codes that represent the amplitude of the analog input at each of the sample times.

The process of converting an analog value to a code is called quantization.

During the quantization process, the ADC converts each sampled value of the analog signal to a binary
code.
The more bits that are used to represent a sampled value, the more accurate is the representation.
 lets quantize a reproduction of the analog
waveform into four levels (03).
Two bits are required for four levels.
Each quantization level is represented by a 2-bit
code on the vertical axis, and each sample
interval is numbered along the horizontal axis.
The sampled data is held for the entire sample
period. This data is quantized to the next lower
level.

If the resulting 2-bit digital codes are used to reconstruct

the original waveform, you would get the waveform shown
beside.
This operation is done by Digital-to-Analog Converters
(DACs), which are circuits that perform digital-to-analog
conversions.
As you can see, quite a bit of accuracy is lost using only two
bits to represent the sampled values.
 Now, lets see how more bits will improve the accuracy.
Figure on the right shows the same waveform with sixteen
quantization levels (4 bits). The 4-bit quantization process is
summarized in Table below.

If the resulting 4-bit digital codes are used to reconstruct the original
waveform, you would get the waveform shown in Figure below.
As you can see, the result is much more like the original waveform than
for the case of four quantization levels. This shows that greater accuracy is
achieved with more quantization bits.
 Checkup
What does sampling mean?
Sampling is the process of converting an analog signal into a series of impulses, each representing the
amplitude of the analog signal.

Why must you hold a sampled value?

A sampled value is held to allow time to convert the value to a binary code.

If the highest frequency component in an analog signal is 20 kHz, what is the minimum sample
frequency?
The minimum sampling frequency is 40 kHz.

What does quantization mean?

Quantization is the process of converting a sampled level to a binary code.

What determines the accuracy of the quantization process?

The number of bits determine quantization accuracy.
 2. Methods of Analog-to-Digital Conversion
Two important ADC parameters are:
Resolution: which is the number of bits.
Throughput: which is the sampling rate an ADC can handle in units of samples per second (sps).

Flash ADC
The flash method utilizes special high-speed comparators that compare reference voltages with the analog input
voltage.
When the input voltage exceeds the reference voltage for a given comparator, a HIGH is generated.
The number of bits used in an ADC is its resolution.
Advantages:
It provides a fast conversion time because of a high throughput, measured in samples per second (sps).
Disadvantages:
The large number of comparators necessary for a reasonable-sized binary number
 Flash ADC
This figure shows a 3-bit converter
that uses seven comparator circuits;
a comparator is not needed for the
all-0s condition.
In general, comparators are
required for conversion to an n-bit
binary code.
The reference voltage for each
comparator is set by the resistive
voltage-divider circuit.
The output of each comparator is
connected to an input of the priority
encoder.
The encoder is enabled by a pulse on
the EN input, and a 3-bit code
representing the value of the input
appears on the encoders outputs.
The binary code is determined by
the highest-order input having a
HIGH level.
Flash ADC

Example 1 Determine the binary code output of the 3-bit flash ADC in Figure above for the
input signal in Figure below and the encoder enable pulses shown. For this
example, = + .
Flash ADC

Solution
The resulting digital output sequence is
listed as follows and shown in the
waveform diagram of the figure on the
right in relation to the enable pulses:
100, 110, 111, 110, 100, 010, 000, 001,
011, 101, 110, 111

If the enable pulse frequency in Figure of Example 1 were halved, determine the binary
Home
numbers represented by the resulting digital output sequence for 6 pulses. Is any
Work information lost?
 Dual-Slope ADC
A dual-slope ADC is common in digital voltmeters and other types of measurement instruments.
A ramp generator (integrator) is used to produce the dual-slope characteristic.
 Dual-Slope ADC
Start by assuming that the counter is reset and the output of the integrator is zero.
Now assume that a positive input voltage is applied to the input through the switch (SW) as selected by the control logic.
Since the inverting input of 1 is at virtual ground, and assuming that Vin is constant for a period of time, there will be constant
current through the input resistor R and therefore through the capacitor C.
Capacitor C will charge linearly because the current is constant, and as a result, there will be a negative-going linear voltage ramp on
the output of 1 .
When the counter reaches a specified count (n), it will be reset (R), and the control logic will switch the negative reference
voltage( ) to the input of 1 .
At this point the capacitor is charged to a negative voltage (-V) proportional to the input analog voltage.
 Dual-Slope ADC
Now the capacitor discharges linearly because of the constant current from the .
This linear discharge produces a positive-going ramp on the 1 output, starting at -V and having a constant slope that is independent
of the charge voltage.
As the capacitor discharges, the counter advances from its RESET state.
The time it takes the capacitor to discharge to zero depends on the initial voltage -V (proportional to ) because the discharge rate
(slope) is constant.
When the integrator (1 ) output voltage reaches zero, the comparator (2 ) switches to the LOW state and disables the clock to the
counter. The binary count is latched, thus completing one conversion cycle.
 Successive-Approximation ADC
One of the most widely used methods of analog-to-digital
conversion is successive-approximation:
It has a much faster conversion time than the dual-slope
conversion, but it is slower than the flash method.
It also has a fixed conversion time that is the same for any
value of the analog input.
It consists of a DAC, a successive-approximation register
(SAR), and a comparator.
The basic operation is as follows:
o The input bits of the DAC are enabled (made equal to a 1)
one at a time, starting with the most significant bit (MSB).
o As each bit is enabled, the comparator produces an output
that indicates whether the input signal voltage is greater or
less than the output of the DAC.
o If the DAC output is greater than the input signal, the
comparators output is LOW, causing the bit in the register
to reset. If the output is less than the input signal, the 1 bit
is retained in the register.
 Successive-Approximation ADC

Example 2
Lets assume that the DAC has the
following output characteristics:
= 8 V for the bit (MSB),
= 4 V for the bit,
= 2 V for the bit,
= 1 V for the bit (LSB).
 Successive-Approximation ADC
The first step in the
conversion cycle with
the MSB = 1.
The output of the DAC is
8 V.
Since this is greater than
the input of 5.1 V, the
output of the
comparator is LOW,
causing the MSB in the
SAR to be reset to a 0.
 Successive-Approximation ADC
The second step in the
conversion cycle with
the bit equal to a 1.
The output of the DAC is
4 V.
Since this is less than
the input of 5.1 V, the
output of the
comparator switches to
a HIGH, causing this bit
to be retained in the
SAR.
 Successive-Approximation ADC
The third step in the
conversion cycle with
the bit equal to a 1.
The output of the DAC is
6 V because there is a 1
on the bit input and
on the bit input;
4 V + 2 V = 6 V.
Since this is greater than
the input of 5.1 V, the
output of the
comparator switches to
a LOW, causing this bit
to be reset to a 0.
 Successive-Approximation ADC
The fourth and final step in
the conversion cycle with
the bit equal to a 1.
The output of the DAC is 5
V because there is a 1 on
the bit input and on the
bit input;
4 V + 1 V = 5 V.
The four bits have all been
tried, thus completing the
conversion cycle.
At this point the binary
code in the register is 0101,
which is approximately the
binary value of the input of
5.1 V.
Additional bits will produce
an even more accurate
result.
 Segma-Delta ADC

Sigma-delta is a widely used method of analog-to-digital conversion, particularly in

telecommunications using audio signals.
The method is based on delta modulation where the difference between two successive
samples (increase or decrease) is quantized; other ADC methods were based on the
absolute value of a sample.
A delta modulation (DM or -modulation) is an analog-to-digital and digital-to-analog
signal conversion technique used for transmission of voice information where quality is
not of primary importance.
Delta modulation is a 1-bit quantization method.
The output of a delta modulator is a single-bit data stream where the relative number
of 1s and 0s indicates the level or amplitude of the input signal.
The number of 1s over a given number of clock cycles establishes the signal amplitude
during that interval.
 Segma-Delta ADC

A maximum number of 1s corresponds to the

maximum positive input voltage.
A number of 1s equal to one-half the
maximum corresponds to an input voltage of
zero.
No 1s (all 0s) corresponds to the maximum
negative input voltage.

For example, assume that 4096 1s occur during the interval when the input signal is a positive
maximum.
Since zero is the midpoint of the dynamic range of the input signal, 2048 1s occur during the
interval when the input signal is zero.
There are no 1s during the interval when the input signal is a negative maximum.
For signal levels in between, the number of 1s is proportional to the level.
 Segma-Delta ADC
The analog input signal and the
analog signal from the converted
quantized bit stream from the DAC
in the feedback loop are applied to
the summation () point.
The difference () signal out of the
is integrated, and the 1-bit ADC
increases or decreases the number
of 1s depending on the difference
signal.
This action attempts to keep the quantized signal that is fed back equal to the incoming analog signal.
The 1-bit quantizer is essentially a comparator followed by a latch.
To complete the sigma-delta conversion process using one particular approach, the single bit data stream is
converted to a series of binary codes.
The counter counts the 1s in the quantized data stream for successive intervals.
The code in the counter then represents the amplitude of the analog input signal for each interval.
These codes are shifted out into the latch for temporary storage. What comes out of the latch is a series of n-bit
codes, which completely represent the analog signal.
 Testing Analog-to-Digital Converters
A DAC is used as part of the test setup to convert the ADC output back to analog form for
comparison with the test input.
A test input in the form of a linear ramp is applied to the input of the ADC.
The resulting binary output sequence is then applied to the DAC test unit and converted to a
stair-step ramp.
The input and output ramps are compared for any deviation.
 Analog-to-Digital Conversion Errors
Missing Code

The stairstep output in Figure indicates that the

binary code 1001 does not appear on the output
of the ADC.
Notice that the 1000 value stays for two intervals
and then the output jumps to the 1010 value.
In a flash ADC, for example, a failure of one of the
op-amp comparators can cause a missing-code
error.
 Analog-to-Digital Conversion Errors
Incorrect Code

The stair-step output in Figure indicates that

several of the binary code words coming out of
the ADC are incorrect.
Analysis indicates that the 21 -bit line is stuck in
the LOW (0) state in this particular case.
 Analog-to-Digital Conversion Errors
Offset

In this situation the ADC interprets the analog

input voltage as greater than its actual value.
 Analog-to-Digital Conversion Errors

Example 3
A 4-bit flash ADC is shown in left-figure. The
resulting reconstructed analog output is
shown in right-figure.
Identify the problem and the most probable
fault.

Solution
The binary code 0011 is missing from the
ADC output, as indicated by the missing
step.
Most likely, the output of comparator 3 is
stuck in its inactive state (LOW).
 Analog-to-Digital Conversion Errors

Example 4
Reconstruct the analog output in a test
setup if the ADC in Figure of Example 3 has
comparator 8 stuck in the HIGH output
state.

Solution
Due to the priority counter function, and
because of comp. 8 stuck in the HIGH state,
then the counter will produce a HIGH output
all the way from 0000 to 1000 as it sees the
comp. 8 is HIGH. This will change as soon as
comp. 9 is HIGH because the new high-order
level is coming from comp. 9 which is work
properly.
See the right-figure.
 Checkup

What is the fastest method of analog-to-digital conversion?

The simultaneous (flash) method is fastest.
Which analog-to-digital conversion method produces a single-bit data stream?
The sigma-delta method produces a single-bit data stream.
Does the successive-approximation converter have a fixed conversion time?
Yes, successive approximation has a fixed conversion time.
Name two types of output errors in an ADC.
Missing code, incorrect code, and offset are types of ADC output errors.
 2. Methods of Digital-to-Analog Conversion

Binary-Weighted-Input DAC
One method of digital-to-analog conversion uses a resistor
network with resistance values that represent the binary
weights of the input bits of the digital code.
Each of the input resistors will either have current or have
no current, depending on the input voltage level.
If the input voltage is zero (binary 0), the current is also
zero.
If the input voltage is HIGH (binary 1), the amount of
current depends on the input resistor value and is
different for each input resistor, as indicated in the figure.
Disadvantages of this type of DAC are the number of
different resistor values and the fact that the voltage levels
must be exactly the same for all inputs.
Binary-Weighted-Input DAC
Since there is practically no current into the op-amp inverting (-)
input, all of the input currents sum together and go through .
Since the inverting input is at 0 V (virtual ground), the drop across
is equal to the output voltage, so = .
The values of the input resistors are chosen to be inversely
proportional to the binary weights of the corresponding input bits.
The lowest-value resistor (R) corresponds to the highest binary-
weighted input (23 ).
The other resistors are multiples of R (that is, 2R, 4R, and 8R) and
correspond to the binary weights 22 , 21 , and 20 , respectively.

= = + + +

In General = = + + + +

 Binary-Weighted-Input DAC

Example 5
Determine the output of the DAC in Figure(a) if the waveforms representing a sequence of 4-bit numbers in Figure(b)
are applied to the inputs. Input is the least significant bit (LSB).
Binary-Weighted-Input DAC

Solution 3 2 1 0 Binary Input

= = + + +
2 4 8 0000 0
0001 -0.25
0010 -0.50
0011 -0.75
0100 -1.00
0101 -1.25
0110 -1.50
0111 -1.75
1000 -2.00
1001 -2.25
1010 -2.50
1011 -2.75
1100 -3.00
1101 -3.25
1110 -3.50
1111 -3.75
 R/2R Ladder DAC
Advantages
Only two resistor values (R and 2R).
Does not require high precision resistors.
Disadvantage
Lower conversion speed than binary weighted
DAC.
R/2R Ladder DAC
Start by assuming that the D3 input is HIGH (+5 V) and the others are LOW (ground, 0 V).
This condition represents the binary number .
A circuit analysis will show that this reduces to the equivalent form shown in figure(a).
Essentially no current goes through the 2R equivalent resistance because the inverting input is at virtual ground.
Thus, all of the current (I = 5 V/2R) through R7 also goes through , and the output voltage is -5 V.
The operational amplifier keeps the inverting (-) input near zero volts (0 V) because of negative feedback.
Therefore, all current goes through rather than into the inverting input.
R/2R Ladder DAC
Figure(b) shows the equivalent circuit when the 2 input is at +5 V and the others are at ground.
This condition represents .
If we thevenize looking from 8 , we get 2.5 V in series with R, as shown.
This results in a current through of I = 2.5 V/2R, which gives an output voltage of -2.5 V.
Keep in mind that there is no current into the op amp inverting input and that there is no current
through the equivalent resistance to ground because it has 0 V across it, due to the virtual ground.
R/2R Ladder DAC
Figure(c) shows the equivalent circuit when the 1 input is at +5 V and the others are at ground.
This condition represents .
Again thevenizing looking from 8 , you get 1.25 V in series with R as shown.
This results in a current through of I = 1.25 V/2R, which gives an output voltage of -1.25 V.
 R/2R Ladder DAC
In part (d), the equivalent circuit representing the case where 1 is at +5 V and the other inputs are at
ground is shown.
This condition represents 0001.
Thevenizing from 8 gives an equivalent of 0.625 V in series with R as shown.
The resulting current through is I = 0.625 V/2R, which gives an output voltage of -0.625 V.
Notice that each successively lower-weighted input produces an output voltage that is halved, so that the
output voltage is proportional to the binary weight of the input bits.
 R/2R Ladder DAC

For a 4-Bit R-2R Ladder

= + + +

For general n-Bit R-2R Ladder or Binary Weighted Resister DAC

=

=
 Performance Characteristics of DACs

Resolution: is the amount of variance in output voltage for every change of the LSB in the digital input.
An n-bit resolution can resolve 2 1 distinct analog levels, i.e. The total number of discrete steps
equals 2 1, where n is the number of bits.

= %

 Performance Characteristics of DACs
Accuracy is derived from a comparison of the actual output of a DAC with the
expected output.
It is expressed as a percentage of a full-scale, or maximum, output voltage. For
example, if a converter has a full-scale output of 10 V and the accuracy is 0.1%,
then the maximum error for any output voltage is (10 V)(0.001) = 10 mV.
Ideally, the accuracy should be no worse than 1/2 of a least significant bit.

.
= %

 Performance Characteristics of DACs
Linearity: is the difference between the desired analog output and the actual output over the full
range of expected values.
Ideally, a DAC should produce a linear relationship between a digital input and the analog output, this
is not always the case.
A special case is an offset error, which is the amount of output voltage when the input bits are all
zeros.

Linearity (Ideal) Non-Linearity

Analog Output Signal

Analog Output Signal

0000 0001 0010 0011 0100 0101 0000 0001 0010 0011 0100 0101
Digital Input Signal Digital Input Signal
 Performance Characteristics of DACs

A DAC is monotonic if it does not

take any reverse steps when it is
sequenced over its entire range of
input bits.
 Performance Characteristics of DACs

Settling Time time required for

the output to fall with in +/-
when a change occurs in the input
code.
 Digital-to-Analog Conversion Errors

The step reversals indicate nonmonotonic

performance, which is a form of nonlinearity.
In this particular case, the error occurs
because the 21 bit in the binary code is
interpreted as a constant 0.
That is, a short is causing the bit input line to
be stuck LOW.
 Performance Characteristics of DACs
The figure here illustrates differential
nonlinearity in which the step amplitude is
less than it should be for certain input
codes.
This particular output could be caused by
the 22 bit having an insufficient weight,
perhaps because of a faulty input resistor.
We could also see steps with amplitudes
greater than normal if a particular binary
weight were greater than it should be.
 Performance Characteristics of DACs
In the case of low gain, all of the step
amplitudes are less than ideal.
In the case of high gain, all of the step
amplitudes are greater than ideal.
This situation may be caused by a faulty
feedback resistor in the op-amp circuit.
 Performance Characteristics of DACs

Notice that when the binary input is 0000,

the output voltage is nonzero and that this
amount of offset is the same for all steps
in the conversion.
A faulty op-amp may be the culprit in this
situation.
 Binary-Weighted-Input DAC

Example 6
The DAC output in figure is observed when a straight 4-bit
binary sequence is applied to the inputs. Identify the type of
error, and suggest an approach to isolate the fault.

Solution
The DAC in this case is nonmonotonic. Analysis of the output reveals
that the device is converting the following sequence, rather than the
actual binary sequence applied to the inputs.
0010, 0011, 0010, 0011, 0110, 0111, 0110, 0111, 1010, 1011, 1010,
1011, 1110, 1111,1110, 1111
1
Apparently, the 2 bit is stuck in the HIGH (1) state. To find the problem,
first monitor the bit input pin to the device. If it is changing states, the
fault is internal to the DAC and it should be replaced. If the external pin
is not changing states and is always HIGH, check for an external short to
+V that may be caused by a solder bridge somewhere on the circuit
board.
 Binary-Weighted-Input DAC

Example 7
Determine the output of a DAC when a straight 4-bit
binary sequence is applied to the inputs and the 20 bit
is stuck HIGH.

Solution
 The Reconstruction Filter
The output of the DAC is a stair-step approximation of the original analog signal after
it has been processed by the digital signal processor (DSP), which is a special type of
microprocessor that processes data in real time.
The purpose of the low-pass reconstruction filter (sometimes called a postfilter) is to
smooth out the DAC output by eliminating the higher frequency content that results
from the fast transitions of the stair-steps, as roughly illustrated in figure below.
 Q1

A wheel, rotating at 6 Hz, is seen in a dark room by means of a strobe light flashing at a rate of 8 Hz.
Determine the apparent rotational speed and sense of rotation of the wheel. Repeat the question if the
flashes occur at 12 Hz, 16 Hz, or 24 Hz.
 Q2

Hard disk recording systems for digital audio are becoming widely available. It is often quoted that to record
1 minute of CD quality digital audio in 2-Channels stereo, one needs about 10 Megabytes of hard disk
space. Please, derive this result, explaining your reasoning.
Assume each sample is quantized with 16 bits.
 Q3

Please specify the following sentences are TRUE or FALSE:

1. An analog signal can be converted to a digital signal using sampling.
2. An ADC is an analog data component.
3. Aliasing is a desired factor in sampling.
4. A higher sampling rate is more accurate than a lower sampling rate for a given analog
signal.
5. MIPS stands for memory instructions per second.
6. Successful approximation is an analog-to-digital conversion method.
7. Delta modulation is based on the difference of two successive samples.
8. Two types of DAC are the binary-weighted input and the R/2R ladder.
9. The process of converting an analog value to a code is called quantization.
10. A flash ADC differs from a simultaneous ADC.
 Q4
Choose the correct answer: 3. The most common ADC seen in
1. Aliasing results in telecommunications based on audio signals is
(a) oversampling (a) flash ADC
(b) undersampling (b) successive approximation ADC
(c) guard-band formation (c) sigma-delta ADC
(d) perfect sampling (d) dual-slope ADC
2. The quantization process 4. A digital signal processing system usually
(a) converts the sample-and-hold output to operates in
binary code (a) real time
(b) converts a sample impulse to a level (b) imaginary time
(c) converts a sequence of binary codes to a (c) compressed time
reconstructed analog signal (d) computer time
(d) filters out unwanted frequencies before
sampling takes place
Q5 The waveform shown in Figure is applied to a sampling
circuit and is sampled every 3 ms.
(A) Show the output of the sampling circuit. Assume a
one-to-one voltage correspondence between the
input and output.
(B) The output of the sampling circuit in Problem A is
applied to a hold circuit. Show the output of the hold
circuit.
(C) If the output of the hold circuit in Problem B is
quantized using two bits, what is the resulting
sequence of binary codes?
(D) Repeat Problem C using 4-bit quantization.
(E) Reconstruct the analog signal from the 2-bit
quantization in Problem C.
(F) Reconstruct the analog signal from the 4-bit
quantization in Problem D.
(G) Graph the analog function represented by the
following sequence of binary numbers: 1111, 1110,
1101, 1100, 1010, 1001, 1000, 0111, 0110, 0101,
0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011,
1100, 1100, 1100, 1011, 1010, 1001.
 Q6

Give the results and the explanations if the following

errors taken place in the ADC in figure below:
Resistor fails open.
Resistor fails open.
Comparator output fails low.
Solder bridge (short) across resistor .