EXPERIMENT-6

To study and verification of State table of different Flip-Flops

Objects:- Verification of State table and state diagram

(i) S R flip flop.

(ii) D- flip-flop.
(iii) J K flip-flop.
(iv) T flip-flop.

COMPONENTS REQUIRED

1. IC 7400, IC 7404, IC 74101 No/each IC

2. Patch Cords & single Stand wire.
3. Components development system

THEORY:- A Flip Flop is a sequential device that samples its input signals and changes its
output states only at times determined by clocking signal. Flip Flops may vary in the number of
inputs they possess and the manner in which the inputs affect the binary states. Flip flops are the
basic building blocks in any memory systems since its output will remain in its state until it is
forced to change it by some means.

State Table

The state table representation of a sequential circuit consists of three sections labelled present state,
next state and output. The present state designates the state of flip-flops before the occurrence of a
clock pulse. The next state shows the states of flip-flops after the clock pulse, and the output section
lists the value of the output variables during the present state.

State Diagram

In addition to graphical symbols, tables or equations, flip-flops can also be represented graphically
by a state diagram. In this diagram, a state is represented by a circle, and the transition between
states is indicated by directed lines (or arcs) connecting the circles.

You can see from the table that all four flip-flops have the same number of states and transitions.
Each flip-flop is in the set state when Q=1 and in the reset state when Q=0. Also, each flip-flop can
move from one state to another, or it can re-enter the same state. The only difference between the
four types lies in the values of input signals that cause these transitions
State Diagrams of Various Flip-flops

NAME STATE DIAGRAM

SR

JK

RS FLIP FLOP:

The clocked RS flip flop consists of NAND gates and the output changes its state with respect to the
input on application of clock pulse. When the clock pulse is high the S and R inputs reach the
second level NAND gates in their complementary form. The Flip Flop is reset when the R
input high and S input is low. The Flip Flop is set when the S input is high and R input is
low. When both the inputs are high the output is in an indeterminate state.

D FLIP FLOP:

To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when both inputs
are high at the same time, in the D Flip Flop the inputs are never made equal at the same time. This
is obtained by making the two inputs complement of each other.

JK FLIP FLOP:

The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs behave like S
and R inputs to set and reset the Flip Flop. The output Q is ANDed with K input and the clock
pulse, similarly the output Q is ANDed with J input and the Clock pulse. When the clock pulse is
zero both the AND gates are disabled and the Q and Q output retain their previous values. When
the clock pulse is high, the J and K inputs reach the NOR gates. When both the inputs are high the
output toggles continuously. This is called Race around condition and this must be avoided.

T FLIP FLOP:
This is a modification of JK Flip Flop, obtained by connecting both inputs J and K inputs
together. T Flip Flop is also called Toggle Flip Flop.

CIRCUIT DIAGRAM & RESULT :-

RS FLIP FLOP
LOGIC SYMBOL:

CIRCUIT DIAGRAM:

CHARACTERISTIC TABLE (State Table)

CLOCK INPUT PRESENT NEXT STATUS
PULSE S R STATE (Q) STATE(Q+1) NAME
1 0 0 0
2 0 0 1
3 0 1 0
4 0 1 1
5 1 0 0
6 1 0 1
7 1 1 0
8 1 1 1
D FLIP FLOP
LOGIC SYMBOL:

CIRCUIT DIAGRAM:

CHARACTERISTIC TABLE: (State table) RESULT TABLE

CLOCK INPUT PRESENT NEXT STATUS

PULSE D STATE (Q) STATE(Q+1) NAME
1 0 0
2 0 1
3 1 0
4 1 1

JK FLIP FLOP
LOGIC SYMBOL:

CIRCUIT DIAGRAM:
 CHARACTERISTIC TABLE: (RESULT TABLE)

CLOCK INPUT PRESENT NEXT STATUS

PULSE J K STATE (Q) STATE(Q+1) NAME
1 0 0 0
2 0 0 1
3 0 1 0
4 0 1 1
5 1 0 0
6 1 0 1
7 1 1 0
8 1 1 1
T FLIP FLOP
LOGIC SYMBOL:

CIRCUIT DIAGRAM:

CHARACTERISTIC TABLE: (RESULT TABLE)

CLOCK INPUT PRESENT NEXT STATUS

PULSE T STATE (Q) STATE(Q+1) NAME
1 0 0
2 0 1
3 1 0
4 1 1

PROCEDURE: 1. Connections are given as per the circuit diagrams.

2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and observe the status of all the flip flops.
 Summary of the Types of Flip-flop Behavior

FLIP-
FLIP-FLOP CHARACTERISTIC CHARACTERISTIC
FLOP EXCITATION TABLE
SYMBOL TABLE EQUATION
NAME
S R Q(next) Q Q(next) S R
0 0 Q 0 0 0 X
Q(next) = S + R'Q
SR 0 1 0 0 1 1 0
SR = 0 1 0 0 1
1 0 1
1 1 ? 1 1 X 0

J K Q(next) Q Q(next) J K
0 0 Q 0 0 0 X
JK 0 1 0 Q(next) = JQ' + K'Q 0 1 1 X
1 0 1 1 0 X 1
1 1 Q' 1 1 X 0

Q Q(next) D
D Q(next) 0 0 0
D 0 0 Q(next) = D 0 1 1
1 1 1 0 0
1 1 1

Q Q(next) T
T Q(next) 0 0 0
T 0 Q Q(next) = TQ' + T'Q 0 1 1
1 Q' 1 0 1
1 1 0

Each of these flip-flops can be uniquely described by its graphical symbol, its characteristic table, its
characteristic equation or excitation table. All flip-flops have output signals Q and Q'.

The characteristic table in the third column defines the state of each flip-flop as a function of its
inputs and previous state. Q refers to the present state and Q(next) refers to the next state after the
occurrence of the clock pulse. The characteristic table for the RS flip-flop shows that the next state is
equal to the present state when both inputs S and R are equal to 0. When R=1, the next clock pulse
clears the flip-flop. When S=1, the flip-flop output Q is set to 1. The equation mark (?) for the next
state when S and R are both equal to 1 designates an indeterminate next state.
The characteristic table for the JK flip-flop is the same as that of the RS when J and K are replaced
by S and R respectively, except for the indeterminate case. When both J and K are equal to 1, the
next state is equal to the complement of the present state, that is, Q(next) = Q'.

The next state of the D flip-flop is completely dependent on the input D and independent of the
present state.

The next state for the T flip-flop is the same as the present state Q if T=0 and complemented if T=1.

The characteristic table is useful during the analysis of sequential circuits when the value of flip-flop
inputs are known and we want to find the value of the flip-flop output Q after the rising edge of the
clock signal. As with any other truth table, we can use the map method to derive the characteristic
equation for each flip-flop, which are shown in the third column

During the design process we usually know the transition from present state to the next state and
wish to find the flip-flop input conditions that will cause the required transition. For this reason we
will need a table that lists the required inputs for a given change of state. Such a list is called the
excitation table, which is shown in the fourth column of Table 1. There are four possible transitions
from present state to the next state. The required input conditions are derived from the information
available in the characteristic table. The symbol X in the table represents a "don't care" condition,
that is, it does not matter whether the input is 1 or 0.

Result and Analysis: Flip-flops (FFs) are devices used in the digital field for a variety of purposes.
Flip-flops are a fundamental building block of digital electronics systems used in computers,
communications, and many other types of systems.. In JK flip-flop, the letter J is for set and the
letter K is for clear. When logic 1 inputs are applied to both J and K simultaneously, the flip-flop
switches to its complement state, ie., if Q=1, it switches to Q=0 and vice versa. Flip-flops and latches
are used as data storage elements. Such data storage can be used for storage of state, and such a
circuit is described as sequential logic. When used in a finite-state machine, the output and next state
depend not only on its current input, but also on its current state (and hence, previous inputs.) It can
also be used for counting of pulses, and for synchronizing variably-timed input signals to some
reference timing signal.