Verilog interview Questions

1) Write a verilog code to swap contents of two registers with and without a temporary register?

With temp reg ;

always @ (posedge clock)

begin
temp=b;
b=a;
a=temp;
end

Without temp reg;

always @ (posedge clock)

begin
a <= b;
b <= a;
end

2) Difference between blocking and non-blocking?(Verilog interview questions that is most commonly asked)

The Verilog language has two forms of the procedural assignment statement: blocking and non-blocking. The two are
distinguished by the = and <= assignment operators. The blocking assignment statement (= operator) acts much like in
traditional programming languages. The whole statement is done before control passes on to the next statement. The non-
blocking (<= operator) evaluates all the right-hand sides for the current time unit and assigns the left-hand sides at the end of
the time unit. For example, the following Verilog program

// testing blocking and non-blocking assignment

module blocking;
reg [0:7] A, B;
initial begin: init1
A = 3;
#1 A = A + 1; // blocking procedural assignment
B = A + 1;

$display("Blocking: A= %b B= %b", A, B ); A = 3;
#1 A <= A + 1; // non-blocking procedural assignment
B <= A + 1;
#1 $display("Non-blocking: A= %b B= %b", A, B );
end
endmodule

produces the following output:

Blocking: A= 00000100 B= 00000101
Non-blocking: A= 00000100 B= 00000100

The effect is for all the non-blocking assignments to use the old values of the variables at the beginning of the current time
unit and to assign the registers new values at the end of the current time unit. This reflects how register transfers occur in
some hardware systems.
blocking procedural assignment is used for combinational logic and non-blocking procedural assignment for sequential
Tell me about verilog file I/O?

OPEN A FILE

integer file;
file = $fopenr("filename");
file = $fopenw("filename");
file = $fopena("filename");
The function $fopenr opens an existing file for reading. $fopenw opens a new file for writing, and $fopena opens a
new file for writing where any data will be appended to the end of the file. The file name can be either a quoted
string or a reg holding the file name. If the file was successfully opened, it returns an integer containing the file
number (1..MAX_FILES) or NULL (0) if there was an error. Note that these functions are not the same as the
built-in system function $fopen which opens a file for writing by $fdisplay. The files are opened in C with 'rb',
'wb', and 'ab' which allows reading and writing binary data on the PC. The 'b' is ignored on Unix.

CLOSE A FILE

integer file, r;
r = $fcloser(file);
r = $fclosew(file);

The function $fcloser closes a file for input. $fclosew closes a file for output. It returns EOF if there was an error,
otherwise 0. Note that these are not the same as $fclose which closes files for writing.

3) Difference between task and function?

Function:
A function is unable to enable a task however functions can enable other functions.
A function will carry out its required duty in zero simulation time. ( The program time will not be incremented
during the function routine)
Within a function, no event, delay or timing control statements are permitted
In the invocation of a function their must be at least one argument to be passed.
Functions will only return a single value and can not use either output or inout statements.

Tasks:
Tasks are capable of enabling a function as well as enabling other versions of a Task
Tasks also run with a zero simulation however they can if required be executed in a non zero simulation time.
Tasks are allowed to contain any of these statements.
A task is allowed to use zero or more arguments which are of type output, input or inout.
A Task is unable to return a value but has the facility to pass multiple values via the output and inout statements .
4) Difference between inter statement and intra statement delay?

//define register variables

reg a, b, c;

//intra assignment delays

initial
begin
a = 0; c = 0;
b = #5 a + c; //Take value of a and c at the time=0, evaluate
//a + c and then wait 5 time units to assign value
//to b.
end

//Equivalent method with temporary variables and regular delay control

initial
begin
a = 0; c = 0;
temp_ac = a + c;
#5 b = temp_ac; //Take value of a + c at the current time and
//store it in a temporary variable. Even though a and c
//might change between 0 and 5,
//the value assigned to b at time 5 is unaffected.
end

5) What is delta simulation time?

6) Difference between $monitor, $display & $strobe?

These commands have the same syntax, and display text on the screen during simulation. They are much less
convenient than waveform display tools like cwaves?. $display and $strobe display once every time they are
executed, whereas $monitor displays every time one of its parameters changes.
The difference between $display and $strobe is that $strobe displays the parameters at the very end of the current
simulation time unit rather than exactly where it is executed. The format string is like that in C/C++, and may
contain format characters. Format characters include %d (decimal), %h (hexadecimal), %b (binary), %c
(character), %s (string) and %t (time), %m (hierarchy level). %5d, %5b etc. would give exactly 5 spaces for the
number instead of the space needed. Append b, h, o to the task name to change default format to binary, octal or
hexadecimal.
Syntax:
$display (format_string, par_1, par_2, ... );
$strobe (format_string, par_1, par_2, ... );
$monitor (format_string, par_1, par_2, ... );

7) What is difference between Verilog full case and parallel case?

A "full" case statement is a case statement in which all possible case-expression binary patterns can be matched to
a case item or to a case default. If a case statement does not include a case default and if it is possible to find a
binary case expression that does not match any of the defined case items, the case statement is not "full."
A "parallel" case statement is a case statement in which it is only possible to match a case expression to one and
only one case item. If it is possible to find a case expression that would match more than one case item, the
matching case items are called "overlapping" case items and the case statement is not "parallel."

8) What is meant by inferring latches,how to avoid it?

Consider the following :

always @(s1 or s0 or i0 or i1 or i2 or i3)
case ({s1, s0})
2'd0 : out = i0;
2'd1 : out = i1;
2'd2 : out = i2;
endcase

in a case statement if all the possible combinations are not compared and default is also not specified like in example above a
latch will be inferred ,a latch is inferred because to reproduce the previous value when unknown branch is specified.
For example in above case if {s1,s0}=3 , the previous stored value is reproduced for this storing a latch is inferred.
The same may be observed in IF statement in case an ELSE IF is not specified.
To avoid inferring latches make sure that all the cases are mentioned if not default condition is provided.

9) Tell me how blocking and non blocking statements get executed?

Execution of blocking assignments can be viewed as a one-step process:

1. Evaluate the RHS (right-hand side equation) and update the LHS (left-hand side expression) of the blocking
assignment without interruption from any other Verilog statement. A blocking assignment "blocks" trailing
assignments in the same always block from occurring until after the current assignment has been completed

Execution of nonblocking assignments can be viewed as a two-step process:

1. Evaluate the RHS of nonblocking statements at the beginning of the time step. 2. Update the LHS of
nonblocking statements at the end of the time step.
10) Variable and signal which will be Updated first?
Signals

11) What is sensitivity list?

The sensitivity list indicates that when a change occurs to any one of elements in the list change, beginend
statement inside that always block will get executed.

12) In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? if yes, why?

Yes in a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk other wise it will
result in pre and post synthesis mismatch.

13) Tell me structure of Verilog code you follow?

A good template for your Verilog file is shown below.

// timescale directive tells the simulator the base units and precision of the simulation
`timescale 1 ns / 10 ps
module name (input and outputs);
// parameter declarations
parameter parameter_name = parameter value;
// Input output declarations
input in1;
input in2; // single bit inputs
output [msb:lsb] out; // a bus output
// internal signal register type declaration - register types (only assigned within always statements). reg register variable 1;
reg [msb:lsb] register variable 2;
// internal signal. net type declaration - (only assigned outside always statements) wire net variable 1;
// hierarchy - instantiating another module
reference name instance name (
.pin1 (net1),
.pin2 (net2),
.
.pinn (netn)
);
// synchronous procedures
always @ (posedge clock)
begin
.
end
// combinatinal procedures
always @ (signal1 or signal2 or signal3)
begin
.
end
assign net variable = combinational logic;
endmodule
14) Difference between Verilog and vhdl?

Compilation
VHDL. Multiple design-units (entity/architecture pairs), that reside in the same system file, may be separately
compiled if so desired. However, it is good design practice to keep each design unit in it's own system file in which
case separate compilation should not be an issue.

Verilog. The Verilog language is still rooted in it's native interpretative mode. Compilation is a means of speeding
up simulation, but has not changed the original nature of the language. As a result care must be taken with both the
compilation order of code written in a single file and the compilation order of multiple files. Simulation results can
change by simply changing the order of compilation.

Data types
VHDL. A multitude of language or user defined data types can be used. This may mean dedicated conversion
functions are needed to convert objects from one type to another. The choice of which data types to use should be
considered wisely, especially enumerated (abstract) data types. This will make models easier to write, clearer to
read and avoid unnecessary conversion functions that can clutter the code. VHDL may be preferred because it
allows a multitude of language or user defined data types to be used.

Verilog. Compared to VHDL, Verilog data types a re very simple, easy to use and very much geared towards
modeling hardware structure as opposed to abstract hardware modeling. Unlike VHDL, all data types used in a
Verilog model are defined by the Verilog language and not by the user. There are net data types, for example wire,
and a register data type called reg. A model with a signal whose type is one of the net data types has a
corresponding electrical wire in the implied modeled circuit. Objects, that is signals, of type reg hold their value
over simulation delta cycles and should not be confused with the modeling of a hardware register. Verilog may be
preferred because of it's simplicity.

Design reusability
VHDL. Procedures and functions may be placed in a package so that they are avail able to any design-unit that
wishes to use them.

Verilog. There is no concept of packages in Verilog. Functions and procedures used within a model must be
defined in the module. To make functions and procedures generally accessible from different module statements
the functions and procedures must be placed in a separate system file and included using the `include compiler
directive.

15) What are different styles of Verilog coding I mean gate-level, continuous level and others explain in
detail?
16) Can you tell me some of system tasks and their purpose?

$display, $displayb, $displayh, $displayo, $write, $writeb, $writeh, $writeo.

The most useful of these is $display.This can be used for displaying strings, expression or values of variables.
Here are some examples of usage.
$display("Hello oni");
--- output: Hello oni
$display($time) // current simulation time.
--- output: 460
counter = 4'b10;
$display(" The count is %b", counter);
--- output: The count is 0010
$reset resets the simulation back to time 0; $stop halts the simulator and puts it in interactive mode where the
user can enter commands; $finish exits the simulator back to the operating system

17) Can you list out some of enhancements in Verilog 2001?

In earlier version of Verilog ,we use 'or' to specify more than one element in sensitivity list . In Verilog 2001, we
can use comma as shown in the example below.
// Verilog 2k example for usage of comma
always @ (i1,i2,i3,i4)

Verilog 2001 allows us to use star in sensitive list instead of listing all the variables in RHS of combo logics . This
removes typo mistakes and thus avoids simulation and synthesis mismatches,
Verilog 2001 allows port direction and data type in the port list of modules as shown in the example below
module memory (
input r,
input wr,
input [7:0] data_in,
input [3:0] addr,
output [7:0] data_out
);

18)Write a Verilog code for synchronous and asynchronous reset?

Synchronous reset, synchronous means clock dependent so reset must not be present in sensitivity disk eg:
always @ (posedge clk )

begin if (reset)
. . . end
Asynchronous means clock independent so reset must be present in sensitivity list.
Eg
Always @(posedge clock or posedge reset)
begin
if (reset)
. . . end
19) What is pli?why is it used?

Programming Language Interface (PLI) of Verilog HDL is a mechanism to interface Verilog programs with
programs written in C language. It also provides mechanism to access internal databases of the simulator from the
C program.
PLI is used for implementing system calls which would have been hard to do otherwise (or impossible) using
Verilog syntax. Or, in other words, you can take advantage of both the paradigms - parallel and hardware related
features of Verilog and sequential flow of C - using PLI.

20) There is a triangle and on it there are 3 ants one on each corner and are free to move along sides of
triangle what is probability that they will collide?

Ants can move only along edges of triangle in either of direction, lets say one is represented by 1 and another by
0, since there are 3 sides eight combinations are possible, when all ants are going in same direction they wont
collide that is 111 or 000 so probability of not collision is 2/8=1/4 or collision probability is 6/8=3/4

How to write FSM is verilog?

there r mainly 4 ways 2 write fsm code

1) using 1 process where all input decoder, present state, and output decoder r combine in one process.
2) using 2 process where all comb ckt and sequential ckt separated in different process
3) using 2 process where input decoder and persent state r combine and output decoder seperated in
other process
4) using 3 process where all three, input decoder, present state and output decoder r separated in 3
process.

21)What is difference between freeze deposit and force?

$deposit(variable, value);
This system task sets a Verilog register or net to the specified value. variable is the
register or net to be changed; value is the new value for the register or net. The value
remains until there is a subsequent driver transaction or another $deposit task for the
same register or net. This system task operates identically to the ModelSim
force -deposit command.

The force command has -freeze, -drive, and -deposit options. When none of these is
specified, then -freeze is assumed for unresolved signals and -drive is assumed for resolved
signals. This is designed to provide compatibility with force files. But if you prefer -freeze
as the default for both resolved and unresolved signals.

22)Will case infer priority register if yes how give an example?

yes case can infer priority register depending on coding style
reg r;
// Priority encoded mux,
always @ (a or b or c or select2)
begin
r = c;
case (select2)
2'b00: r = a;
2'b01: r = b;
endcase
end

23)Casex, z difference, which is preferable, why?

CASEZ :
Special version of the case statement which uses a Z logic value to represent don't-care bits.
CASEX :
Special version of the case statement which uses Z or X logic values to represent don't-care bits.

CASEZ should be used for case statements with wildcard dont cares, otherwise use of CASE is
required; CASEX should never be used.
This is because:
Dont cares are not allowed in the "case" statement. Therefore casex or casez are required. Casex will
automatically match any x or z with anything in the case statement. Casez will only match zs -- xs
require an absolute match.

24)Given the following Verilog code, what value of "a" is displayed?

always @(clk) begin

a = 0;
a <= 1;
$display(a);
end

This is a tricky one! Verilog scheduling semantics basically imply a

four-level deep queue for the current simulation time:
1: Active Events (blocking statements)
2: Inactive Events (#0 delays, etc)
3: Non-Blocking Assign Updates (non-blocking statements)
4: Monitor Events ($display, $monitor, etc).
Since the "a = 0" is an active event, it is scheduled into the 1st "queue".
The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue.
Finally, the display statement is placed into the 4th queue. Only events in the active queue are completed this sim cycle, so the "a = 0" happens, and then
the display shows a = 0. If we were to look at the value of a in the next sim cycle, it would show 1.

25) What is the difference between the following two lines of Verilog code?
#5 a = b;
a = #5 b;

#5 a = b; Wait five time units before doing the action for "a = b;".
a = #5 b; The value of b is calculated and stored in an internal temp register,After five time units,
assign this stored value to a.

26)What is the difference between:

c = foo ? a : b;
and
if (foo) c = a;
else c = b;

The ? merges answers if the condition is "x", so for instance if foo = 1'bx, a = 'b10, and b = 'b11, you'd
get c = 'b1x. On the other hand, if treats Xs or Zs as FALSE, so you'd always get c = b.

27)What are Intertial and Transport Delays ??

28)What does `timescale 1 ns/ 1 ps signify in a verilog code?

'timescale directive is a compiler directive.It is used to measure simulation time or delay time. Usage :
`timescale / reference_time_unit : Specifies the unit of measurement for times and delays. time_precision:
specifies the precision to which the delays are rounded off.

29) What is the difference between === and == ?

output of "==" can be 1, 0 or X.

output of "===" can only be 0 or 1.
When you are comparing 2 nos using "==" and if one/both the numbers have one or more bits as "x" then the
output would be "X" . But if use "===" outpout would be 0 or 1.
e.g A = 3'b1x0
B = 3'b10x
A == B will give X as output.
A === B will give 0 as output.
"==" is used for comparison of only 1's and 0's .It can't compare Xs. If any bit of the input is X output will be X
"===" is used for comparison of X also.

30)How to generate sine wav using verilog coding style?

A: The easiest and efficient way to generate sine wave is using CORDIC Algorithm.

31) What is the difference between wire and reg?

Net types: (wire,tri)Physical connection between structural elements. Value assigned by a continuous assignment
or a gate output. Register type: (reg, integer, time, real, real time) represents abstract data storage element.
Assigned values only within an always statement or an initial statement. The main difference between wire and reg
is wire cannot hold (store) the value when there no connection between a and b like a->b, if there is no connection
in a and b, wire loose value. But reg can hold the value even if there in no connection. Default values:wire is Z,reg
is x.

32 )How do you implement the bi-directional ports in Verilog HDL?

module bidirec (oe, clk, inp, outp, bidir);

// Port Declaration
input oe;
input clk;
input [7:0] inp;
output [7:0] outp;
inout [7:0] bidir;
reg [7:0] a;
reg [7:0] b;
assign bidir = oe ? a : 8'bZ ;
assign outp = b;
// Always Construct
always @ (posedge clk)
begin
b <= bidir;
a <= inp;
end
endmodule

34)what is verilog case (1) ?

wire [3:0] x;
always @(...) begin
case (1'b1)
x[0]: SOMETHING1;
x[1]: SOMETHING2;
x[2]: SOMETHING3;
x[3]: SOMETHING4;
endcase
end
The case statement walks down the list of cases and executes the first one that matches. So here, if the lowest 1-bit
of x is bit 2, then something3 is the statement that will get executed (or selected by the logic).

35) Why is it that "if (2'b01 & 2'b10)..." doesn't run the true case?

This is a popular coding error. You used the bit wise AND operator (&) where you meant to use the logical AND
operator (&&).

36)What are Different types of Verilog Simulators ?

There are mainly two types of simulators available.

Event Driven
Cycle Based

Event-based Simulator:

This Digital Logic Simulation method sacrifices performance for rich functionality: every active signal is
calculated for every device it propagates through during a clock cycle. Full Event-based simulators support 4-28
states; simulation of Behavioral HDL, RTL HDL, gate, and transistor representations; full timing calculations for
all devices; and the full HDL standard. Event-based simulators are like a Swiss Army knife with many different
features but none are particularly fast.

Cycle Based Simulator:

This is a Digital Logic Simulation method that eliminates unnecessary calculations to achieve huge performance
gains in verifying Boolean logic:

1.) Results are only examined at the end of every clock cycle; and
2.) The digital logic is the only part of the design simulated (no timing calculations). By limiting the calculations,
Cycle based Simulators can provide huge increases in performance over conventional Event-based simulators.
Cycle based simulators are more like a high speed electric carving knife in comparison because they focus on a
subset of the biggest problem: logic verification.
Cycle based simulators are almost invariably used along with Static Timing verifier to compensate for the lost
timing information coverage.

37)What is Constrained-Random Verification ?

Introduction

As ASIC and system-on-chip (SoC) designs continue to increase in size and complexity, there is an equal or
greater increase in the size of the verification effort required to achieve functional coverage goals. This has created
a trend in RTL verification techniques to employ constrained-random verification, which shifts the emphasis from
hand-authored tests to utilization of compute resources. With the corresponding emergence of faster, more
complex bus standards to handle the massive volume of data traffic there has also been a renewed significance for
verification IP to speed the time taken to develop advanced testbench environments that include randomization of
bus traffic.

Directed-Test Methodology

Building a directed verification environment with a comprehensive set of directed tests is extremely time-
consuming and difficult. Since directed tests only cover conditions that have been anticipated by the verification
team, they do a poor job of covering corner cases. This can lead to costly re-spins or, worse still, missed market
windows.

Traditionally verification IP works in a directed-test environment by acting on specific testbench commands such
as read, write or burst to generate transactions for whichever protocol is being tested. This directed traffic is used
to verify that an interface behaves as expected in response to valid transactions and error conditions. The drawback
is that, in this directed methodology, the task of writing the command code and checking the responses across the
full breadth of a protocol is an overwhelming task. The verification team frequently runs out of time before a
mandated tape-out date, leading to poorly tested interfaces. However, the bigger issue is that directed tests only test
for predicted behavior and it is typically the unforeseen that trips up design teams and leads to extremely costly
bugs found in silicon.

Constrained-Random Verification Methodology

The advent of constrained-random verification gives verification engineers an effective method to achieve
coverage goals faster and also help find corner-case problems. It shifts the emphasis from writing an enormous
number of directed tests to writing a smaller set of constrained-random scenarios that let the compute resources do
the work. Coverage goals are achieved not by the sheer weight of manual labor required to hand-write directed
tests but by the number of processors that can be utilized to run random seeds. This significantly reduces the time
required to achieve the coverage goals.

Scoreboards are used to verify that data has successfully reached its destination, while monitors snoop the
interfaces to provide coverage information. New or revised constraints focus verification on the uncovered parts of
the design under test. As verification progresses, the simulation tool identifies the best seeds, which are then
retained as regression tests to create a set of scenarios, constraints, and seeds that provide high coverage of the
design.
What are the differences between blocking and nonblocking assignments?

While both blocking and nonblocking assignments are procedural assignments, they differ in behavior with respect
to simulation and logic
synthesis as follows:
How can I model a bi-directional net with assignments influencing both source and destination?

The assign statement constitutes a continuous assignment. The changes on the RHS of the statement
immediately reflect on the LHS net. However, any changes on the LHS don't get reflected on the RHS. For
example, in the following statement, changes to the rhs net will update the lhs net, but not vice versa.

System Verilog has introduced a keyword alias, which can be used only on nets to have a two-way
assignment. For example, in the following code, any changes to the rhs is reflected to the lh s , and vice
versa.

wire rhs , lhs

assign lhs=rhs;

System Verilog has introduced a keyword alias, which can be used only on nets to have a two-way
assignment. For example, in the following code, any changes to the rhs is reflected to the lh s , and vice
versa.

module test ();

wire rhs,lhs;

alias lhs=rhs;

In the above example, any change to either side of the net gets reflected on the other side.

Are tasks and functions re-entrant, and how are they different from static task and function calls?

The reentrant tasks have a keyword automatic between the keyword task and the name of the task.
The presence of the keyword automatic replicates and allocates the variables within a task
dynamically for each task entry during concurrent task calls, i.e., the values dont get overwritten
for each task call. Without the keyword, the variables are allocated statically, which means these
variables are shared across different task calls, and can hence get overwritten by each task call.
How can I override variables in an automatic task?

By default, all variables in a module are static, i.e., these variables will be replicated for all
instances of a module. However, in the case of task and function, either the task/function itself or
the variables within them can be defined as static or automatic. The following explains the
inferences through different combinations of the task/function and/or its variables, declared either
as static or automatic:

No automatic definition of task/function or its variables This is the Verilog-1995 format, wherein the
task/function and its variables were implicitly static. The variables are allocated only once. Without
the mention of the automatic keyword, multiple calls to task/function will override their variables.

static task/function definition

System Verilog introduced the keyword static. When a task/function is explicitly defined as static,
then its variables are allocated only once, and can be overridden. This scenario is exactly the same
scenario as before.

automatic task/function definition

From Verilog-2001 onwards, and included within SystemVerilog, when the task/function is declared
as automatic, its variables are also implicitly automatic. Hence, during multiple calls of the
task/function, the variables are allocated each time and replicated without any overwrites.

static task/function and automatic variables

SystemVerilog also allows the use of automatic variables in a static task/function. Those without
any changes to automatic variables will remain implicitly static. This will be useful in scenarios
wherein the implicit static variables need to be initialised before the task call, and the automatic
variables can be allocated each time.

automatic task/function and static variables

SystemVerilog also allows the use of static variables in an automatic task/function. Those without
any changes to static variables will remain implicitly automatic. This will be useful in scenarios
wherein the static variables need to be updated for each call, whereas the rest can be allocated
each time.

What are the rules governing usage of a Verilog function?

The following rules govern the usage of a Verilog function construct:

A function cannot advance simulation-time, using constructs like #, @. etc.

A function shall not have nonblocking assignments.
A function without a range defaults to a one bit reg for the return value.
It is illegal to declare another object with the same name as the function in the scope where the
function is declared.
How do I prevent selected parameters of a module from being overridden during instantiation?

If a particular parameter within a module should be prevented from being overridden, then it
should be declared using the localparam construct, rather than the parameter construct. The
localparam construct has been introduced from Verilog-2001. Note that a localparam variable is
fully identical to being defined as a parameter, too. In the following example, the localparam
construct is used to specify num_bits, and hence trying to override it directly gives an error
message.

Note, however, that, since the width and depth are specified using the parameter construct, they
can be overridden during instantiation or using defparam, and hence will indirectly override the
num_bits values. In general, localparam constructs are useful in defining new and localized
identifiers whose values are derived from regular parameters.

What are the pros and cons of specifying the parameters using the defparam construct vs. specifying during
instantiation?

The advantages of specifying parameters during instantiation method are:

All the values to all the parameters dont need to be specified. Only those parameters that are assigned the
new values need to be specified. The unspecified parameters will retain their default values specified within
its module definition.

The order of specifying the parameter is not relevant anymore, since the parameters are directly specified
and linked by their name.

The disadvantage of specifying parameter during instantiation are:

This has a lower precedence when compared to assigning using defparam.

The advantages of specifying parameter assignments using defparam are:

This method always has precedence over specifying parameters during instantiation.

All the parameter value override assignments can be grouped inside one module and together in one place,
typically in the top-level testbench itself.

When multiple defparams for a single parameter are specified, the parameter takes the value of the last
defparam statement encountered in the source if, and only if, the multiple defparams are in the same file. If
there are defparams in different files that override the same parameter, the final value of the parameter is
indeterminate.

The disadvantages of specifying parameter assignments using defparam are:

The parameter is typically specified by the scope of the hierarchies underneath which it exists. If a particular
module gets ungrouped in its hierarchy, [sometimes necessary during synthesis], then the scope to specify
the parameter is lost, and is unspecified. B
For example, if a module is instantiated in a simulation testbench, and its internal parameters are then
overridden using hierarchical defparam constructs (For example, defparam U1.U_fifo.width = 32;). Later,
when this module is synthesized, the internal hierarchy within U1 may no longer exist in the gate-level netlist,
depending upon the synthesis strategy chosen. Therefore post-synthesis simulation will fail on the
hierarchical defparam override.

Can there be full or partial no-connects to a multi-bit port of a module during its instantiation?

No. There cannot be full or partial no-connects to a multi-bit port of a module during instantiation

What happens to the logic after synthesis, that is driving an unconnected output port that is left open (, that
is, noconnect) during its module instantiation?

An unconnected output port in simulation will drive a value, but this value does not propagate to
any other logic. In synthesis, the cone of any combinatorial logic that drives the unconnected
output will get optimized away during boundary optimisation, that is, optimization by synthesis
tools across hierarchical boundaries.

How is the connectivity established in Verilog when connecting wires of different widths?

When connecting wires or ports of different widths, the connections are right-justified, that is, the
rightmost bit on the RHS gets connected to the rightmost bit of the LHS and so on, until the MSB of
either of the net is reached.

Can I use a Verilog function to define the width of a multi-bit port, wire, or reg type?

The width elements of ports, wire or reg declarations require a constant in both MSB and LSB.
Before Verilog 2001, it is a syntax error to specify a function call to evaluate the value of these
widths. For example, the following code is erroneous before Verilog 2001 version.

reg [ port1(val1:vla2) : port2 (val3:val4)] reg1;

In the above example, get_high and get_low are both function calls of evaluating a constant result
for MSB and LSB respectively. However, Verilog-2001 allows the use of a function call to evaluate
the MSB or LSB of a width declaration

What is the implication of a combinatorial feedback loops in design testability?

The presence of feedback loops should be avoided at any stage of the design, by periodically
checking for it, using the lint or synthesis tools. The presence of the feedback loop causes races
and hazards in the design, and 104 RTL Design
leads to unpredictable logic behavior. Since the loops are delay-dependent, they cannot be tested
with any ATPG algorithm. Hence, combinatorial loops should be avoided in the logic.

What are the various methods to contain power during RTL coding?

Any switching activity in a CMOS circuit creates a momentary current flow from VDD to GND during
logic transition, when both N and P type transistors are ON, and, hence, increases power
consumption.
The most common storage element in the designs being the synchronous FF, its output can change
whenever its data input toggles, and the clock triggers. Hence, if these two elements can be
asserted in a controlled fashion, so that the data is presented to the D input of the FF only when
required, and the clock is also triggered only when required, then it will reduce the switching
activity, and, automatically the power.

The following bullets summarize a few mechanisms to reduce the power consumption:

Reduce switching of the data input to the Flip-Flops.

Reduce the clock switching of the Flip-Flops.

Have area reduction techniques within the chip, since the number of
gates/Flip-Flops that toggle can be reduced.

How do I model Analog and Mixed-Signal blocks in Verilog?

First, this is a big area.Analog and Mixed-Signal designers use tools like Spice to fully characterize and model their
designs.My only involvement with Mixed-Signal blocks has been to utilize behavioral models of things like PLLs, A/Ds,
D/As within a larger SoC.There are some specific Verilog tricks to this which is what this FAQ is about (I do not wish to
trivialize true Mixed-Signal methodology, but us chip-level folks need to know this trick).

A mixed-signal behavioral model might model the digital and analog input/output behavior of, for example, a D/A (Digital to
Analog Converter).So, digital input in and analog voltage out.Things to model might be the timing (say, the D/A utilizes an
internal Success Approximation algorithm), output range based on power supply voltages, voltage biases, etc.A behavioral
model may not have any knowledge of the physical layout and therefore may not offer any fidelity whatsoever in terms of
noise, interface, cross-talk, etc.A model might be parameterized given a specific characterization for a block.Be very careful
about the assumptions and limitations of the model!

Issue #1; how do we model analog voltages in Verilog.Answer: use the Verilog real data type, declare analog wires as
wire[63:0] in order to use a 64-bit floating-type represenation, and use the built-in PLI functions:

$rtoi converts reals to integers w/truncation e.g. 123.45 -> 123

$itor converts integers to reals e.g. 123 -> 123.0

$realtobits converts reals to 64-bit vector

$bitstoreal converts bit pattern to real

That was a lot.This is a trick to be used in vanilla Verilog.The 64-bit wire is simply a ways to actually interface to the ports of
the mixed-signal block.In other words, our example D/A module may have an output called AOUT which is a voltage.Verilog
does not allow us to declare an output port of type REAL.So, instead declare AOUT like this:

module dtoa (clk, reset..... aout.....);

....

wire [63:0]aout;// Analog output

....

We use 64 bits because we can use floating-point numbers to represent out voltage output (e.g. 1.22x10-3 for 1.22
millivolts).The floating-point value is relevant only to Verilog and your workstation and processor, and the IEEE floating-
point format has NOTHING to do with the D/A implementation.Note the disconnect in terms of the netlist itself.The physical
netlist that you might see in GDS may have a single metal interconnect that is AOUT, and obviously NOT 64 metal
wires.Again, this is a trick.The 64-bit bus is only for wiring.You may have to do some quick netlist substitutions when you
hand off a netlist.

In Verilog, the real data type is basically a floating-point number (e.g. like double in C).If you want to model an analog value
either within the mixed-signal behavorial model, or externally in the system testbench (e.g. the sensor or actuator), use the
real data type.You can convert back and forth between real and your wire [63:0] using the PLI functions listed above.A trivial
D/A model could simply take the digital input value, convert it to real, scale it according to some #defines, and output the
value on AOUT as the 64-bit psuedo-analog value.Your testbench can then do the reverse and print out the value, or
whatever.More sophisticated models can model the Successive Approximation algorithm, employ look-ups, equations, etc.
etc.

Thats it.If you are getting a mixed-signal block from a vendor, then you may also receive (or you should ask for) the
behavioral Verilog models for the IP.

How do I synthesize Verilog into gates with Synopsys?

The answer can, of course, occupy several lifetimes to completely answer.. BUT.. a straight-forward Verilog module can be
very easily synthesized using Design Compiler (e.g. dc_shell). Most ASIC projects will create very elaborate synthesis
scripts, CSH scripts, Makefiles, etc. This is all important in order automate the process and generalize the synthesis
methodology for an ASIC project or an organization. BUT don't let this stop you from creating your own simple dc_shell
experiments!

Let's say you create a Verilog module named foo.v that has a single clock input named 'clk'. You want to synthesize it so that
you know it is synthesizable, know how big it is, how fast it is, etc. etc. Try this:

target_library = { CORELIB.db } <--- This part you need to get from your vendor...
read -format verilog foo.v
create_clock -name clk -period 37.0
set_clock_skew -uncertainty 0.4 clk
set_input_delay 1.0 -clock clk all_inputs() - clk - reset
set_output_delay 1.0 -clock clk all_outputs()
compile
report_area
report_timing
write -format db -hierarchy -output foo.db
write -format verilog -hierarchy -output foo.vg
quit

You can enter all this in interactively, or put it into a file called 'synth_foo.scr' and then enter:

dc_shell -f synth_foo.scr

You can spend your life learning more and more Synopsys and synthesis-related commands and techniques, but don't be
afraid to begin using these simple commands.
How can I pass parameters to my simulation?

A testbench and simulation will likely need many different parameters and settings for different sorts of tests and conditions.
It is definitely a good idea to concentrate on a single testbench file that is parameterized, rather than create a dozen seperate,
yet nearly identical, testbenches. Here are 3 common techniques:

Use a define. This is almost exactly the same approach as the #define and -D compiler
arg that C programs use. In your Verilog code, use a `define to define the variable condition
and then use the Verilog preprocessor directives like `ifdef. Use the '+define+' Verilog
command line option. For example:
... to run the simulation ..

verilog testbench.v cpu.v +define+USEWCSDF

... in your code ...
`ifdef USEWCSDF
initial $sdf_annotate (testbench.cpu, "cpuwc.sdf");
`endif

The +define+ can also be filled in from your Makefile invocation, which in turn, can be finally
filled in the your UNIX promp command line.
Defines are a blunt weapon because they are very global and you can only do so much with
them since they are a pre-processor trick. Consider the next approach before resorting to
defines.
Use parameters and parameter definition modules. Parameters are not preprocessor
definitions and they have scope (e.g. parameters are associated with specific modules).
Parameters are therefore more clean, and if you are in the habit of using a lot of defines;
consider switching to parameters. As an example, lets say we have a test (e.g. test12) which
needs many parameters to have particular settings. In your code, you might have this sort of
stuff:
module testbench_uart1 (....)
parameter BAUDRATE = 9600;
...
if (BAUDRATE > 9600) begin
... E.g. use the parameter in your code like you might any general variable
... BAUDRATE is completely local to this module and this instance. You might
... have the same parameters in 3 other UART instances and they'd all be different
... values...
Now, your test12 has all kinds of settings required for it. Let's define a special module
called testparams which specifies all these settings. It will itself be a module instantiated
under the testbench:
module testparams;
defparam testbench.cpu.uart1.BAUDRATE = 19200;
 defparam testbench.cpu.uart2.BAUDRATE = 9600;
defparam testbench.cpu.uart3.BAUDRATE = 9600;
defparam testbench.clockrate CLOCKRATE = 200; // Period in ns.
... etc ...
endmodule

The above module always has the same module name, but you would have many different
filenames; one for each test. So, the above would be kept in test12_params.v. Your
Makefile includes the appropriate params file given the desired make target. (BTW: You
may run across this sort of technique by ASIC vendors who might have a module containing
parameters for a memory model, or you might see this used to collect together a large
number of system calls that turn off timing or warnings on particular troublesome nets, etc.
etc.)
Use memory blocks. Not as common a technique, but something to consider. Since
Verilog has a very convenient syntax for declaring and loading memories, you can store your
input data in a hex file and use $readmemh to read all the data in at once.
In your testbench:

module testbench;
...
reg [31:0] control[0:1023];
...
initial $readmemh ("control.hex", control);
...
endmodule

You could vary the filename using the previous techniques. The control.hex file is just a file
of hex values for the parameters. Luckily, $readmemh allows embedded comments, so you
can keep the file very readable:
A000 // Starting address to put boot code in
10 // Activate all ten input pulse sources
... etc...

Obviously, you are limitied to actual hex values with this approach. Note, of course, that

you are free to mix and match all of these techniques!

RTL Coding for Logic Synthesis
1.1. Synthesizable and Non-Synthesizable Verilog constructs

Synthesizable Non-Synthesizable

Identifiers, escaped identifiers, Sized constants (b, o, d, h),

Unsized constants (2'b11, 3'07, 32'd123, 8'hff), Signed constants
(s) 3'bs101, module, endmodule, macromodule, ANSI-style system tasks, real
Basic module, task, and function port lists constants

wire, wand, wor, tri, triand, trior, supply0, supply1, trireg

(treated as wire), reg, integer, parameter, input, output, inout, real, time, event, tri0,
Data types memory(reg [7:0] x [3:0];), N-dimensional arrays, tri1

Connect port by name, order, Override parameter by order,

Module Override parameter by name, Constants connected to ports,
instances Unconnected ports, Expressions connected to ports, Delay on built-in gates

Generate
statements if,case,for generate, concurrent begin end blocks, genvar,

User defined primitives

(UDPs), table, pullup,
pulldown, pmos, nmos,
cmos, rpmos, rnmos,
rcmos, tranif0, tranif1,
and, or, nand, nor, xor, xnor,not, notif0, notif1, buf, bufif0, bufif1, rtran, rtranif0,
Primitives tran, rtranif1,

Operators
and
expressions +, - (binary and unary)

Bitwise
operations &, |, ^, ~^, ^~

Reduction &, |, ^, ~&, ~|, ~^, ^~, !, &&, || , ==, !=, <, <=, >, >=, <<, ===, !==
 operations >>, <<< >>>, {}, {n{}}, ?:, function call

Event event or, @ (partial), event or using comma syntax, posedge, Event trigger (->), delay
control negedge (partial), and wait (#)

Bit select, Bit select of array element, Constant part select,

Bit and part Variable part select ( +:, -:), Variable bit-select on left side of an
selects assignment

Continuous
assignment
s net and wire declaration, assign Using delay

Procedural
blocks always (exactly one @ required), initial

Procedural ;, begin-end, if-else, repeat, case, casex, casez, default, for-

statements while-forever-disable(partial), fork, join

Procedural
assignment
s blocking (=), non-blocking (<=) force, release

Functions
and tasks Functions, tasks

Compiler `define, `undef, `resetall, `ifndef, `elsif, `line, `ifdef, `else,

directives `endif, `include

1.2. How hardware is infered?

1.2.1 Register inference

Whenever there is a posedge or negedge construct synthesis tool infers a flip flop.

always @(posedge clk)

output_reg <= data;

Above code infers D-flip flop.

Asynchronous reset :
module async_rst(clk,rst,data,out);

input clk, rst, data;

output out;

reg out;

always @(posedge clk or negedge rst)

begin

if(!rst)

out<=1b0;

else

out<=data;

end

endmodule

In above case the sensitivity list includes both clock and the rst and hence it infers a asynchronous
reset flip flop. rst has negedge in sensitivity list and hence same should be checked in the code.
Synchronous Reset:
module sync_rst(clk,rst,data,out);

input clk, rst, data;

output out;

reg out;

always @(posedge clk)

begin

if(!rst)

out<=1b0;

else

out<=data; end endmodule

In above case the sensitivity list doesnt include rst and hence it infers a synchronous reset
flip flop.

1.2.2 Mux Inference

if else loop infers a mux.
eg.:
if(sel) z=a; else z=b;

General case statement infers a mux. If case statement is a overlapping structure then priority
encoder in infered. Case statements only works with true values of 0 or 1.

1.2.3. Priority Encoder Inference

 Multiple if statements with multiple branches result in the creation of priority encoder structure.
if else if infers priority encoder.

1.2.4. Combo Logics

If unknown x or z is assigned then it will be realized into tristate buffer. So avoid using x and z.
usage of these may mislead synthesis.
Eg.:
assign tri_out=en ? tri_in : 1bz;

1.2.5. if vs case
Multiflexer is faster circuit. Therefore is priority encoding structure is not required then use case
staements instead of if-else statement.
Use late arriving signal early in an if-else loop to keep these late arriving signals with critical
timing closest to the output of a logic block.

1.2.6. Proper partitioning for synthesis

Properly partition the top level design based on functionality. Keep related combinational logic in
same module. It is not recommended to add glue logic at top level of the module. Heirarchical
designs are good but unnecessary heirachies may limit the optimizations across the heirarchies. It
is pracically observed that deeper heirarchies cause miserably failing boundary optimizations due
to incresed number of either setup or hold fixing buffer insertion. In such cases ungrouping or
flattening heirachy command can be used to flatten the unwanted heirarchies before cmpiling the
design to achieve better results.

1.2.7 FSM synthesis guidelines

If you are using state machine for coding then take care to separate it from other logic. This helps
synthesis tools to synthesize and optimize FSM logic much better. Use parameter in Verilog to
describe state names. A always block should have all the combinational logic for computing the
next state.

1.2.8. Blocking vs non-blocking-race condition

Never mix a description of combinational (blocking) construct with sequential
(nonblocking).
Blocking: combinational racing
Since the final outputs depends on the order in which the assignments are evaluated, blocking
assignments within sequential block may cause race condition.
 Nonblocking: sequential No race condition
Nonblockng assignments closely resemble hardware as they are order independent.
Most of the applications which require data tranfer within module required to be written
using non-blocking assignment statement.
1.2.9. Technology independent RTL coding
Write HDL code in technology independent fasion. This helps reusage of the HDL code for any
technology node. Do not hard code logic gates from the technology library unless it is necessary to
meet critical timing issues.

1.2.10. Pads separate from core logic

Pads are instantiated like any other module instantiation. If design has large number of I/O pads it
is recommended to keep the pad instantiations in a separate file. Note that pads are technology
dependant and hence the above recommendation!

1.2.11. Clock logic guidelines

In case of multiple clocks in the design, make sure that clock generation and reset logics are
written in one module for better handling in synthesis. If a clock is used in different modules of
different heirarchy then keep clock names common across all the modules. This makes constraining
that clock easier and also supports better handling of synthesis scripts.

Dont use mixed clock edges

mixing of edge sensitive and level sensitive lists are not allowed. Below code is a wrong one.
always @(posedge clk or posedge rst)

Avoid clock buffers or any other logic

If any signal crosses multiple clock domains having different clock frequencies then those signals
must be properly synchronised with synchronous logic. Synthesis tools cant optimize any timing
paths between asynchronous clock domains.

1.2.12. Reset logic guidelines

Synchronous Reset:
Advantages:
Easy to synthesize, just another synchronous input to the design.
Disadvantages:
Require a free running clock. At power-up clock is must for reset.
Asynchronous Reset:
Advantages:
 Doesnt require a free running clock.
Uses separate input on flip flop, so it doesnt affect flop data timing.
Disadvantages:
Harder to implement. Considered as high fanout net
STA, simulation, DFT becomes difficult

1.2.13. Registered outputs

All outputs should be registered and combinational logic should be either at the input section or in
between two registered stages of a module.

1.2.14. Incomplete sensitivity list

Sensitive list should contain all inputs. If inputs are missed in the sensitivity list, then the changes
of that inputs will not be recognised by simulator. Synthesised logic in most cases may correct for
the blocks containing incomplete sensitivity list. But this may cause simulation mismatches
between source RTL and synthesised netlist. Generally synthesis tools issue a warning for the
always block having incomplete sensitivity list. Registers can also be added in the sensitive list.

1.2.15. Avoid latch inference

if-else statements must be end with else statements. Else unintentional latches will be realized
(at output) due to the missing else statement at the end.
Same is true for case statement. default statement must be added.
Work Around:
Either include all possible combination of inputs or initialise the value before the loop starts.
Eg.:
if(z)a=b;

Above code will infer a latch. Because if z=1, value of a is defined. But if z=0 value of a is not
specified. Hence it is assumed that previous value has to be retained and hence latch is infered.
Eg.:
modulelatch_inf_test(a,x,y,t,out);

input[2:0]a;

inputx,y,t;

outputout;regout;

always@(aorxoryort)

begin

case(a)

3b001:out=x;
3b010:out=y;

3b100:out=t;

endcase

end

endmodule

Eg.:

modulecase_latch(dout,sel,a,b,c);

input[1:0]sel;

inputa,b,c;

outputdout;

regdout;

always@(aorborcorsel)

begin

case(sel)

2'b00:dout=a;

2'b01:dout=b;

2'b10:dout=c;

endcase

end

endmodule

(Above code and figure are Courtesy of Cadence Manuals)

Preventing a Latch by Assigning a Default Value

modulecase_default(dout,sel,a,b,c);

input[1:0]sel;

inputa,b,c;

outputdout;

regdout;

always@(aorborcorsel)
 begin

case(sel)

2'b00:dout=a;

2'b01:dout=b;

2'b10:dout=c;

default:dout=1'b0;

endcase end endmodule

(AbovecodeandfigurearecourtesyofCadenceManuals)

1.2.16. Use Constants

Use constants instead of hard coded numeric values.

Below coding style is not recommended:

wire[15:0]input_bus;

reg[15:0]outputbus;

Recommended coding style:

defineINPUT_BUS_WIDTH16

defineOUTPUT_BUS_WIDTH16

wire[INPUT_BUS_WIDTH1:0]input_bus;

reg[OUTPUT_BUS_WIDTH1:0]output_bus;

Keep constants and parameters definitions in separate file with naming convention such as design_name.constants.v and
design_name.parameters.v

1.2.17. General Coding guidelines for ASIC synthesis

Inference of the logic should be given higher priority compared to instantiation of the
logic.
File name and module name should be same.
A file should have only one module.
Use lowercase letters for ports, variables and signal names.
 Use uppercase for constants, user defined types.

Synchronous Reset:
Advantages:

Easy to synthesize, just another synchronous input to the design.

Disadvantages:

Require a free running clock. At power-up clock is must for reset.

Asynchronous Reset:
Advantages:

Doesnt require a free running clock.

Uses separate input on flip flop, so it doesnt affect flop data timing.

Disadvantages:

Harder to implement. Considered as high fanout net

STA, simulation, DFT becomes difficult

Clock logic guidelines

 Dont use mixed clock edges

mixing of edge sensitive and level sensitive lists are not allowed. Below code is a wrong one.

always @(posedge clk or posedge rst)

Avoid clock buffers or any other logic

If any signal crosses multiple clock domains having different clock frequencies then those signals must be properly
synchronised with synchronous logic. Synthesis tools cant optimize any timing paths between asynchronous clock
domains.

ASIC SYNTHESIS
14.4. Environmental constraints
14.3. Timing Constraints
These constraints specify clock related definitions which affect synthesis and timing analysis.
14.2 Optimization constraints

14.1. Logical DRC constraints

Operating conditions
 This section models the environmental variations of IC. These are known as Process, Voltage, and temperature variations. In short it is
called PVT.

A set of values of PVT is known as operating condition. A logic library is characterised for one set of operating condition. Generally there
are different libraries specific to different operating condition. There are three operating conditions very commonly used in ASIC
synthesis and implementation. Based on the affect on cell delay due to the variation in PVT these classifications are made.
They are:
worst (also called max or slow) library in which cells are characterised for maximum delay
best(also called min or fast) library in which cells are characterised for minimum delay
nominal(also called typical or normal) library in which cells are characterised for typical delay
Sources of variation in performance of a chip are due to:
Process variation (P)
This variation accounts for deviations in the semiconductor fabrication process. Usually process variation is
treated as a percentage
variation in the performance calculation. Variations in the process parameters can be impurity concentration
densities, oxide thicknesses
and diffusion depths. These are caused bye non uniform conditions during depositions and/or during diffusions of
the impurities. This
introduces variations in the sheet resistance and transistor parameters such as threshold voltage. Variations are
in the dimensions of the
devices, mainly resulting from the limited resolution of the photolithographic process. This causes (W/L)
variations in MOS transistors.

Supply voltage (V) Operating Temperature (T)

The power consumption is mainly due to switching, short-circuit and leakage power consumption. The short-circuit
power dissipation is due to the finite rise and fall times. The nMOS and pMOS transistors may conduct for a short time during
switching, forming a direct current from the power supply to the ground. The leakage power consumption is due to the nonzero
reverse leakage and sub-threshold currents. The biggest contribution to the power consumption is the switching.
The threshold voltage of a transistor depends on the temperature. A higher temperature will decrease the threshold voltage. A
lower threshold voltage means a higher current and therefore a better delay performance.

The best and worst design corners are defined as follows:

Best case: fast process, highest voltage and lowest temperature
Worst case: slow process, lowest voltage and highest temperature
 Technology libraries :.lib

Technology library is a collection gates along with characteristics information of it. Technology libraries are
provided by fabrication house (such as TSMC, UMC etc.) based on technology of manufacturing. Thus
technology libraries contain information about the characteristics and functions of each logic cell provided in
a semiconductor vendors library. Technology libraries are distributed and maintained by semiconductor
vendors (i.e. fabrication houses).
Inputs and output from ASIC synthesis flow
Outcome of Synthesis is Gate level netlist which is again in Standard Verilog format. Netlists can be simulated as well which
we call as Gate Level Simulation.

6.2.1. Register Transfer Level (RTL) Representation

RTL is the functional specification of the design to logic synthsis which is represented by HDLs.
Register: Storage element like F-F, latches
Transfer: Transfer data between input, output and register using combinational logic.
Level: Level of Abstraction modeled using HDL.
6.2.2. Constraints
The major objective of the logic synthesis is to meet the optimization constraints specified by the designer. Timing, area and
power targets are the optimization constraints.
Timing Constraints: The synthesis tool tries to meet the setup and hold timing constraints on the sequential logic in the design.
Area constraints: Area constraints specifies maximum area for a design.
Power Constraints: Power constraints specifies the maximum power consumption for the design.

6.2.3. Target Library

Target library is standard cell library corresponding to a particular technology node (eg. 45nm). This is a collection of combinational
logic gates and sequential logic elements which are used to convert HDL to gate level netlist.
If logic synthesis is carried ou for FPGAs then HDL description is translated and mapped to LUTs, flip-flops and block RAMs. For
FPGA implementation separate synthesis tool is required. ASIC synthesis tool cant synthesize the HDL into FPGA omplemtable netlist.

A clean technology independent HDL description of design can be synthesized to any technology node. This can also be targeted for
FPGA implementations.

ASIC Synthesis: Synthesis definition, goals

1. ASIC Synthesis

6.1. Synthesis definition, goals

Synthesis is the process of transforming your HDL design into a gate-level netlist, given all the specified constraints and optimization
settings.
Logic synthesis is the process of translating and mapping RTL code written in HDL (such as Verilog or VHDL ) into technology specific
gate level representation.

There are 3 steps in Synthesis:

Translation: RTL code is translated to technolohgy independent representation. The converted logic is available in boolean
equation form.
Optimization: Boolean equation is optimized using SoP or PoS optimization methods.
Technology mapping: Technology independent boolean logic equations are mapped to technology dependant library logic gates
based on design constraints, library of available technology gates. This produces optimized gate level representation which is
generally represented in Verilog.
Then the gate level circuit generated is logically optimized to meet the targets or goals set as per the user constraints. The clock frequency
target is the number one goal that has to be met by the synthesis operation.**** check TOM figure