6.

012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 7-1

Lecture 7 - PN Junction and MOS

Electrostatics (IV)

Electrostatics of
Metal-Oxide-Semiconductor Structure

February 27, 2003

Contents:

1. Introduction to MOS structure

2. Electrostatics of MOS at zero bias
3. Electrostatics of MOS under bias

Reading assignment:

Howe and Sodini, Ch. 3, 3.7-3.8

6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 7-2

Key questions

What is the big deal about the metal-oxide-semiconductor

structure?
What do the electrostatics of the MOS structure look
like at zero bias?
How do the electrostatics of the MOS structure get
modified if a voltage is applied across its terminals?
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 7-3

1. Introduction

Metal-Oxide-Semiconductor structure:

metal
interconnect to gate

gate oxide
ox = 3.9 o n+ polysilicon gate

p-type x
s = 11.7 o

metal interconnect to bulk

MOS at the heart of the electronics revolution:

Digital and analog functions: Metal-Oxide-Semiconductor
Field-Effect Transistor (MOSFET) is key element of
Complementary Metal-Oxide-Semiconductor (CMOS)
circuit family
Memory function: Dynamic Random Access Mem-
ory (DRAM) and Flash Erasable Programmable Mem-
ory (EPROM)
Imaging: Charge-Couple Device (CCD) camera
Displays: Active-Matrix Liquid-Crystal Displays
...
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 7-4

2. MOS electrostatics at zero bias

Idealized 1D structure:

"metal"
(n+ polySi)

semiconductor
oxide (p type)
contact contact

-tox 0 x

Metal: does not tolerate volume charge charge can

only exist at its surface
Oxide: insulator no volume charge (no free carriers,
no dopants)
Semiconductor: can have volume charge (SCR)

Thermal equilibrium cant be established through oxide;

need wire to allow transfer of charge between metal and
semiconductor.

MOS structure: sandwich of dissimilar materials car-

rier transfer space-charge region at zero bias built-in
potential
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 7-5

For most metals on p-Si, equilibrium achieved by elec-

trons diffusing from metal to semiconductor and holes
from semiconductor to metal:

log po, no
Na
po

no
ni2
Na
-tox 0 xdo x

Remember: nopo = n2i

Fewer holes near Si/SiO2 interface ionized acceptors

exposed (volume space charge)
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 7-6

2 Space charge density

log po, no
Na
po

no
ni2
Na
-tox 0 xdo x

QG

0 0 xdo
-tox x

-qNa

In semiconductor: space-charge region close to Si/SiO2

interface can do depletion approximation
In metal: sheet of charge at metal/SiO2 interface
Overall charge neutrality

x tox o(x) = QG (tox)

tox < x<0 o(x) = 0
0 < x < xdo o(x) = qNa
xdo < x o(x) = 0
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 7-7

2 Electric field

Integrate Gauss equation:

1 Z x2
Eo(x2) Eo(x1) = x1 o(x)dx


At interface between oxide and semiconductor:

change in permittivity change in electric field

oxEox = sEs

Eox s
= '3
Es ox

Eox

Es

0
0 x
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 7-8

Start integrating from deep inside semiconductor:

0 0 xdo
-tox x

-qNa

E
Eox

Es
0
-tox 0 xdo x

xdo < x Eo(x) = 0

qNa
0 < x < xdo Eo(x) = (x xdo)
s
s + qNaxdo
tox < x < 0 Eo(x) = Eo(x = 0 ) =
ox ox

x < tox Eo(x) = 0

6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 7-9

2 Electrostatic potential
(with = 0 @ no = po = ni)

kT no kT po
= ln = ln
q ni q ni

In QNRs, no and po known can determine :

in n+ gate: no = Nd+ g = n+

in p-QNR: po = Na p = kT
q
ln Nnia

n+

B
0
-tox 0 xdo x
p

Built-in potential:

kT Na
B = g p = n+ + ln
q ni
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 7-10

To get o(x), integrate Eo(x); start from deep inside semi-

conductor bulk:
Z
x2
o(x2) o(x1) = x1 Eo(x)dx
E

Eox

Es
0
-tox 0 xdo x

n+

Vox,o
B 0 xdo
0 x
-tox
VB,o
p

xdo < x o(x) = p

qNa
0 < x < xd o(x) = p + (x xdo)2
2s
qNax2do qNaxdo
tox < x < 0 o(x) = p + + (x)
2s ox

x < tox o(x) = n+

6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 7-11

2 Still dont know xdo need one more equation:

Potential difference across structure has to add up to B :

qNax2do qNaxdotox
B = VB,o + Vox,o = +
2s ox

Solve quadratic equation:

v v
u u
s u
u
u 22oxB s u
u
u 4B
xdo = tox[ 1 +
u
t 1] = u
t[ 1 + 2 1]
ox sqNat2ox Cox

where Cox is capacitance per unit area of oxide [units:

F/cm2]:

ox
Cox =
tox

and is body factor coefficient [units: V 1/2]:

1 r
= 2sqNa
Cox
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 7-12

2 Numerical example:

Nd = 1020 cm3, Na = 1017 cm3, tox = 8 nm

B = 550 mV + 420 mV = 970 mV

Cox = 4.3 107 F/cm2

= 0.43 V 1/2

xdo = 91 nm
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 7-13

There are also contact potentials

total contact-to-contact potential difference is zero!

"metal"
semiconductor
contact oxide contact
(p type)

n+

B
0 0
x
-tox xdo
p
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 7-14

3. MOS electrostatics under bias

Apply voltage to gate with respect to semiconductor:

VGB

"metal"
(n+ polySi)

semiconductor
oxide (p type)
contact contact

-tox 0 x

Electrostatics of MOS structure affected potential dif-

ference across entire structure now 6= 0.

How is potential difference accommodated?

Potential can drop in:

gate contact
n+-polysilicon gate
oxide
semiconductor SCR
semiconductor QNR
semiconductor contact
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 7-15

Potential difference shows up across oxide and SCR in

semiconductor:

VGB B+VGB
? B
0 -tox 0 xdo
x

Oxide is insulator no current anywhere in structure

In SCR, quasi-equilibrium situation prevails

new balance between drift and diffusion

electrostatics qualitatively identical to zero bias (but

amount of charge redistribution is different)
np = n2i
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 7-16

Apply VGB > 0: potential difference across structure in-

creases need larger charge dipole SCR expands into
semiconductor substrate:

xd
0
-tox 0 x

-qNa

Eox

Es

0
-tox 0 xd x

VGB=0

VGB>0

B+VGB
B
0
-tox xd x
0

log p, n
Na

n
ni2
Na
-tox 0 xd x

Simple way to remember:

with VGB > 0, gate attracts electrons and repels holes.
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 7-17

Qualitatively, physics unchanged by applying VGB > 0.

Use mathematical formulation of zero bias, but:

B B + VGB

For example,
v
u
u
s 4(B + VGB )
u
u
xd(VGB ) = [ 1+ u
t 1]
Cox 2

VGB xd
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 7-18

Key conclusions

Charge redistribution in MOS structure at zero bias:

SCR in semiconductor
built-in potential across MOS structure.
In most cases, can do depletion approximation in semi-
conductor SCR.
Application of voltage modulates depletion region width
in semiconductor. No current flows.