Volume 2, Issue 3, March 2017 International Journal of Innovative Science and Research Technology

ISSN No: - 2456- 2165

Implementation of High Speed Vedic Multiplier

M.Durga Madhuri1, G.Sweta Sree2,D.Raghunadh3,G.Panduranga Vittal4, Ch.Surya Narayana5
Department of Electronics and Communication
Lendi Institute of Engineering and Technology, Denkada mandal,
Vizianagaram, India.

Abstract:- Today processor needs high speed multipliers. the learners in a wide area of problems, ensuring both speed
Multipliers are the essential block to process functions in and accuracy, strictly based on rational and logical reasoning.
high speed arithmetic logic units, multiplier and 1. Anurupye Shunyamanyat-(If one is in ratio, the other is
accumulate units, digital signal processing units etc. To Zero)
enhance speed many modifications over the standard 2. Chalana-Kalanabyham( Differences and Similarities)
modified booth algorithm, Wallace tree methods for 3. Ekadhikina Purvena( By one more than the previous one)
multiplier design have been made and several new 4. Ekanyunena Purvena( By one less than the previous one)
techniques are being worked upon. With the increasing 5. Gunakasamuchyah (The factors of the sum is equal to the
constraints on delay, more and more emphasis is being laid sum of the factors)
on design of faster multiplications. Among these Vedic 6. Gunitasamuchyah (The product of the sum is equal to the
multipliers based on Vedic mathematics are presently sum of the product)
focused due to these being one of the fastest and low power 7. Nikhilam Navatashcaramam Dashatah( All from 9 and the
multiplier. Out of sixteen sutras in Vedic mathematics of last from 10)
multiplication Urdhva Tiryagbhyam has been selected 8. Paraavartya Yojayet( Transpose and adjust)
as a most efficient one in terms of speed. A large number 9. Puranapuranabyham( By the completion or non
of high speed Vedic multipliers have been proposed with completion).
Urdhva Tiryagbhyam sutra. Few of them are presented in 10. Sankalana-vyavakalanabhyam (By addition and by
this paper giving an insight into their methodology, merits Subtraction)
and demerits. Carry save adder, Ripple carry adder based 11. Shesanyankena Charamena( The remainders by the last
Vedic Multipliers show considerable improvements in Digit)
speed and area efficiency over the conventional ones. 12. Shunyam Saamyasamuccaye (When the sum is the same
that sum is zero)
Keywords: Vedic mathematics, Urdhva 13. Sopaantyadvayamantyam (The ultimate and twice the
Penultimate)
Tiryagbhyam, carry save adder, ripple carry adder. 14. Urdhva Tiryagbyham( Vertically and crosswise.)
15. Vyashtisamanstih( Part and Whole)
I. INTRODUCTION 16. Yaavadunam( Whatever the extent to fits deficiency).

The Sanskrit word Veda is derived from the root Vid, meaning A. Brauns Multiplier
to know Without limit. The word Veda covers all Veda-sakhas
known to humanity. Swami Bharati Krishna Tirtha (1884- Brauns multiplier[3] is an n m bit parallel multiplier and
1960)[1], former Jagadguru Sankaracharya of Puri culled a set generally known as carry save multiplier and is constructed
of 16 Sutras (aphorisms) and 13 Sub-Sutras (corollaries) from with m (n-1) address and m n AND gates. The Brauns
the Atharva Veda. He developed methods and techniques for multiplier has a glitching problem which is due to the ripple
amplifying the principles contained in the aphorisms and their carry adder in the last stage of the multiplier. Vedic multipliers
corollaries, and called it Vedic Mathematics. Vedic show the considerable improvements in speed and area
Mathematics offers a new and entirely different approach to efficiency over the BRAUN MULTIPLIERS.
the study of Mathematics based on pattern recognition. Vedic
Mathematics designs used in many applications like ALU, B. UT Sutra
MAC etc.
The proposed Vedic multiplier depends on the "Urdhva
II. VEDIC MATHEMATICS SUTRAS Tiryagbhyam" sutra. These Sutras have been customarily
utilized for the increase of two numbers in the decimal number
These 16 Sutras apply to and cover almost every branch of framework. It is a general increase equation relevant to all
Mathematics[2]. They apply even to complex problems instances of augmentation. It actually signifies "Vertically and
involving a large number of mathematical operations. Crosswise". It makes all the numeric calculations quicker and
Application of the Sutras improves the computational skills of less demanding. The benefit of multiplier in view of this sutra
over the others is that with the expansion in number of bits,

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Volume 2, Issue 3, March 2017 International Journal of Innovative Science and Research Technology
ISSN No: - 2456- 2165
range and postpone increment at a littler rate in contrast with
others.
Urdhva Tiryagbhyam is the general equation material to all
instances of augmentation and furthermore in the division of a
substantial number by another expansive number.

Fig.3. 4X4 vedic multiplication block diagram

Another strategy for the estimation of Urdhva Tiryakbhyam

technique is appeared in Figure 2. In this method, the numbers
to be duplicated given us a chance to state 5498 and 2314 are
composed on the sequential sides of the square table. On
Fig 1. Block diagram of 4-Bit vedic multiplier apportioning the square into lines and segments, each
line/segment has a place with one of the digit of the two
The multiplication of two decimal numbers 325 and 738. The numbers to be increased to such an extent that each digit of
numbers of steps in the process depend upon the number of one number has a little square normal to the digit of other
the digits being used. Digits on the two ends of the lines are number. These little squares are further partitioned into two
multiplied and resultant is added to the carry from previous equivalent amounts of by transversely lines. Presently the
step. When the number of crossing lines in a single step is every digit of one number is duplicated with each digit of
greater than one then they all are added along with the second number and two digit items are set in their relating
previous carry. After this, only the least significant digit of the square. The digits on transversely line are included with past
resulting number is taken as product digit and rest are convey. Digits on dabbed noteworthy digit of the subsequent
considered as carry digits. Initial carry is taken as zero.[4] number are taken as item digit and rest are considered as
convey digits. Introductory convey is thought to be zero here
moreover. [2] The technique can be reached out for parallel
numbers. A basic 1-digit twofold increase is portrayed by
AND entryway operation. Utilizing this and UT technique
2X2 duplication for a1a0 and b1b0 is executed by 2 half
adders and resultant bits are r2 (2 bits) r1r0 as shown in Fig. 4.
The equations regarding this are given below. [5]

r0 (1bit) = a0b0 .....(1)

r1 (1bit) =a0b1 +a1b0 .....(2)
r2 (2bit) = b1a1 +c1 .....(3)
Product = r2&r1&r0 .....(4)

Higher double augmentations can likewise be acquired with

the assistance of lower increase units and the snake unit. The
individual increase items are acquired by same partitioning
technique, at last utilizing the 2X2 piece duplication strategy.
For NXN increase unit, we require four N/2 bit multipliers,
two N bit full adders, one half adder and N/2 bit full adder to
include the aggregate and carry of half adder appeared. Fast of
multiplier depends endless supply units utilized.

Fig 2. Decimal number multiplication using UT sutra

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Volume 2, Issue 3, March 2017 International Journal of Innovative Science and Research Technology
ISSN No: - 2456- 2165
essential and one carry info and produces SUM and CARRY
yield. In carry save adder, one piece full adder circuits are
organized in course. Carry yield of the each full adder capacity
is associated as carry contribution of one twofold piece higher
full adders. Bit a0, b0 s to the slightest critical bits to be
included and c0 speak to the carry input flag. In these adders,
the primary goal is to create last carry and to obtain with better
speed and lower control utilization[6].

Fig 4. Alternate way to calculate UT sutra

III. 2X2 VEDIC MULTIPLIER

Fig 6. Ripple carry adder
The 2X2 Vedic multiplier module is implemented using four
input AND gates & two half-adders which is in its block In ripple carry adder, one bit full adder circuits are arranged in
diagram. It is found that the hardware architecture of 2x2 bit cascade. Carry output of the every full adder function is
Vedic multiplier is same as the hardware architecture of 2x2 connected as carry input of one binary bit higher full adder .
bit conventional Array Multiplier .Hence it is concluded that Bit a0, b0 represent the least significant bits to be added and
multiplication of 2 bit binary numbers by Vedic method does c0 represent the carry input signal. In these adders, the main
not made significant effect in improvement of the multipliers objective is to produce final carry and sum output with better
efficiency. speed and lower power consumption.

Fig 5. 2X2 Vedic multiplier

VI. 4x4 BIT VEDIC MULTIPLICATION USING RIPPLE

CARRY ADDER

A RCA is a coherent circuit in which the complete of each

full adder is given as the carry contribution to the following
sequence full adder. It is purported in light of the fact that it
gets undulated to the following stage. Adders are the primary
squares to finish a multiplier outline. The Ripple Carry Adder
(RCA) has the littlest area when compared with alternate
adders. So it is restricted to applications where the range must
be limited. The ripple carry adder is one of the least complex Fig7. Block diagram for 4X4 vedic multiplier using ripple
adders. The ripple carry adder is built by combining full carry adder
adders (FA) obstructs in arrangement. One full adder is in
charge of the expansion of two paired digits at any phase of
the carry. A carry save circuit actualizes the expansion of two

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Volume 2, Issue 3, March 2017 International Journal of Innovative Science and Research Technology
ISSN No: - 2456- 2165
V. MULTIPLICATION USING CARRY SAVE ADDER VI. CONCLUSION

A ripple carry adder is a kind of computerized adder, utilized Vedic Multiplier supposedly is productive in speed, control
as a part of PC miniaturized scale engineering to figure the and zone in computerized plans as for different multipliers.
aggregate of at least three n-bit numbers in twofold. It varies Considering every one of the plans of it examined above, we
from other computerized adders in that it yields two quantities can say that the Carry save adder based Vedic multiplier with
of an indistinguishable measurements from the information Urdhva Tiryakbhyam sutra is viewed as a promising technique
sources, one which is an arrangement of halfway entirety bits in terms of speed and area. The work can be further extend
and another which is a succession of bits. The carry save adder with the compressor based vedic multiplier and utilization of
is utilized to include at least three N bit operands by creating such multiplier in arithmetic logical unit, increase in
the yield of two N bit numbers in two sequences. One is accumulator unit designs and comparing at the outcomes with
having the N bit partial addition results comes about and existing same designs.
another is having the arrangement of carry bits. At that point a
ripple carry adder, for the most part Ripple carry adder is REFERENCES
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Fig8. Carry save adder
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Fig 9. Block diagram for 4X4 vedic multiplier using carry

save adder.

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