IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 32, NO.

3, MARCH 2013 479

Short Paper
A Method to Construct Low Delay Single Error while more sophisticated codes are used in critical applications
Correction Codes for Protecting such as space [3]. The main reason for this is that SEC codes
Data Bits Only can be encoded or decoded with simple circuitry and require a
low number of redundant bits. SEC codes can correct a single
Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, and bit error per block. For memory protection, SEC codes are
Marco Ottavi commonly extended to also detect double errors. In this case,
the codes are known as SEC double error detection (SEC-
AbstractError correction codes (ECCs) have been used for decades
DED) codes [4].
to protect memories from soft errors. Single error correction (SEC) codes A classical type of SEC codes is Hamming codes that can
that can correct 1-bit error per word are a common option for memory be constructed in a simple way [5]. Hamming codes can also
protection. In some cases, SEC codes are extended to also provide double
error detection and are known as SEC-DED codes. As technology scales,
be extended with a parity bit to obtain a SEC-DED code. More
soft errors on registers also became a concern and, therefore, SEC codes sophisticated SEC-DED codes have also been proposed as, for
are used to protect registers. The use of an ECC impacts the circuit example, the ones described in [4], [6], and [7]. In those cases,
design in terms of both delay and area. Traditional SEC or SEC-DED
codes developed for memories have focused on minimizing the number of
the number of redundant bits is kept to the lowest achievable
redundant bits added by the code. This is important in a memory as those value, and the different codes optimize the area and delay
bits are added to each word in the memory. However, for registers used of the encoder and decoder or the detection of triple errors.
in circuits, minimizing the delay or area introduced by the ECC can be
more important. In this paper, a method to construct low delay SEC or
This is a reasonable approach for memories as the number of
SEC-DED codes that correct errors only on the data bits is proposed. The redundant bits has a direct impact on memory size.
method is evaluated for several data block sizes, showing that the new As technology scales, soft errors also become an issue for
codes offer significant delay reductions when compared with traditional
SEC or SEC-DED codes. The results for the area of the encoder and
registers used in digital circuits. SEC codes can also be used
decoder also show substantial savings compared to existing codes. to protect those registers that may store, for example, the state
Index TermsDouble error detection, error correction codes (ECCs),
of a finite state machine or data-path values in an arithmetic
single error correction (SEC), soft errors. circuit. In those cases, the design constraints for the SEC
code are different than in memories. For example, in circuits
minimizing the encoding and decoding delay may be the most
I. Introduction critical aspect. The impact on area is also different, as the
redundant bits are only added to the register being protected
Soft errors are an important issue for electronic circuits, and
such that their cost can be lower than that of the encoding
many different techniques are used to mitigate their effects
and decoding circuitry. In memories, since the redundant
[1]. To protect memories, error correction codes (ECCs) are
bits are added to each word, their overall cost commonly
widely used [2]. ECCs have an impact on circuit delay, area,
has the largest impact on area. Another difference is that
and power consumption. The delay is added as data has to
in memories it can be useful to correct errors on the parity
be encoded when writing into the memory and decoded when
bits when decoding. This is the case, for example, when
reading from it. The impact on area and power comes from the
scrubbing is used to periodically remove errors to prevent
encoding and decoding circuitry and also from the redundant
their accumulation [8]. In registers, the correction of parity
bits that the ECC adds to each data block. For memories, the
bits has little interest as the register contents are in many cases
number of redundant bits is typically the most critical factor
updated frequently and the input data comes from other circuit
as those bits are added to each memory word. This means that
elements. In spite of these differences, the SEC or SEC-DED
the impact on area scales with memory size.
codes that have been used or designed to protect memories
Single error correction (SEC) codes are the ones most
are also used in registers. This clearly suggests the interest of
commonly used to protect standard memories and circuits [2],
designing SEC codes that are targeted to the needs of registers.
Manuscript received June 29, 2012; revised September 7, 2012; accepted In this paper, a method to construct SEC and SEC-DED
October 19, 2012. Date of current version February 14, 2013. This work was codes that have low encoding and decoding delay is proposed.
supported in part by the Spanish Ministry of Science and Education under
Grant AYA2009-13300-C03. The work of M. Ottavi was funded by the Italian The proposed scheme can be used to design codes for any data
Ministry for University and Research, Program Incentivazione alla mobilit block size using a simple script. To illustrate the benefits of
di studiosi stranieri e italiani residenti allestero, D.M. 96, 23.04.2001. This the method, the derived SEC codes are compared to Hamming
paper is part of a collaboration in the framework of COST ICT Action 1103
Manufacturable and Dependable Multicore Architectures at Nanoscale. This SEC codes and the proposed SEC-DED codes with the opti-
paper was recommended by Associate Editor J. Cortadella. mized SEC-DED codes presented in [6]. The results show that
P. Reviriego and J. A. Maestro are with the Universidad Antonio de Nebrija, they achieve a significantly lower delay and also a lower area
Madrid 28040, Spain (e-mail: [email protected]; [email protected]).
S. Pontarelli and M. Ottavi are with the University of Rome for the encoder and the decoder. The proposed codes require,
Tor Vergata, Rome 00133, Italy (e-mail: [email protected]; in most cases, more redundant bits than traditional codes. This
[email protected]). limits their applications to large memories, but is not an issue
Digital Object Identifier 10.1109/TCAD.2012.2226585
for registers where the area of the encoder and decoder can be
0278-0070/$31.00 
c 2013 IEEE
480 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 32, NO. 3, MARCH 2013

larger than that of the register itself. Therefore, the proposed

method can be used to design SEC or SEC-DED codes that
are tailored for the protection of registers in circuits. Another
application of the proposed codes is the protection of high-
speed memories or caches in which speed is more important
than area.
The rest of this paper is organized as follows. Section II
describes single error correction codes analyzing, in detail, the
encoder and decoder. In Section III, the proposed method to
construct low delay SEC and SEC-DED codes is presented. In
Section IV, the derived codes are evaluated in terms of area and Fig. 1. Encoder for the SEC Hamming code with k = 8.
delay and compared with existing codes. Finally, conclusions
of this paper and some ideas for future work are summarized
in Section V.

II. Single Error Correction Codes

A linear block code takes k data bits and produces an n-bit
block [9]. In many applications, systematic codes that preserve
the original k data bits and simply add n-k parity bits are
preferred. A given linear block code can be described by its
generator matrix G. Given a block of k data bits, the n bits
codeword is obtained by multiplying the data block by the
generator matrix. As an example, the generator matrix for an
SEC Hamming code for k = 8 and n = 12 is shown in (1). The
last four columns define the added parity bits. The generator
matrix is used to encode the data block

1 0 0 0 0 0 0 0 1 1 0 0
0 1 0 0 0 0 0 0 1 0 1 0

0 0 1 0 0 0 0 0 0 1 1 0

0 0 0 1 0 0 0 0 1 1 1 0
G= . (1)

0 0 0 0 1 0 0 0 1 0 0 1
0 0 0 0 0 1 0 0 0 1 0 1 Fig. 2. Structure of the decoder for the SEC Hamming code with k = 8.

0 0 0 0 0 0 1 0 1 1 0 1
0 0 0 0 0 0 0 1 0 0 1 1 obtained syndrome must be checked against every column in
H and if there is a match; that is the bit in error that is then
To decode a codeword, the parity check matrix H is used. corrected. Each of those checks requires an n k input AND
This matrix when multiplied by a codeword will be an all gate. The encoder for the Hamming code used as an example
zero vector if there are no errors. If there is an error, the value is illustrated in Fig. 1. The data bits (di ) are the inputs and
of that vector, usually called syndrome, will serve to detect the parity check bits (ci ) the outputs.
the error and correct it. The H matrix for the SEC Hamming The structure of the decoder is shown in Fig. 2. In this
code previously considered is shown in (2). It can be observed case, the data bits (di ) and the parity check bits (ci ) are the
that all columns in the matrix are different. This means that inputs, and the outputs are the corrected data bits (dic ). It can
any single-bit error will produce a different syndrome, and be observed that the complexity and delay is larger in the case
therefore the error can be corrected of the decoder as it is normally the case for most ECCs.
The number of parity bits required by a Hamming code
1 1 0 1 1 0 1 0 1 0 0 0
1 0 1 1 0 1 1 0 0 1 0 0 grows logarithmically with the data block size, and the values
H = 0 1 1 1 0 0 0 1 0 0 1 0 . (2)
for common block sizes are shown in Table I. These values
are the same for other SEC codes, and as discussed before are
0 0 0 0 1 1 1 1 0 0 0 1
an important parameter when the codes are used in memories.
The structure of the encoder and decoder can be explained SEC-DED codes are similar to SEC codes and can be
using the G and H matrixes. Encoding is simply computing obtained by using a parity check matrix H with an odd number
the multiplication of the input data block by the G matrix. of ones (odd weight) in all its columns [4]. This reduces the
This requires a number of XOR gates for each column in G number of combinations that can be used in the columns, and
that is proportional to the number of ones in that column. therefore increases the number of additional bits required. This
Decoding starts by multiplying the H matrix by the codeword. can be observed in Table I, where the parity check bits for
This requires a number of XOR gates for each row in H that traditional SEC-DED codes are illustrated. The encoding and
is proportional to the number of ones in that row. Then, the decoding is similar to that of SEC codes with the addition of
REVIRIEGO et al.: METHOD TO CONSTRUCT LOW DELAY SEC CODES 481

TABLE I the bit affected by the error. This condition is satisfied if no

Number of Parity Check Bits in Existing SEC column of H includes all the ones present in another column.
and SEC-DED Codes For data bits, this can be achieved for example, if all the
data bits have the same number of ones w in their column of
k SEC (Hamming) SEC-DED [4], [6] the H matrix. Then, as the columns are different, no column
8 4 5 can include all the ones in another column as that would imply
16 5 6
that the two columns are equal. To minimize the number of
32 6 7
64 7 8 ones, the value w = 2 can be used to obtain SEC codes. It is
also interesting to analyze the case w = 3 as in that case the
TABLE II code is SEC-DED.
Number of One Elements in the H Matrix for Different Codes Since for the parity bits the columns have only a one, the
condition is not met as other columns have a one in that bit.
k Hamming Proposed Hsiao [7] Proposed Therefore, this modification cannot correct errors in the parity
SEC SEC SEC-DED SEC-DED SEC-DED bits. This is not an issue for registers as the correction of
8 22 21 29 27 29
parity bits is not normally needed as discussed before. The
16 43 39 54 52 54
32 87 73 103 104 103
decoder modification combined with a low number of ones in
64 186 140 216 216 201 the columns of the H matrix results in an additional reduction
of the decoding delay.
The method to construct the code starts by finding the
some logic to detect double errors. This logic simply performs
smallest value of n k for which the following is true:
the OR of the n k syndrome bits and also the XOR of those 
bits. A double error is detected when the OR takes a value of nk
k. (3)
one (at least one syndrome bit is different from zero, therefore w
there are errors) and the XOR a value of zero (an even number For w = 2, this value can be found analytically by solving
of syndrome bits are different from zero, i.e., more than one (3) that is a quadratic equation in n. As the value of n has to
error has occurred). be larger than k, only one of the two possible solutions of the
The number of ones in the parity check matrix is related equation is valid in our case. The value of n k obtained is
to the number of XOR gates needed to generate and check the

parity check bits. Therefore, it can be used as a first estimate 1 + 8k + 1
nk (4)
of the complexity of the encoders and decoders [6]. The values 2
for the different codes and block sizes are provided in Table
II. The proposed SEC and proposed SEC-DED are the values that shows a growth of the number of parity bits with the
for the codes that will be presented in the remainder of this square root of k that is larger than the logarithmic growth of
paper. It can be observed that SEC codes have less ones than Hamming codes. This means that as k increases, the overhead
SEC-DED codes as they are simpler. For the Hamming codes, of the proposed codes in terms of the number of additional
columns have been reordered to ensure that the ones with the parity bits compared to Hamming will also increase.
lowest weights are used for the data bits. The SEC-DED codes Similarly, for w = 3, the solution to (3) is given by
with the lowest number of ones are those presented in [6], and  1/3
therefore they will be used as the reference for comparison in 243k2 1 1
nk 3/2
+ 3k +  1/3 + 1
the following. It is important to note that for the decoder, the 3 243k2 1
number of ones gives only a rough idea of the complexity as 3 + 3k
33/2
the logic to identify the syndrome values that is independent (5)
of the number of ones is the most complex block. that, as k is larger than one, can be approximated by

III. Construction of Low Delay Single-Error n k (6k)1/3 + 1. (6)

Correction Codes The growth of the number of parity check bits with k is
The proposed method to construct SEC and SEC-DED smaller than for w = 2, but is still larger than the logarithmic
codes tries to minimize the number of ones in each row and in growth of traditional SEC-DED codes.
each column of the H matrix. Reducing the number of ones in In the second step to constructing the codes, a different
the rows lowers the delay when computing the parity bits in combination of w of the n k added bits is used for each of
the encoder and also when recomputing the parity checks in the first k columns of the H matrix. Equation (3) guarantees
the decoder. Reducing the number of ones in the columns of that there are sufficient different combinations. The remaining
the H matrix does not lower the delay by itself. To achieve a n k columns form an identity matrix of size n k. An H
reduction in the delay, the final phase of decoding is modified. matrix constructed using this procedure for w = 2 and k = 8
This is done by checking only for the bits that are one in each is shown in (7). Compared with the matrix in (2), it can be
column to correct the corresponding bit. observed that the number of parity bits (n k) is five instead
For this modification to work, this checking must be suffi- of four. However, the maximum number of ones in any row
cient to uniquely identify the column of H corresponding to is five compared with six in (2). The number of ones is two
482 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 32, NO. 3, MARCH 2013

TABLE IV
Delay Estimates for the SEC Encoder and Decoder

Hamming Proposed SEC Reduction

k Enc Dec Enc Dec Enc Dec
8 0.27 0.42 0.23 0.37 14.8% 11.9%
16 0.33 0.49 0.28 0.40 15.2% 18.4%
32 0.39 0.56 0.30 0.45 23.1% 19.6%
64 0.45 0.65 0.35 0.48 22.2% 26.1%

input AND gate of traditional codes. The number of parity

check bits required is the same as existing SEC-DED codes for
small values of k, as can be seen comparing Tables I and III.
The number of ones in the parity check matrix is also the same
as in Hsiao SEC-DED codes [4] for small values of k (see
Table II). For larger values of k, reductions in the number of
ones in the parity check matrix are obtained at the expense of
additional parity check bits. One interesting observation is that
Fig. 3. Structure of the decoder for the proposed SEC code with k = 8.
Hsiao codes for small values of k have a weight of three in all
TABLE III
the data bits. Therefore, the proposed optimized error location
Number of Parity Bits in the Proposed SEC and SEC-DED Codes
scheme can be used to reduce the delay of the decoders when
we are only interested in correcting errors on the data bits.
k SEC (Weight Two) SEC-DED (Weight Three) One distinct feature of the proposed codes is that they
8 5 5 correct errors on the data bits only. This is similar to other
16 7 6 codes such as orthogonal Latin square (OLS) codes [10].
32 9 7
However, in OLS codes, each pair of data bits participates
64 12 9
in at most one shared parity check bit to ensure that majority
logic decoding can be used. This is different from the proposed
in every column compared to some columns with three ones scheme in which the goal is to ensure that no data bit
in the Hamming matrix. This reduction in the number of ones participates in all the parity check bits, in which another data
enables a lower encoding and decoding delay. The proposed bit participates. This is then used to simplify the location and
decoder is illustrated in Fig. 3. Compared with the one in correction of an error, as described before. Another difference
Fig. 2, it can be observed that the logic depth is significantly is that OLS codes are commonly used when multiple error
smaller. The reduction in the upper part comes from having correction capabilities are needed although SEC can also be
less ones in the rows of H. The reduction in the lower part implemented. The main issues with SEC OLS codes are that
comes from having only two ones in the columns of H and they are only implemented for a few block sizes and require
using the modified decoding to correct errors. a large number of parity check bits.
Finally, it is worth mentioning that the parity check matrixes
0 0 0 0 0 0 1 1 1 0 0 0 0 of the proposed codes are similar to that of low density
0 0 0 1 1 1 0 0 0 1 0 0 0
parity check (LDPC) codes commonly used in communication
H = 0 1 1 0 0 1 0 0 0 0 1 0 0 (7)

systems [11]. Nevertheless, since LDPC codes usually have
1 0 1 0 1 0 0 1 0 0 0 1 0
large block size, and must provide multiple error correction,
1 1 0 1 0 0 1 0 0 0 0 0 1 the encoding and decoding procedures are very different from
In a general case, a Hamming code will have rows with a our proposed codes and require complex logic circuitry [11].
number of ones that is roughly k/2. This compares with the
proposed SEC codes (w = 2) for which the number of ones in
a row is by design at most n k 1. Similarly, to locate an IV. Evaluation
error a traditional SEC code requires an n k input AND gate To evaluate the benefits of the proposed codes in practical
compared with a simple two input AND gate in the proposed implementations, the method has been used to design SEC
code. In practical implementations, this results in a significant and SEC-DED codes for the values of k in Table II. Then,
reduction of the encoding and decoding delays, as discussed the encoders and decoders have been implemented in HDL.
in the next section. The number of parity bits is, however, The designs have then been synthesized for the 45 nm OSU
larger than for traditional SEC codes. Table III illustrates for FreePDK Standard Cell Library [12] using Synopsys Design
different values of k the number of parity check bits required Compiler. The results of the proposed SEC codes are com-
in the proposed scheme. Those can be directly compared with pared with those of an SEC Hamming code. For SEC-DED,
the values for the Hamming codes in Table I. the proposed codes are compared with the optimized SEC-
For the proposed SEC-DED codes (w = 3), a three-input DED codes recently proposed in [6]. In all cases, the decoders
AND gate is needed to locate an error compared with the n k only correct errors in the data bits.
REVIRIEGO et al.: METHOD TO CONSTRUCT LOW DELAY SEC CODES 483

TABLE V for SEC-DED codes the value goes up to 0.82 ns. This means
Area Estimates for the SEC Encoder and Decoder that for a 250 MHz circuit approximately 20% of the clock
will be devoted to the ECC protection. For circuits that have
Hamming Proposed SEC Reduction
a higher clock rate, there will be parts of the circuit that have
k Enc Dec Enc Dec Enc Dec
8 84.5 416.3 71.3 306.9 15.6% 26.3%
significant timing margin, and therefore the ECCs can still
16 177.4 630.7 168.9 504.6 4.8% 20.0% be used to protect those parts of the circuits while the faster
32 399.4 918.4 321.0 762.1 19.6% 17.0% triplication with voting can be used on the critical paths.
64 855.1 1982.8 685.6 1559.5 19.8% 21.4%
V. Conclusion
TABLE VI
In this paper, a method to construct low delay SEC and
Delay Estimates for the SEC-DED Encoder and Decoder
SEC-DED codes was presented. The proposed method used
SEC-DED [6] Proposed SEC-DED Reduction
some additional parity bits to reduce the number of ones in the
k Enc Dec Enc Dec Enc Dec rows and columns of the parity check matrix. This reduction
8 0.29 0.45 0.29 0.41 0.0% 8.9% was then used to simplify the decoding logic to achieve
16 0.36 0.54 0.32 0.50 11.1% 7.4% lower delay and area. The proposed method was evaluated
32 0.46 0.61 0.37 0.58 19.6% 4.9% and compared with traditional SEC Hamming and SEC-DED
64 0.47 0.65 0.42 0.61 10.6% 6.2% codes, showing significant reductions in both area and delay.
The proposed codes can be useful to protect registers in
TABLE VII circuits where the area and delay of the encoder and decoder
Area Estimates for the SEC-DED Encoder and Decoder can be a more important issue than the number of parity bits.
The codes can also be useful to protect high-speed memories
SEC-DED [6] Proposed SEC-DED Reduction or caches as they can minimize delay at the expense of a few
k Enc Dec Enc Dec Enc Dec additional parity check bits.
8 143.1 415.7 113.6 355.8 20.6% 14.4%
16 247.3 694.6 227.1 563.7 8.2% 19.8%
32 464.4 1060.2 455.2 927.3 2.0% 12.5% Acknowledgment
64 814.2 1904.8 905.7 1881.4 11.2% 1.2% The authors would like to thank V. Gherman, S. Evain,
and Y. Bonhomme for providing the H matrixes of the codes
presented in [6].
The delay estimates (in ns) and area estimates (in m2 ) for
both the encoder (Enc) and the decoder (Dec) SEC codes are
shown in Tables IV and V. For delay, significant reductions References
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