A Stack-Based Routing Methodology For Nanometric

Analogue CMOS Devices

Stephanie Youssef, Damien Dupuis, Ramy Iskander, Marie-Minerve Louerat

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Stephanie Youssef, Damien Dupuis, Ramy Iskander, Marie-Minerve Louerat. A Stack-Based
Routing Methodology For Nanometric Analogue CMOS Devices. The IEEE Virtual World-
wide Forum For PhD Researchers in Electronic Design Automation, (VW FEDA), Nov 2011,
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 A Stack-Based Routing Methodology For
Nanometric Analogue CMOS Devices
Stephanie YOUSSEF, Damien DUPUIS, Ramy ISKANDER and Marie-Minerve LOUERAT
LIP6 Laboratory, University of Pierre and Marie-Curie, France
Email: [email protected]

Abstract In this paper, we present a nanometric layout or specific RF constraints [11]. The close link between the
generation tool for analogue building blocks called devices. We physical realization and the electrical behavior leads the circuit
focus on the procedural routing methods inside devices. A device designer to compare several layout styles with appropriate
may have one or more folded transistors fingers merged into
at least one stack depending on the chosen layout style. We routing of the basic cell (device) and choose the most suitable
present two routing methods: intra-stack and inter-stack to ease one, according to the specification of the whole circuit.
the routing of the wired segments. Taking advantage of both In this paper, we will focus on basic building blocks called
routing methods, the layout generation tool provides a range devices to develop a library of parametrized analogue cells
of transistor folding to respect the designer-defined constraints that support different layout styles (interdigitated, mirror, M2
(either electrical or physical). Both routing methods are used
to generate different layout styles. The layout generation for a module and 2D common-centroid). We introduce a parametric
differential pair device is illustrated using four layout styles: generic routing methodology. This methodology provides the
interdigitated, mirror, 2D common-centroid and M2 modules. designer a procedural way to perform a symmetrical routing
Keywords: Migration, Layout Generation, Routing, Stress effects and therefore a symmetrical layout. Its main advantage is to
handle a large set of device topologies based on a generic
Python method driven with a few input parameters. The
I. I NTRODUCTION
resulting procedural description of a device may handle several
A lot of studies have targeted the automation of the layout technology processes and several aspect ratio. Based upon
generation of analogue circuits [1][12]. Their common goal these generic devices, parametrized analogue blocks can be
is to improve the analogue IC design cycle [5], [13] to get designed as reusable blocks matching use-case constraints (i.e.
closer to the efficiency of the digital one. The challenge is that low-power, RF, ...). Taking advantage of such reusable blocks,
the layout generation must support the evolution of CMOS the whole analogue IC design cycle may be improved.
down to the deep submicron technologies while meeting a The remainder of this paper is organized as follows. Sec-
wide range of constraints dealing with power supply, power tion II introduces the context of the layout generation tool,
consumption, biasing, high speed, area, symmetry, matching, then presents the definitions of the device and the stack
coupling. With the migration to deep-sub-micron (DSM) tech- object. Section III introduces the two routing methodologies.
nologies, a new constraint related to the MOS technology Section IV illustrates the routing results for a differential
process has to be taken into consideration. pair device with four layout styles: Interdigitated, mirror, 2D-
The DSM technologies use Shallow Trench Isolation (STI) common centroid and M2-Module styles. Finally, we conclude
for its accurate dimension control when compared with LO- in section V.
COS isolation [14]. STI is implemented in the form of trenches
II. L AYOUT OF THE DEVICE
etched into the wafer and filled with silicon dioxide to isolate
the active area of the transistors. Although STI provides some A. Proposed Layout Generation Tool
degree of latch-up protection [15], this isolation technique The flow, still commonly used, for an analogue circuit con-
induces mechanical stress on the transistor and hence degrades sists of laborious iteration loops. Each iteration is composed
its performance [16][18]. As shown in [19], this mechanical of several steps: circuit sizing, layout generation, parasistics
stress is highly dependent on the layout style being used. To extraction and performance evaluation. While performances
reduce the impact of mechanical stress, the layout must be are not satisfactory, the loop is repeated. It is time consuming
designed so that all the transistors of the device are affected and subject to human errors. To speed up the design cycle,
in the same way. layout oriented methodolody were proposed [4], [6], [7], [9],
Analogue circuits are much more sensitive to the layout [10], [20], [21].
than the digital ones and their performance may be affected [4] showed the advantage of providing a two ways
easily. Hence it is required to carefully control the routing communication between the sizing and layout generation as
from the transistor level in order to respect the different shown in Fig. 1. The idea is that the sizing tool provides
constraints that highly depend on the application. Examples the layout generation tool with the electrical parameters of
are the parasitic capacitance and resistance induced by the the transistor such as the width (W), length (L), number of
routing wires to avoid the cross talk between wires [1], [6] fingers (NF), etc... Once the layout is generated, the layout
 Fig. 1. Applied design flow.
Fig. 2. Layout stack example W = 2.0m, L = 0.2m, N F s = 7,
T ype = N M OS and N Bdummies = 1.

tool sends back the layout-dependent parasitic parameters

such as the drain and source areas and perimeters, the stress NFs: The number of stacks fingers (including dum-
effect parameters, etc... to re-evaluate the performance. This mies).
internal loop is repeated several times, with minimal designer NBdum : The number of dummies at each stack ends
intervention, till the targeted specifications are achieved. The (same for both ends).
final layout is then realized. This methodology minimizes the
design time and possible errors. It has been implemented into Note that we assume that each finger of the stack, except
our framework which is dedicated to analogue synthesis and dummies, has the same width and length. Based on this
technology migration for mixed-signal circuits in nanometric createStack() method, a dedicated Python API has been
technologies. Our layout generation tool allows the generation introduced to provide the designer with the possibility to
of parametrized and shaped layouts, with different analogue describe a device as a stack arrangement. The generated layout
dedicated layout styles [8], [12], [22]. passes design rule checking.
2) Layout Dependant Parameter Computation Methods:
B. The Device Definition Three Layout Dependant Parameter (LDP) computation meth-
A device is defined as an atomic analogue function realized ods have been introduced in the stack object, described in
by a small set of transistors. The motivation to build a device Python. The first one computes the diffusion parameters like
is the following: the analogue electrical behavior of the set of the area and perimeter of the drain and source zones. The
transistors requires a dedicated layout with strong geometrical second one computes the stress effect parameters introduced
and robustness constraints. Therefore the layout of the tran- in BSIM4 [24] to model nanometric DSM effects. The third
sistors set has to be designed as a whole. A typical library one computes the parasitic capacitance and resistance due to
of analogue devices contains: a folded transistor, a differential the routing. A dedicated Python API has been introduced to
pair, a current mirror and a cross coupled pair. Each device provide the device designer with the LDP values of a stack.
may have different layout styles to match use-case constraints. Since each device uses at least one stack, the device designer
Here we will study four different styles of the differential pair: may compute easily the device LDP from the stack LDP.
interdigitated, mirror, 2D common-centroid and M2 module
[12] to illustrate our two routing methodologies. III. ROUTING M ETHODOLOGY
A. Intra-Stack Routing Methodology
C. The Stack Object
The intra-stack routing addresses the routing between tran-
1) Stack object: Transistor folding technique is commonly sistors connectors inside the same stack. The idea is to
used in analogue circuits to control the aspect ratio of the reserve track(s) for routing each net of the stack according
device layout and to reduce parasitic capacitance and gate to the chosen pattern as shown in Fig. 3. Each device net is
resistance [3], [23] while allowing more accurate geometries routed, one after the other, i.e. Drain (D), Bulk (B), Gate (G),
and providing better electrical performance. Interdigitation and Source (S), etc... Different patterns are supported: line, comb,
mirror styles are usually used to equally distribute process serpentine or mixed between these three patterns. The goal is
gradients along the device. Since the stack structure is a to set up a simple method that takes advantage of the regular
common feature of the analogue device, we have defined structure of the stack while supporting its shape variation
a Stack object [19]. To create the layout of a complete resulting from its parameter variation: transistor width, length
stack, the designer of parametrized analogue devices simply and number of fingers. The designer should specify only a set
calls the createStack() method with well specified input of combination of 1s and 0s where 1 indicates a top track
parameters as shown in Fig. 2. A device layout is made of a and 0 indicates a bottom track.
set of horizontal or vertical stacks. This combination is called pattern. For example if the
The input parameters of the createStack() method are : designer specify 1 pattern to a net, this net will be routed
Type: The type of the transistor NMOS or PMOS. in a top line pattern like Fig. 4.a, if the designer specify 0
W: The overall width of the transistor. pattern to a net, this net will be routed in a bottom line pattern
L: The length of each finger (except dummies). like Fig. 4.b, if the designer specify 10 pattern to a net, this
 Fig. 5. L-Shape routing, dx specified.

Fig. 3. One stack with reserved tracks.

net will be routed in a serpentine pattern like Fig. 4.c. Also the
designer can choose any other random pattern like in Fig. 4.d.
The first routed net has the first reserved track.
The advantage of the method is that the designer can specify
any pattern and the router draws automatically the routing Fig. 6. Z-Shape routing, dx specified.
segments at the appropriate reserved tracks that passes the
DRC check.

Fig. 4. Different inter-stack routing patterns.

Fig. 7. U-Shape routing, dx specified.

B. Inter-Stack Routing Methodology
The inter-stack routing method addresses the routing be-
tween two routing segments of the same net belonging
to two different stacks of the same device. This method
routeSegments() performs segment to segment routing.
It supports different patterns like Line, L-shape, U-shape or
Z-shape. Unlike the intra-stack routing methodology, the inter-
stack methodology allows routing around and between stacks.
This method has four parameters: the net to be routed, the
first segment (Segment 1) and the second segment (Segment Fig. 8. U-Shape routing, dx specified.
2) to be routed and some coordinates. Depending on the
coordinates specified by the device designer, this method is
able to deduce the suitable pattern.
The special case of two horizontal segments routing is
detailed in the following. Eight different parameters config-
urations are considered. In each case, the designer specifies
at least the value of X1 and X2 belonging respectively
to Segment 1 and Segment 2. Then, depending upon the
remaining parameter, the method selects automatically the Fig. 9. L-Shape routing, dy specified.
suitable shape:
1) dx = 0, L-Shape is deduced (Fig.5).
2) 0 < dx < X2 X1, Z-Shape is deduced (Fig.6).
3) dx > X2 X1, U-Shape is deduced (Fig.7).
4) 0 > dx, U-Shape is deduced (Fig.8).
5) dy = 0, L-Shape is deduced (Fig.9).
6) Y 2 Y 1 < dy < 0, Z-Shape is deduced (Fig.10).
7) dy < Y 2 Y 1, U-Shape is deduced (Fig.11).
8) dy > 0, U-Shape is deduced (Fig.12). Fig. 10. Z-Shape routing, dy specified.
 transistors since the parasitic capacitance and resistance are
directly proportional to the length of the routing segments of
each net. Also, the two transistors T1 and T2 are affected by
the same stress effect.

Fig. 11. U-Shape routing, dy specified.

Fig. 12. U-Shape routing, dy specified. Fig. 14. Differential pair interdigitated style W = 3.0m, L = 0.15m,
N F = 4, T ype = N M OS and N Bdummies = 0.

Similar algorithms are introduced to route two vertical

segments or one vertical segment with one horizontal segment.
B. Mirror Differential Pair
IV. R ESULTS
The mirror technique alternates fingers of T1 and T2 starting
In the following examples, we consider the differential from the middle of the stack. Fig. 15 shows a differential pair
pair device shown in Fig. 13 in CMOS 65nm technology. with mirror style. The gate nets G1 and G2 are routed in a
This device is composed of two transistors that have to be line pattern, while the two drain nets D1 and D2 are routed
matched. Among the several ways to match and organize the in a comb pattern and finally the source net S is routed in
two transistors in one stack, we consider the interdigitated a mixed pattern. It can be noticed that the routing segments
and the mirror styles [22] to illustrate the intra-stack routing lengths of neither the drain nets D1 and D2, nor the gate
methodology. The multi-stack organization as well as the the nets G1 and G2 are equal. So there will be some mismatch
inter-stack routing will be illustrated by the M2 Module and in the electrical behavior between the two transistors. Also,
the 2D common-centroid styles [22]. The transistor T 1 has T1 transistor, placed at the boundaries of the stack, suffers
top connectors grids (called G1) and the transistor T 2 has a more significant stress effect than T2 transistor. This is
bottom connectors grids (called G2). due to the fact that T1 is closer to the STI. Its important
to note that although the mirror technique is preferred in
the old technologies, the interdigitated layout style is much
preferred in nanometric technologies to eliminate the stress
effects, which are more significant.
In the interdigitated and the mirror styles we used only the
inter-stack routing methodology because the device is made
Fig. 13. Differential Pair Schematic View. of a single stack.

A. Interdigitated Differential Pair

The interdigitated technique simply alternates n fingers of
each transistor from left to right of the stack. Fig. 14 shows a
differential pair in interdigitated style. The hatched segments
show the inter-stack routing segments. The gate nets G1 and
G2 are routed in a line pattern, while the two drain nets D1
and D2 are routed in a comb pattern and finally the source
net S is routed in a serpentine pattern.
It can be noticed that the length of the routing segments of
the drain net D1 is equal to the length of the drain net D2, and
the length of the routing segments of the gate net G1 is equal to Fig. 15. Differential pair mirror style W = 3.0m, L = 0.15m, N F = 4,
T ype = N M OS and N Bdummies = 0.
the length of the gate net G2. This deals with the decreasing
of the mismatch in the electrical behavior between the two
C. M2 Module Differential Pair
The idea of the M2 module [12] showed in Fig. 16, is
to encapsulate every two fingers of the same transistor in
a separated stack. The advantage of this approach is that
although it takes more area, the stress effect of each stack
is well defined and each stack can be placed in different
topologies to control the overall placement of each transistor
inside the device.

Fig. 16. Differential pair M2 module style W = 3.0m, L = 0.15m,

N F = 4, T ype = N M OS and N Bdummies = 0.

Since this device is a multi-stack one, it takes advantage of

both intra-stack and inter-stack routing methods. The hatched
segments show the inter-stacks routing segments and the
unhatched segments show the intra-stack routing segments
(Fig. 16). The gate nets G1 and G2 are routed in a line pattern
and the drain nets D1 and D2 as well as the source net S are
Fig. 17. Differential pair 2D common-centroid style W = 3.0m, L =
routed in a U-shape pattern. The length of the routing segments 0.15m, N F = 8, T ype = N M OS and N Bdummies = 0.
of the gate and drain of each transistor is the same, allowing
transistor matching. TABLE I
ROUTING SEGMENTS LENGTH AS FUNCTION OF LAYOUT STYLE
D. 2D Common-Centroid Differential Pair
Routing segments length in m.
The idea of the two 2D common-centroid [8] is to split
the device into different stacks and placed the finger of these Interdigitated Mirror M2 Module 2D Common
stacks a specific way so that all the transistors fingers of all Centroid
the stacks have the a common center point.
Net G1 6.94 7.98 12.88 13.24
This device being also a multi-stack one, it takes advan- Net G2 6.94 5.9 12.88 13.24
tage of both intra-stack and inter-stack routing methods. The Net D1 10.8 11.825 16.745 17.17
Net D2 10.8 9.655 16.745 17.17
hatched segments show the inter-stacks routing segments and Net S 21.465 21.465 40.74 27.645
the unhatched segments show the intra-stack routing segments
(Fig. 17). The source net S is routed in a line pattern and the
other nets are routed in a U-shape pattern. It can be noticed
that although the required area is large, the length of the 3.0m, L = 0.15m, N F = 4 (interdigitated, mirror and
routing segments of the gate and drain of each transistor is M2 module cases) or N F = 8 (2D common-centroid case),
the same, allowing transistor matching. T ype = N M OS and N Bdummies = 0 respectively for the
four layout styles (interdigitated, mirror, M2 Module and 2D
E. Routing and Area Comparison
common-centroid). Note that the routing area is larger than
Table I shows the total length of each routed net for each the active area in all the cases.
transistor of the differential pair in a 65 nm technology, with These tables provide the circuit designer with a clear vision
W = 3.0m, L = 0.15m, N F = 4 (interdigitated, mirror of the advantage and drawbacks of various solutions to draw
and M2 module cases) or N F = 8 (2D common-centroid analogue device layouts.
case), T ype = N M OS and N Bdummies =0 respectively for
the four layout styles (interdigitated, mirror, M2 Module and F. Layout Dependant Parameter: Routing Capacitance
2D common-centroid). Nets G1 and D1 belong to transistor Let us take the example of the differential pair with 2D
T1, nets G2 and D2 belong to transistor T2. Net S is shared common-centroid style, with W = 1.45m, L = 0.18m
between T1 and T2. and N F = 4 in CMOS 65 nm technology. After the layout
Table II compares area, aspect ratio and matching features generation, the LDP, such as the parasitic routing capacitance
of the differential pair in a 65 nm technology, with W = and resistance can be retreived from the device. Table III
 TABLE II
[4] Mohamed Dessouky, Marie-Minerve Lou erat, and Jacky Porte. Layout-
A REA AND M ATCHING F EATURES AS F UNCTION OF L AYOUT S TYLES Oriented Synthesis of High Performance Analog Circuits . In Proc.
Design, Automation and Test in Europe, pages 5357, Paris, France,
Areas in m 2. March 2000.
[5] Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, and
Interdigitated Mirror M2 Module 2D Common C. J. Richard Shi. IPRAIlintellectual property reuse-based analog IC
Centroid
layout automation. Integration, the VLSI Journal, 36(4):237 262, 2003.
Analog and Mixed-signal IC Design and Design Methodologies.
Total area 10.01 10.01 17.70 27.67 [6] Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sam-
Active area 3.23 3.23 5.46 13.65 path, Ranga Vemuri, and Georges Gielen. Fast, layout-inclusive analog
height/width 0.48 0.48 0.27 2.07 circuit synthesis using pre-compiled parasitic-aware symbolic perfor-
horizontal mance models. In Proc. Design, Automation and Test in Europe Conf.,
gradient + + +
pages 604609, Paris, France, February 2004.
compensation
[7] D. Stefanovic, M. Kayal, and M. Pastre. PAD: A new interactive
vertical
gradient +
knowledge-based analog design approach. Analog Integrated Circuits
compensation and Signal Processing, Kluwer Academic Publishers, pages 291299,
March 2005.
STI + ++ + [8] Qiang Ma, E.F.Y. Young, and K.P. Pun. Analog placement with common
compensation centroid constraints. In Computer-Aided Design, 2007. ICCAD 2007.
IEEE/ACM International Conference on, pages 579 585, november
2007.
[9] Rafael Castro-Lopez, O. Guerra, E. Roca, and F.V. Fernandez. An
shows the values of the parasitic routing capacitances related Integrated Layout-Synthesis Approach for Analog ICs. IEEE Trans.
on Computer Aided Design, 27(7):11791189, July 2008.
to the gate net, drain net and source net of one of the two [10] H. Graeb, F. Balasa, R. Castro-Lopez, Y.W Chang, F.V. Fernandez,
transistors of the differential pair. P.H Lin, and M. Strasser. Analog layout synthesis - Recent advances
in topological approaches. In Design, Automation Test in Europe
TABLE III Conference Exhibition, 2009. DATE 09., pages 274 279, april 2009.
PARASITIC ROUTING CAPACITANCES OF A 2D COMMON - CENTROID [11] E. Avci, M. Strasser, H. Graeb, and U. Schlichtmann. A free-shape
router for analog and RF applications. In Circuit Theory and Design,
DIFFERENTIAL PAIR 2009. ECCTD 2009. European Conference on, pages 771 774, august
2009.
Capacitance in fF. [12] L. Lewyn, and N. Williams. Is a New Paradigm for Nanoscale Analog
Gate Net Drain Net Source Net CMOS Design Needed? Proceedings of the IEEE, 99(1):3 6, january
0.0581 0.0937 0.0389 2011.
[13] R. Sommer, I. Rugen-Herzig, E. Hennig, U. Gatti, P. Malcovati, F. Mal-
oberti, K. Einwich, C. Clauss, P. Schwarz, and G. Noessing. From
In this example the value of the parasitic routing capacitance system specification to layout: Seamless top-down design methods for
analog and mixed-signal applications. In Proc. Design Automation and
of the G1 net is equal to the G2 one (Gate Net capacitance). Test in Europe Conf. (DATE), page 884, 2002.
The value of the parasitic routing capacitance of the D1 net [14] Darius Andriukaitis, Romualdas Anilionis, and Tomas Kersys. LOCOS
is equal to the D2 one (Drain Net capacitance). CMOS process simulation. In Conf. Information Technology Interfaces,
pages 489 494, Catvat, Croatia, June 2006.
V. C ONCLUSION [15] Wang-Ling Goh, Kiat-Seng Yeo, Stephen Lazuardi, Wei Peng, Kam-
Chew Leong, Lap Chan, and Alex See. Latchup characterization of
In this paper we have presented a method that allows simple 0.18-micron sti cobalt silicided test structures. Microelectronics Journal,
and concise description for complex devices in nanometric 32(9):725 731, 2001.
[16] W.L. Goh et al. A comprehensive geometrical and biasing analysis for
technologies. It allows direct and accurate quantification of latchup in 0.18-m Co SI2 STI CMOS structure. Solid-State Electronics
the layout-dependent parameters for different layout styles. J., 48(12):2109 2114, 2004.
The designer is therefore able to compare between layout [17] V. Moroz, and G. Eneman, and P. Verheyen, and F. Nouri, and L.
Washington, and L. Smith, and M. Jurczak, and D. Pramanik, and X.
styles and choose the suitable device layout for his circuit. Xu. The impact of layout on stress-enhanced transistor performance.
We have investigated the two routing methods (intra-stack In Int. Conf. on Simulation of Semiconductor Processes and Devices,
routing and inter-stack routing) for a differential pair in four pages 143 146, Tokyo, Japan, September 2005.
[18] P.G. Drennan and M. L. Kniffin and D. R. Locascio. Implications of
different styles (interdigitated, mirror, M2 module and the 2D proximity effects for analog design. In Custom Integrated Circuits Conf.,
common-centroid). We showed that layout styles preferred for pages 169 176, San Diego, USA, September 2006.
old technologies, such as mirror, may not be beneficial for [19] Stephanie Youssef and Damien Dupuis and Ramy Iskander and Marie-
Minerve Louerat. Automatic Stress Effects Computation Based On A
new nanometric technologies. Layout Generation Tool For Analog IC. In IEEE International Be-
havioral Modeling and Simulation Conference, pages 712, September
R EFERENCES 2010.
[1] D.J. Garrod, R.A. Rutenbar, and L.R. Carley. Automatic layout of [20] Vivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, and Kanak
custom analog cells in ANAGRAM. In Computer-Aided Design, 1988. Agarwal. Stress aware layout optimization. In Proc. Int. Symp. on
ICCAD-88. Digest of Technical Papers., IEEE International Conference Physical design, pages 168174, Portland, Oregon, April 2008.
on, pages 544 547, november 1988. [21] Ender Yilmaz and Gunhan Dundar. Analog layout generator for cmos
[2] J. M. Cohn, R. A. Rutenbar, and L. R. Carley. KOAN/ANAGRAM II: circuits. cad, 28(1):3245, january 2009.
New Tools for Device-Level Analog Placement and Routing. IEEE J. [22] R. Jacob Baker. CMOS: circuit design, layout, and simulation. John
of Solid-State Circuits, 26(3):330342, march 1991. Wiley and Sons, 2008.
[3] Ravindranath Naiknaware and Terri S. Fiez. Automated hierarchical [23] Behzad Razavi. Design of Analog CMOS Integrated Circuits. McGraw-
CMOS analog circuit stack generation with intramodule connectivity and Hill, 2000.
matching considerations. IEEE J. of Solid-State Circuits, 34(3):304317, [24] W. Liu. MOSFET Models for SPICE Simulation including BSIM3v3 and
March 1999. BSIM4. Wiley Interscience, 2001.