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Pin Assignment

Pin assignment in EDI allows optimizing pin locations for partitions and blackboxes. Pins can be assigned automatically or through placement and routing-based methods. Various constraints can guide pin assignment, including pin guides, blockages, layers, and spacing. The checkPinAssignment command verifies legal pin assignment and pinAnalysis reports quality metrics.

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0% found this document useful (0 votes)
690 views

Pin Assignment

Pin assignment in EDI allows optimizing pin locations for partitions and blackboxes. Pins can be assigned automatically or through placement and routing-based methods. Various constraints can guide pin assignment, including pin guides, blockages, layers, and spacing. The checkPinAssignment command verifies legal pin assignment and pinAnalysis reports quality metrics.

Uploaded by

Abhishek Chauhan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Pin Assignment Flow in EDI

May 2010

Product(s)
Encounter Digital Implementation (EDI) System

Purpose

This document explains pin assignment flow in EDI.


Pin Assignment:

You can optimize partition and blackbox pins in the EDI System environment based on routing or
placement information. You can assign the pins or ports to a location on a partition, and set various
constraints as per your requirements on pin assignment, for example, you can create pin blockages on
specified areas.

Run the Check Pin Assignment menu command (Partition Check Pin Assignment) or the
checkPinAssignment text command after pin assignment to make sure that all pins are assigned, are
placed on routing grids, and are not overlapping.

Blackbox pins are assigned in the same way as partition pins.

Pin assignment supports the following:


Rectilinear partitions and black boxes
Repeated partitions and black boxes. Both master and clones are considered when assigning their
pins.
Designs with an arbitrary origin.
Non-uniform tracks.
Pin Assignment Methodology:
Automatic Pin Assignment:

Pin assignment support all types of pins such as partition, black box, and I/O pins. You can use
assignPtnPin command to assign pins to black box and partition as well and assignIoPins command to
assign I/O pins.

assignPtnPin:Assign black box and/or assignIoPins: Assign I/O pins


partition pins
Partition/Black Box Pin Assignment:

Black box pin versus partition pin


There is no visibility to placement within Black Boxes, so any solution along the neighboring edges of the
partitions is equally good. Black Box Pin Assignment is provided for early in the design cycle before
gate-level netlist for all partitions is available.

With partition pin assignment, the tool has visibility within the partitions in a virtual-flat view and uses this
information to derive pin locations. Shown here, the pin is placed such that the total net length after
assembly is more optimal.

Black-box pin assignment Partition pin assignment

Support both placement and route-based for black box and partition pin assignment

Placement-based pin assignment does not consider congestion, so scenic routing may occur to make this
connection. Pin assignment is based on connectivity flightlines. Cell placement should be performed
before running pin assignment.

Route-based pin assignment does consider routing blockages. For route-based pin assignment, routing
should be performed prior to the assignPtnPin command. It uses trialRoute topology to determine pin
locations, so scenic routing can be avoided.
Placement based pin assignment Routing based pin assignment

Support channel-less design

Pin assignment can place pins on abutted partition. It reserves abutment edge segments for 2 pins nets
between abutted partitions. Earlier all 2-pin nets in the channel-less design were not aligned.

SEG1: Abutted edge segment between A3 and C1 N1: Set of 2 pins nets between A3 and C1
SEG2: Abutted edge segment between C1 and C2 N2: Set of 2 pins nets between C1 and C2
SEG3: Abutted edge segment between P1 and P2 N3: Set of 2 pins nets between P1 and P2

Support master clone designs


Pin assignment does support master and clone pin assignment. It will look at both master and
clone partitions and assign pins such that pin locations will best results for both master and
clones. This capability is enabled by default. So, you do not need to specify any additional option
for the assignPtnPin command.

First you need to use definePartition command or Partition->Specify Partition GUI to define
partition for this block. You can use -hinst option to specify which instance is the master. The
master partition must have a R0 orientation. Since other instances are referenced the same cell
as the master hierarchical instance, EDI will automatically know they are clones. Once you define
partition for this block, you go through the normal flow and then run assignPtnPin command.
Guiding Pin Assignment:

You can create pin/bus guide to selective guide specific signal pins to be placed in certain area.
Use createPinGuide/createBusGuide command to create pin/bus guide.

You can create pin blockage to prohibit pin placement in certain area. Use createPinBlkg
command to create pin blockage.

You can create pin/net group to place a group of pins in specific order. Use
createPinGroup/createNetGroup and addPinToPinGroup/addNetToNetGroup commands to
create pin/net group and add pins/nets to these groups.

Pin assigned in bus guide area Bus guide Pin blockage Pin guide

You can provide different types of pin constraints for pin assignment:

Pin size will be created based on the minimum area rule by default. Use the
setLayerPinWidth and setLayerPinDepth commands to set new pin width and
depth of a routing layer for a specific partition/black box cell. You can also
specify pin size for a specific pin or pin group using the setPinWidth and the
setPinDepth commands.

You can set the pin-to-corner distance constraint to keep pins away from
partition/black box corners. The default value is 5 routing tracks. Use
setPinToCornerDistance command to set the pin-to-corner distance for a
module.
5 tracks away from corner of partition

Pin size that meets min area rule

You can specify pin layers that will be used for placing pins on a specific partition
side:
You can specify layer constraint per edge at partition level. Use
setAllowedPinLayersOnEdge command with -layer and edge options to
specify layer and edge.

You can specify layer constraints for all pin members of a pin/bus guide.
Use layer option of createPinGuide/ createBusGuide command to
specify the layer. Layer constraint at pin guide will override the layer
constraint at partition level.

You can specify layer constraint for a specific partition/black box pin. Use
-layer parameter of the setPinConstraint command to specify the layer.
Layer constraint at pin level will have higher priority than layer constraint
at partition level.

You can set minimum pin spacing in terms of track number. The default pin
spacing is 2, which places a pin for every two metal tracks.
You can specify global pin spacing at design level Design. Use
setGlobalMinPinSpacing command to set global pin spacing.

You can specify pin spacing at partition/black-box level. Use -


minPitchTop, -minPitchBottom, -minPitchLeft, and -minPitchRight
parameters of definePartition command to specify min spacing at
partition level.

You can specify min pin spacing for particular edge/side of a partition.
Use -edge parameter of the setMinPinSpacing command to specify min
pin spacing.
You can specify min pin spacing for a pin/net group. Use
createPinGroup/createNetGroup command to specify min pin spacing for
pin/net group.

You can specify min pin spacing to a particular pin. Use setPinConstraint
command to specify the min pin spacing to a particular pin.

As spacing constraint can be specified at more than one level, pin assignment will honor spacing
constraint in the following order:
- Pin spacing
- Net group or pin group spacing
- Partition/black box spacing on a particular edge
- Partition/black box spacing
- Global spacing

Useful Pin constraining commands:

Constraining pin layers:


setAllowedPinLayers
setAllowedPinLayersOnEdge
setPinConstraint [layer]
definePartition [-pinLayerTop]
createPinGroup [-alternateLayer]
createPinGuide [-layer]
createPinBlkg [-layer]

Constraining pin size (width & depth):


setPinWidth
setLayerPinWidth
setPinDepth
setLayerPinDepth

Constraining pin spacing/pitch:


setGlobalMinPinSpacing
setMinPinSpacingOnEdge
setPinConstraint [-spacing]
setMinPinSpacing
definePartition [-minPitchTop]
createPinGroup [-spacing]

Constraining specific pin locations:


setPinConstraint [-location x y z]
setPinConstraint [-edge]
createPinGroup [-edge]
createPinGuide [-area]
createPinBlkg [-edge] [-layer]
createPtnPinBlk [-edge] [-area]
setPinToCornerDistance
Constraining pin locations relative to other pins:
createPinGroup [-optimizeOrder]
createPinGuide [-edge] [-area] [-layer]

How to assign pins:

You can use assignPtnPin command or Partition Assign Pins GUI menu to assign pins. There is no
separate step required for assigning black box pins.

Checking Pin Legality:

Use checkPinAssigment command after pin assignment to make sure that pins are legalized (for
example, the pins snap to routing grid, are on reserved routing layers, honor user-specified constraints,
do not cause any DRC violations, and so on).

Report QoR of Pin Assignment:

Use pinAnalysis command to report certain Quality of Results (QoR) metrics for pin assignment. The
pinAnalysis command deletes the existing routes, reroutes the design ensuring that the routes pass
through partition pins, and reports pin assignment QoR metrics.

Adjusting Pins:

You can adjust pins using the Pin Editor or the editPin text command. You can also use direct pin
manipulation to manually move selected pins to different locations.

Aligning Partition Pins:

You can align partition pins with other block pins (using the Pin Editor or the pinAlignment text command).
The pinAlignment command can be used to align partition/black box pins with or without specified
reference object(s). Reference objects can be hard macros, blackboxes, I/O pads, and standard cells.

Running incremental Pin Assignment:

You can re-run pin assignment based on the current pin assignment result. You can specify pin
constraints to further guide new pin placement. If you want to reoptimize only a few specific pins, use the
-ptn and the -pin options of the assignPtnPin command to specify the list of pins that will be reassigned.

ECO Pin Assignment:


The EDI System software provides incremental or ECO pin assignment capability. This capability can be
used in the ECO flow where partition/black box ports in the original netlist get modified (added/deleted). In
this flow, you can preserve most of the existing partition/black box pin locations and let the software
assign the newly added pins.

Saving the Partition Pins:


You can use savePtnPin command to save pin placement information for later use.

Restore Partition Pin Information:


You can use loadPtnPin command to restore/load pin placement information of a particular
partition/blackbox.
Assigning Pins on Rectilinear Edges:
Rectilinear pin assignment can recognize rectilinear edges when assigning pins. It can support any
rectilinear shape (such as L, T, and U shapes).

Swapping Partition Pins:


You can swap pins using GUI or using the swapPins command.

Snapping Pins to the Grid:


To snap center of pins to nearest intersecting routing grid, where the horizontal and vertical routing tracks
cross, use the snapPtnPinsToTracks text command.

Pin Assignment Limitations:


Does not support non-R0 orientation black box (non-R0 master black box) pin assignment.
Does not assign or legalize pins on non-preferred routing layers.
Does not assign power/ground pins. For top-down hierarchical flow, power and ground pins will
be created during the partition step. For bottom-up flow, power/ground pins should be created at
design boundary during power planning stage.
Partition/blackbox pin assignment may cause routing crossing. In such cases, run the
pinAlignment command to improve pin QoR (Quality of Results).

Tips:
For channel-less design, 2-pin nets should be aligned on abutted edges. If they are not aligned or
unplaced:
o Make sure abutted edge(s) have enough room for placing pins of adjacent 2-pin nets
(example, remove un-needed routing blockages)
o Check if they are pins belonged to non-neighboring partitions. If yes then corresponding net
must be feedthrough insertion.
o Check if they are pins belonged to multi-fanout net. If yes, pins are unplaced and the
corresponding net must be feedthrough insertion.
Make sure multi-fanout net has driver; otherwise feedthrough wont be inserted
o May be encounter infeasible pin solution

assignPtnPin is not channel aware. Should create routing blockages in thin channels before
running trialRoute to assure that only pins that are connected between adjacent edges are get
assigned on these edges.

assignPtnPin is not shape based aware so pins may be placed close to adjacent macros that
caused DRC violation. Currently pin assignment only looks at 4 tracks from the boundary.

For pure black box design, assignPtnPin step is optional if


o Running trialRoute after design has been placed (trialRoute will automatically assign black
box pins AND
o Do not need to use any options of assignPtnPin

If design has empty modules then its recommended to use black box pin assignment instead of
partition pin assignment
Should use fastRouteForPinAssign or routeBasedBBoxPin option of trialRoute instead of
handlePartitionComplex
o Should not use fastRouteForPinAssign/-routeBasedBBoxPin for design with thin
channels > cause congestion at thin channels

Make sure design does not have partitions with non R0 master orientation
o Encounter will automatically convert non R0 black box master to R0
Transform its clone orientation accordingly
Placement location is unchanged

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