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Verilog Final Code

This document contains the code for a Verilog module that performs different operations (OR, AND, addition, multiplication) on two 8-bit inputs based on a 2-bit select signal. It constructs 16-bit representations of the inputs for the operations. It outputs the 16-bit result and flags indicating zero, positive, and negative results.

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2K views5 pages

Verilog Final Code

This document contains the code for a Verilog module that performs different operations (OR, AND, addition, multiplication) on two 8-bit inputs based on a 2-bit select signal. It constructs 16-bit representations of the inputs for the operations. It outputs the 16-bit result and flags indicating zero, positive, and negative results.

Uploaded by

api-332129590
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
//
// Company:
// Engineer:
//
// Create Date: 19:15:50 11/13/2016
// Design Name:
// Module Name: Final
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
//
module Final(
input [7:0] inp1,
input [7:0] inp2,
output reg [15:0] out,
input [1:0] s,
output pf,
output sf,
output zf
);
wire [15:0] aa;
wire [15:0] bb ;
wire [15:0] aaa;
wire [15:0] bbb ;
reg [15:0] sum;
reg cmp;
reg sum15;
reg [15:0] prod;
reg prod15;
reg zf,pf,sf;
assign aa[15]=0; // constucting a 16 bit equivalent for the input 1 for multipl
ication
assign aa[14]=0;
assign aa[13]=0;
assign aa[12]=0;
assign aa[11]=0;
assign aa[10]=0;
assign aa[9]=0;
assign aa[8]=0;
assign aa[7]=0;
assign aa[0]=inp1[0];
assign aa[1]=inp1[1];
assign aa[2]=inp1[2];
assign aa[3]=inp1[3];
assign aa[4]=inp1[4];
assign aa[5]=inp1[5];
assign aa[6]=inp1[6];
assign bb[15]=0; // constucting a 16 bit equivalent for the input 2 for multipl
ication
assign bb[14]=0;
assign bb[13]=0;
assign bb[12]=0;
assign bb[11]=0;
assign bb[10]=0;
assign bb[9]=0;
assign bb[8]=0;
assign bb[7]=0;
assign bb[0]=inp2[0];
assign bb[1]=inp2[1];
assign bb[2]=inp2[2];
assign bb[3]=inp2[3];
assign bb[4]=inp2[4];
assign bb[5]=inp2[5];
assign bb[6]=inp2[6];

assign aaa[15]=0; // constucting a 16 bit equivalent for the input 1 for addit
ion
assign aaa[14]=0;
assign aaa[13]=0;
assign aaa[12]=0;
assign aaa[11]=0;
assign aaa[10]=0;
assign aaa[9]=0;
assign aaa[8]=0;
assign aaa[7]=0;
assign aaa[0]=inp1[0];
assign aaa[1]=inp1[1];
assign aaa[2]=inp1[2];
assign aaa[3]=inp1[3];
assign aaa[4]=inp1[4];
assign aaa[5]=inp1[5];
assign aaa[6]=inp1[6];
assign bbb[15]=0; // constucting a 16 bit equivalent for the input 2 for additi
on
assign bbb[14]=0;
assign bbb[13]=0;
assign bbb[12]=0;
assign bbb[11]=0;
assign bbb[10]=0;
assign bbb[9]=0;
assign bbb[8]=0;
assign bbb[7]=0;
assign bbb[0]=inp2[0];
assign bbb[1]=inp2[1];
assign bbb[2]=inp2[2];
assign bbb[3]=inp2[3];
assign bbb[4]=inp2[4];
assign bbb[5]=inp2[5];
assign bbb[6]=inp2[6];
always @(*)
begin
if(s==2'b00) // ie select for
ORing
begin
out<=inp1 | inp2;
out[8]<=0;
out[9]<=0;
out[10]<=0;
out[11]<=0; //padding zeroes
out[12]<=0;
out[13]<=0;
out[14]<=0;
out[15]<=0;
if(out==16'b0000000000000000) //check for flag
s
begin
zf<=1;
end
else
zf<=0;
pf<=~(^out);
if(out[7]==1)
begin
sf<=1; //sequential assi
gnment
end
else
sf<=0;
end
else if(s==2'b01) // select for ANDi
ng
begin
out<= inp1 & inp2;
out[8]<=0;
out[9]<=0;
out[10]<=0;
out[11]<=0; //padding zeroes
out[12]<=0;
out[13]<=0;
out[14]<=0;
out[15]<=0;
if(out==16'b0000000000000000) //check for flags
begin
zf<=1;
end
else
zf<=0;
pf<=~(^out);
if(out[7]==1)
begin
sf<=1;
end
else
sf<=0;
end
else if(s==2'b10)
begin
if(inp1[7]==1'b0 && inp2[7]==1'b0) // ie both are po
sitive nos
begin
sum <= aa + bb ;
sum15<=0; // to indicate th
at the result is positive
end
else if (inp1[7]==1'b1 && inp2[7]==1'b0) // first is negat
ive and second is positive
begin
sum <= bb - aa;
cmp <= bb >= aa ? 1'b1 : 1'b0; // to compare - if
the negative number is more than the positive number => the final answer should
be negative
case(cmp)
1'b1: sum15<=0;
1'b0: sum15<=1;
endcase
end
else if (inp1[7]==1'b0 && inp2[7]==1'b1) // second is negati
ve and first is positive
begin
sum <= aa - bb;
cmp <= aa >= bb ? 1'b1 : 1'b0;
case(cmp)
1'b1: sum15<=0;
1'b0: sum15<=1;
endcase
end
else if (inp1[7]==1'b1 && inp2[7]==1'b1) // both are negati
ve
begin
sum <= aa + bb ;
sum15<=1;
end
sum[15]<=sum15;
assign out = sum ; // out - the final
answer
if(out==16'b0000000000000000) //check for flags
begin
zf<=1;
end
else
zf<=0;
pf<=~(^out);
if(out[7]==1)
begin
sf<=1;
end
else
sf<=0;
end
else if(s==2'b11)
//multiplication
begin

if(inp1[7]==1'b0 && inp2[7]==1'b0) // to see if both


are positive
begin
prod <= aaa * bbb;
prod15<=0;
end
else if(inp1[7]==1'b1 && inp2[7]==1'b0) // to see if any
one of them is negative
begin
prod <= bbb * aaa;
//cmp <= bbb >= aaa ? 1'b1 : 1'b0;
prod15<=1;
end
else if (inp1[7]==1'b0 && inp2[7]==1'b1)
begin
prod <= aaa * bbb;
//cmp <= aaa >= bbb ? 1'b1 : 1'b0;
prod15<=1;
end
else if (inp1[7]==1'b1 && inp2[7]==1'b1) // if both are
negative
begin
prod <= aaa * bbb;
prod15<=0; // output shoul
d be positive
end
prod[15]<=prod15;

assign out = prod;


if(out==16'b0000000000000000) //check for flags
zf<=1;
else
zf<=0;
pf<=~(^out);
if(out[7]==1)
begin
sf<=1;
end
else
sf<=0;
end
end
endmodule

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