Microchip AN1468 Peripheral Brief Programmable Switch Mode Controller
Microchip AN1468 Peripheral Brief Programmable Switch Mode Controller
PXCSRC<1:0> PXCPRE<1:0>
PSMCXCLK
psmc_clk y1,y2,
PSMCXTMR
64 MHZ y4, y8 CLR
FOSC
FFA PSMCXPR =
Period
Event
sync_out
sync_in
PSMCXPRS PSMCXPOL
PSMCXOEN
Rising
Event
PSMCXPH =
S PSMCXA
Output Control
PSMCXB
Mode Control
PSMCXPHS PSMCXC
Q
PSMCXD
PSMCXE
Falling
Event
PSMCXDC =
R PSMCXF
PSMCXDCS PXMODE
PSMCXSTR
Shutdown
Inputs
Period Event
Outputs
PWM Output
Inputs
Period Event
Outputs
PWM Output
Inputs
Period Event
Outputs
PWM Output
The first falling edge event in a cycle period is permitted to cause action in the PWM output signal, all other falling
edge events.
Inputs
Period Event
Outputs
PWM Output
A rising edge event that occurs after a falling edge event in the same cycle period is also suppressed.
Inputs
Period Event
Outputs
PWM Output
If a falling edge event continues into the next cycle period, the rising edge event is suppressed until the next cycle period.
Time-Based Events signal for the given PWM cycle number period. For an
example of a PWM waveform generated with the
If your application requires a PWM output based on time-based event sources, see Figure 7.
very specific rising and falling edge events for a specific
period, that all three can be preloaded, then using
time-based event sources is the way to go. The
PSMCxTMR register (a 16-bit counter) is used as a tim-
ing reference for each PWM period. The counter starts
at 0000h and increments to FFFFh on the rising edge
of the PSMC clock signal. The PSMCxPR period regis-
ter is used to determine a period event referenced to
the 16-bit digital counter PSMCxTMR. A match
between the PSMCxTMR and the PSMCxPR registers
will generate a period event. For example; if PSMCxPR
= 0030h, PSMCxTMR will increment from 0000h to
0030h, then roll over to 0000h, and so on. Thus, each
set of 0030h counts will be one PWM cycle number or
one PWM output period. The PSMCxPH phase register
is used to determine a rising edge event referenced to
the 16-bit PSMCxTMR digital counter. A match
between the PSMCxTMR and the PSMCxPH register
values will generate a rising edge event. For example;
if PSMCxPH = 0002h, when the PSMCxTMR counter
increments to 0002h, a rising edge event will occur.
The PSMCxDC duty cycle register is used to determine
a synchronous falling edge event referenced to the
16-bit PSMCxTMR digital counter. A match between
the PSMCxTMR and the PSMCxDC register values will
generate a falling edge event. For example; if
PSMCxDC = 0028h, when the PSMCxTMR counter
increments to 0028h, a falling edge event will occur.
Also, to configure the PWM output for a zero percent
duty cycle operation, set PSMCxDC equal to
PSMCxPH. This will trigger a falling edge event simul-
taneously with the rising edge event, thus preventing
an output PWM signal. Likewise, with a 100% duty
cycle operation, set PSMCxDC greater than
PSMCxPR. This will prevent a falling edge event from
occurring, as the PSMCxDC value and the time base
counter value will never be equal. These rising and
falling edge events will determine the PWM output
Counter 0000h 0001h 0002h 0003h 0004h 0027h 0028h 0029h 0030h 0000h
PSMCxPR<15:0> 0030h
PSMCxPH<15:0> 0002h
PSMCxDC<15:0> 0028h
Inputs
Period Event
Period Event
PSMCxA
Period Event
PSMCxA
Primary Output Rising Edge Dead Band Rising Edge Dead Band
PSMCxB Falling Edge Dead Band Falling Edge Dead Band Falling Edge Dead Band
Complementary Output
Push-Pull PWM cycles. This mode does not use dead-band delay or
output steering control. The PWM outputs are only
The push-pull PWM is used to drive half and full-bridge available on two of the six output pins. See Figure 10
power supplies, as well as other synchronous drives. It for an example waveform of push-pull PWM operation.
uses at least two outputs and generates PWM signals
that alternate between the two outputs in even and odd
Period Event
B Output
PSMCxA
PSMCxB
Push-Pull PWM with Complementary PWM waveform outputs on four pins presented as two
Outputs pairs of two-output signals with a primary and comple-
mentary output in each pair. This mode of operation
The complementary push-pull PWM is used to drive uses dead-band delay control but not output steering
transistor bridge circuits, as well as synchronous control. See Figure 12 for an example waveform of
switches on the secondary side of the bridge. The push-pull PWM with complementary outputs operation.
Period Event
PSMCxA
Rising Edge Dead Band
PSMCxB
Push-Pull PWM with Four Full-Bridge delay or output PWM steering control and the output
Outputs signals are only available on four of the six output pins.
See Figure 12 for an example waveform of push-pull
The full-bridge push-pull PWM is used for DC to AC PWM with four full-bridge outputs operation.
inverters, Class D output drives and induction motor
drive systems. This mode does not utilize dead-band
Period Event
PSMCxA
PSMCxC
PSMCxB
PSMCxD
Push-Pull PWM with Four Full-Bridge and does use dead-band delay control and sends the
Complementary Outputs primary PWM outputs to four pins and the complemen-
tary outputs to the remaining two of the six output pins.
The push-pull PWM with four full-bridge and comple- See Figure 13 for an example waveform of push-pull
mentary outputs is used for DC to AC inverters, Class PWM with four full-bridge and complementary outputs
D output drives and induction motor drive systems. operation.
This mode does not utilize PWM steering control, but it
FIGURE 13: PUSH-PULL WITH 4 FULL-BRIDGE AND COMPLEMENTARY OUTPUTS PWM MODE
1 2 3
PWM Cycle Number
Period Event
PSMCxA
PSMCxC
Rising Edge Dead Band
Rising Edge Dead Band
PSMCxB
PSMCxD
Rising Edge Dead Band
PSMCxF Falling Edge Dead Band
Pulse-Skipping PWM synchronous rising edge event must occur within the
same single/multiple set of period events, otherwise no
The pulse-skipping PWM is used to generate a series output will be generated. This mode does not utilize
of fixed-length pulses that can be triggered at each dead-band delay or output steering control and the
period event. This type of PWM signal is useful for high output signal is limited to one output pin. See Figure 14
efficiency and Voltage mode boost converters. In order for an example waveform of pulse-skipping PWM.
for an output PWM signal to be asserted, an asynchro-
nous rising edge event must be active (1) and a
Asynchronous
Rising Edge Event
Synchronous
Falling Edge Event
PSMCxA
Asynchronous
Rising Edge Event
Synchronous
Falling Edge Event
PSMCxA
Falling Edge Dead Band
Rising Edge Dead Band
PSMCxB
ECCP Compatible Full-Bridge PWM PWM output signals needed to drive a full-bridge drive
circuit in the forward and reverse directions, see
This mode of operation is designed to match the Figure 16.
Full-Bridge mode from the ECCP module. It is called
ECCP compatible, because this mode replicates the
PxA (Active-High)
PxB (Active-High)
Pulse Width
PxC (Active-High)
PxD (Active-High)
Pulse Width
Note 1: The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle.
2: When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The modulated
PxB and PxD signals are inactive at this time. The length of this time is four Timer counts.
The Full-Bridge Compatible mode uses the same the forward and reverse direction changes. See
waveform events as the single-phase PWM mode to Figure 17 for an example waveform of ECCP
generate the output waveforms. There are both compatible full-bridge PWM.
Forward and Reverse modes available for this opera-
tion, again to match the ECCP implementation. This
mode utilizes dead-band delay control with respect to
PSMCxB
PSMCxA
Falling Edge Dead Band Rising Edge Dead Band
PSMCxC
PSMCxD
Forward Mode Reverse Mode
Variable Frequency Fixed Duty Cycle PWM Duty Cycle PWM. The Fractional Frequency Adjust
(FFA) is a method by which PWM resolution can be
This mode of operation is quite different from all of the improved on 50% fixed duty cycle signals. Higher
other modes. It uses only the period event for waveform resolution is achieved by altering the PWM period by a
generation. At each period event, the PWM output is single count for calculated intervals. This increased
toggled, producing a fixed duty cycle PWM signal. The resolution is based upon the PWM frequency averaged
rising edge and falling edge events are unused in this over a large number of PWM periods. So, after every
mode. This mode is useful for resonant converters and period event, the FFA adds the PSMCxFFA register
fluorescent dimming ballasts. The dead-band delay and value with the previously accumulated result. This
output steering controls are not utilized in this mode, addition causes an overflow and the period event time is
however, fractional frequency adjust can be used for increased by one. See Figure 19 for a simplified block
making fine period timing adjustments. See Figure 18 diagram of the fraction frequency adjust.
for an example waveform of Variable Frequency Fixed
PSMCxA
FIGURE 19: SIMPLIFIED BLOCK DIAGRAM OF THE FRACTIONAL FREQUENCY ADJUST (FFA)
PSMCxFFA<3:0> PSMCxPR<15:0>
6 6
carry
Accumulator<3:0> Comparator = Period Event
psmc_clk PSMCxTMR<15:0>
FIGURE 20: VARIABLE FREQUENCY FIXED DUTY CYCLE WITH COMPLEMENTARY PWM
MODE
1 2 3 4 5 6 7 8 9 10 11 12
PWM Cycle Number
Period Event
PSMCxA
PSMCxB
3-Phase PWM
The 3-Phase mode of operation is used in 3-phase
power supply and motor drive applications configured
half-bridges, see Figure 21.
A half-bridge configuration consists of two power driver outputs consist of a high-side driver and low-side driver
devices in series, between the positive power rail (high output. Now, in order for the motor to rotate forward, the
side) and negative power rail (low side). The three PSMC steering control register values are selected.
outputs come from the junctions between the two The timing speed at which these values are selected
drivers in each half-bridge. When the steering control will determine the speed of the motor, likewise when
selects a phase drive, power flows from the positive rail the PSMC steering register values are selected in
through a high-side power device to the load and back reverse. See Figure 22 for an example waveform of
to the power supply through a low-side power device. 3-phase PWM.
In this mode of operation, all six PSMC outputs are
used, but only two are active at a time. The two active
PSMCxA (1H)
PSMCxB (1L)
PSMCxC (2H)
PSMCxD (2L)
PSMCxE (3H)
PSMCxE (3L)
PSMC Modulation
PSMC modulation is a method to stop/start PWM
operation of the PSMC without having to disable the
module. It also allows other modules to control the
operational period of the PSMC. This is also referred to
as Burst mode. This is a method to implement PWM
dimming for use in LED lighting, and for start-up and
shutdown in power supply design.
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