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Microchip AN1468 Peripheral Brief Programmable Switch Mode Controller

Peripheral Brief: Programmable Switch Mode Controller Microchip PSMC Module

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0% found this document useful (0 votes)
136 views16 pages

Microchip AN1468 Peripheral Brief Programmable Switch Mode Controller

Peripheral Brief: Programmable Switch Mode Controller Microchip PSMC Module

Uploaded by

Roland Szand
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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AN1468

Peripheral Brief: Programmable Switch Mode Controller


(PSMC)
designed to meet a need to intelligently and efficiently
Author: John Mouton drive the MOSFET switching of various Switch Mode
Microchip Technology Inc. Power Supplies, lighting, and motor drive applications.
Basically, it is a PWM Swiss army knife that gives you 12
different modes of PWM generation, and the flexibility to
INTRODUCTION be used with other on-board peripherals to solve or
This peripheral brief reviews the basic functionality of update real world applications. The PIC16(LF)F178X
the Programmable Switch Mode Controller (PSMC), as family of devices are the first PIC microcontrollers
well as discusses which PIC MCUs have this introduced with the PSMC module, which are also
peripheral, and some suggested applications examples equipped with advanced analog peripherals, such as
utilizing this peripheral. 12-bit ADCs, high-speed comparators, operational
amplifiers, 8-bit DACs, capture/compare/PWMs, Fixed
Voltage Reference, multiple timers, I2C/SPI/EUSART
WHAT IS THE PSMC? communications, debug capability, and low-power
The Programmable Switch Mode Controller (PSMC) is a features. Refer to the PIC16(L)F1782/3 product page at
high-performance 16-bit pulse-width modulator (PWM), www.microchip.com, and the product data sheet
that can be configured to operate in one of many modes (DS41579) for more details and information.
to support single or multiple phase applications. It was

FIGURE 1: PSMC SIMPLIFIED BLOCK DIAGRAM

PXCSRC<1:0> PXCPRE<1:0>
PSMCXCLK
psmc_clk y1,y2,
PSMCXTMR
64 MHZ y4, y8 CLR
FOSC

FFA PSMCXPR =
Period
Event

sync_out
sync_in

PSMCXPRS PSMCXPOL
PSMCXOEN
Rising
Event

PSMCXPH =
S PSMCXA
Output Control

PSMCXB
Mode Control

PSMCXPHS PSMCXC
Q
PSMCXD
PSMCXE
Falling
Event

PSMCXDC =
R PSMCXF

PSMCXDCS PXMODE
PSMCXSTR
Shutdown

Blanking PSMCXREBS PSMCXASDS


PSMCXFEBS
C1OUT
C2OUT
C3OUT
PSMCXIN
CCP1
CCP2
PSMCXMDL

2012 Microchip Technology Inc. DS01468A-page 1


AN1468

FUNDAMENTAL OPERATION the period are suppressed, thereby preventing output


chatter from spurious inputs (see Figure 3 and
Figure 4).
Blanking
The inputs to the PSMC can be selected from: the Rising Edge Event
on-board high-speed comparator outputs (CxOUT), an
external input pin (PSMCxIN), or the output of the The rising edge event determines the start of the output
on-board CCP (capture/compare/PWM) modules can pulse. Depending on the PSMC mode, one or more of
be used for PSMC modulation, which will be discussed the PSMC outputs will change in immediate response
later. The inputs from the comparators or the external to the rising edge event (see Figure 2). A rising edge
input pin can then go through an input blanking control. event that occurs after a falling edge event within the
Input blanking is a function whereby the inputs (PSMC same period is suppressed, resulting in no PWM output
input pin and/or any of the comparator outputs) may be signal (see Figure 5).
driven inactive for a short period of time. This is to
prevent electrical transients, from the turning on and/or Falling Edge Event
off of power components, from generating a false
The falling edge event determines the end of the output
event.
pulse. The falling edge event is also referred to as the
duty cycle, because varying the falling edge event,
Inputs while keeping the rising edge event and period events
After blanking control, the input signals will then go to fixed, varies the active drive duty cycle. Depending on
the core of the PSMC, where the fundamental opera- the PSMC mode, one or more of the PSMC outputs will
tion begins. Here, the PSMC operates based on a change in immediate response to the falling edge event
sequence of three events; the Period Event, the Rising (see Figure 2). If a falling edge event continues on into
Edge Event, and the Falling Edge Event. Each of these the next cycle period, the rising edge event of that next
three events are triggered by the user selecting a com- cycle period is suppressed, resulting in no PWM output
bination of external inputs (comparator outputs and signal for that cycle period (see Figure 6).
PSMC input pin), or time-based counter inputs derived
from an internal clock (PSMCxPR, PSMCxPH, Clock Selection
PSMCxDC, and PSMCxTMR registers) see Figure 1.
The PSMC module is clocked from one of three options;
an external clock pin, 64 MHz, or the system oscillator
Period Event frequency (FOSC). An external clock source can range
The period event determines the frequency of the out- from 32 kHz to 20 MHz, depending on the crystal used,
put pulse, which of its sources include any combination independently from the oscillator selection of the micro-
of the PSMC timer/counter match, PSMC input pin, controller CPU. Using the 64 MHz clock option, the user
and/or any of the comparator outputs (see Figure 2). can have the PSMC running at 64 MHz, while the rest of
During a period, the rising edge event and falling edge the microcontroller is running at 32 kHz, thus allowing
event are each permitted to occur only once. Subse- the CPU to run in a lower power mode while the PSMC
quent rising or falling edge events that may occur within runs at a much faster speed. As a final option, the user
can setup the PSMC to run at the same clock speed as
the CPU. See Figure 1 for a PSMC Simplified Block
Diagram.

FIGURE 2: BASIC PWM WAVEFORM GENERATION


PWM Cycle Number 1 2 3

Inputs

Period Event

Rising Edge Event

Falling Edge Event

Outputs

PWM Output

DS01468A-page 2 2012 Microchip Technology Inc.


AN1468

FIGURE 3: SUBSEQUENT RISING EDGE EVENT WAVEFORM


1 2 3
PWM Cycle Number

Inputs
Period Event

Rising Edge Event

Falling Edge Event

Outputs
PWM Output

FIGURE 4: SUBSEQUENT FALLING EDGE EVENT WAVEFORM


1 2 3
PWM Cycle Number

Inputs
Period Event

Rising Edge Event

Falling Edge Event

Outputs
PWM Output

The first falling edge event in a cycle period is permitted to cause action in the PWM output signal, all other falling
edge events.

FIGURE 5: RISING EDGE EVENT AFTER A FALLING EDGE EVENT


1 2 3
PWM Cycle Number

Inputs
Period Event

Rising Edge Event

Falling Edge Event

Outputs
PWM Output

A rising edge event that occurs after a falling edge event in the same cycle period is also suppressed.

2012 Microchip Technology Inc. DS01468A-page 3


AN1468

FIGURE 6: FALLING EDGE EVENT COVERING MULTIPLE CYCLE PERIODS


1 2 3
PWM Cycle Number

Inputs
Period Event

Rising Edge Event

Falling Edge Event

Outputs
PWM Output

If a falling edge event continues into the next cycle period, the rising edge event is suppressed until the next cycle period.

Time-Based Events signal for the given PWM cycle number period. For an
example of a PWM waveform generated with the
If your application requires a PWM output based on time-based event sources, see Figure 7.
very specific rising and falling edge events for a specific
period, that all three can be preloaded, then using
time-based event sources is the way to go. The
PSMCxTMR register (a 16-bit counter) is used as a tim-
ing reference for each PWM period. The counter starts
at 0000h and increments to FFFFh on the rising edge
of the PSMC clock signal. The PSMCxPR period regis-
ter is used to determine a period event referenced to
the 16-bit digital counter PSMCxTMR. A match
between the PSMCxTMR and the PSMCxPR registers
will generate a period event. For example; if PSMCxPR
= 0030h, PSMCxTMR will increment from 0000h to
0030h, then roll over to 0000h, and so on. Thus, each
set of 0030h counts will be one PWM cycle number or
one PWM output period. The PSMCxPH phase register
is used to determine a rising edge event referenced to
the 16-bit PSMCxTMR digital counter. A match
between the PSMCxTMR and the PSMCxPH register
values will generate a rising edge event. For example;
if PSMCxPH = 0002h, when the PSMCxTMR counter
increments to 0002h, a rising edge event will occur.
The PSMCxDC duty cycle register is used to determine
a synchronous falling edge event referenced to the
16-bit PSMCxTMR digital counter. A match between
the PSMCxTMR and the PSMCxDC register values will
generate a falling edge event. For example; if
PSMCxDC = 0028h, when the PSMCxTMR counter
increments to 0028h, a falling edge event will occur.
Also, to configure the PWM output for a zero percent
duty cycle operation, set PSMCxDC equal to
PSMCxPH. This will trigger a falling edge event simul-
taneously with the rising edge event, thus preventing
an output PWM signal. Likewise, with a 100% duty
cycle operation, set PSMCxDC greater than
PSMCxPR. This will prevent a falling edge event from
occurring, as the PSMCxDC value and the time base
counter value will never be equal. These rising and
falling edge events will determine the PWM output

DS01468A-page 4 2012 Microchip Technology Inc.


AN1468

FIGURE 7: BASIC PWM WAVEFORM GENERATED BY TIME-BASED EVENT SOURCES


1
PWM Cycle Number
PSMC clock

Counter 0000h 0001h 0002h 0003h 0004h 0027h 0028h 0029h 0030h 0000h

PSMCxPR<15:0> 0030h

PSMCxPH<15:0> 0002h

PSMCxDC<15:0> 0028h

Inputs
Period Event

Rising Edge Event

Falling Edge Event


Outputs
PWM Output

2012 Microchip Technology Inc. DS01468A-page 5


AN1468

MODES OF OPERATION type of MOSFET switching application available, from


Switch Mode Power Supplies to lighting or motor
After the rising and falling edge events are logically control. Because this peripheral can be used for so
combined, via an SR latch, various output PWM pulse many applications, a short summary table with a
signals are produced based on the mode of operation complete list of modes with features and application
selected. Here the user can select one of 12 modes, examples for each of the 12 different PSMC modes of
each with its own set of features, to drive almost any operation is shown in Table 1.

TABLE 1: PSMC MODES OF OPERATION


Fractional
Dead-Band PWM Primary Complementary
Modes of Operation Freq. Adjust Application Examples
Delay Steering Outputs Outputs
(FFA)
A,B,C,D,E, - Stepper motor
Single Phase PWM No Yes No
F control
- Brushed DC
Complementary PWM Yes Yes A,C,E B,D,F No motor control
- Power supplies
Push-Pull PWM No No A,B No
- Half and full
bridge power
Push-Pull PWM w/ supplies
Yes No A,E B,F No
Complementary Outputs - Synchronous
drives
Push-Pull PWM w/4
No No A,B,C,D No - DC to AC
Full-Bridge Outputs
inverters
Push-Pull PWM w/4 - Class-D output
Full-Bridge and Yes No A,B,C,D E,F No drives
Complementary Outputs - Induction motor
drives
Pulse Skipping PWM No No A No - High efficiency
boost converters
Pulse Skipping PWM w/ - Voltage mode
Yes No A B No
Complementary Outputs
boost controllers
ECCP Compatible Yes (Forward - Brushed DC
No A,B,C,D No
Full-Bridge PWM and Reverse) motor control
- Resonant
Variable Freq. Fixed converters
No No A Yes
Duty Cycle PWM - Fluorescent
dimming ballasts
- Resonant power
Variable Freq. Fixed supplies
Duty Cycle PWM w/ Yes No A,C,E B,D,F Yes - Induction motor
Complementary Outputs drives with speed
control
A and D
A and F
- 3-Phase BLDC
C and F
3-Phase PWM No Yes No motors
C and B
- AC inverters
E and B
E and D

DS01468A-page 6 2012 Microchip Technology Inc.


AN1468

Single-Phase PWM events) to generate the waveform. This mode of oper-


ation does not have dead-band delay control, but the
The single-phase PWM is the most basic of all the PWM output can be steered to any combination of the
waveforms generated by the PSMC module. Common six output pins. See Figure 8 for an example waveform
application examples are motor control and power of single-phase PWM operation.
supply drivers. It consists of a single output that uses all
three events (rising edge, falling edge and period

FIGURE 8: SINGLE-PHASE PWM MODE


1 2 3
PWM Cycle Number

Period Event

Rising Edge Event

Falling Edge Event

PSMCxA

Complementary PWM switches. Dead-band control is available only in modes


with complementary waveform capability. The module
The complementary PWM uses the same event contains independent 8-bit dead-band counters for
sources as the single phase PWM, but two waveforms rising edge and falling edge dead-band control. The
are generated instead of only one. The two waveforms PWM outputs can be steered to three primary PWM
are opposite in polarity to each other, thus one is the output pins and three complementary output pins. See
complement of the other. The two waveforms will also Figure 9 for an example waveform of complementary
have dead-band control as well. The dead-band control PWM operation.
provides non-overlapping PWM signals to prevent
shoot-through current in series connected power

FIGURE 9: COMPLEMENTARY PWM MODE


1 2 3
PWM Cycle Number

Period Event

Rising Edge Event

Falling Edge Event

PSMCxA
Primary Output Rising Edge Dead Band Rising Edge Dead Band

PSMCxB Falling Edge Dead Band Falling Edge Dead Band Falling Edge Dead Band
Complementary Output

2012 Microchip Technology Inc. DS01468A-page 7


AN1468

Push-Pull PWM cycles. This mode does not use dead-band delay or
output steering control. The PWM outputs are only
The push-pull PWM is used to drive half and full-bridge available on two of the six output pins. See Figure 10
power supplies, as well as other synchronous drives. It for an example waveform of push-pull PWM operation.
uses at least two outputs and generates PWM signals
that alternate between the two outputs in even and odd

FIGURE 10: PUSH-PULL PWM MODE


11 22 3 3
PWM Cycle Number
A Output A Output

Period Event

B Output

Rising Edge Event

Falling Edge Event

PSMCxA

PSMCxB

Push-Pull PWM with Complementary PWM waveform outputs on four pins presented as two
Outputs pairs of two-output signals with a primary and comple-
mentary output in each pair. This mode of operation
The complementary push-pull PWM is used to drive uses dead-band delay control but not output steering
transistor bridge circuits, as well as synchronous control. See Figure 12 for an example waveform of
switches on the secondary side of the bridge. The push-pull PWM with complementary outputs operation.

FIGURE 11: PUSH-PULL WITH COMPLEMENTARY OUTPUTS PWM MODE


1 2 3
PWM Cycle Number

Period Event

Rising Edge Event

Falling Edge Event

PSMCxA
Rising Edge Dead Band

PSMCxE Falling Edge Dead Band Falling Edge Dead Band

PSMCxB

PSMCxF Rising Edge Dead Band


Falling Edge Dead Band

DS01468A-page 8 2012 Microchip Technology Inc.


AN1468

Push-Pull PWM with Four Full-Bridge delay or output PWM steering control and the output
Outputs signals are only available on four of the six output pins.
See Figure 12 for an example waveform of push-pull
The full-bridge push-pull PWM is used for DC to AC PWM with four full-bridge outputs operation.
inverters, Class D output drives and induction motor
drive systems. This mode does not utilize dead-band

FIGURE 12: PUSH-PULL WITH 4 FULL-BRIDGE OUTPUTS PWM MODE


1 2 3
PWM Cycle Number

Period Event

Rising Edge Event

Falling Edge Event

PSMCxA

PSMCxC

PSMCxB

PSMCxD

2012 Microchip Technology Inc. DS01468A-page 9


AN1468

Push-Pull PWM with Four Full-Bridge and does use dead-band delay control and sends the
Complementary Outputs primary PWM outputs to four pins and the complemen-
tary outputs to the remaining two of the six output pins.
The push-pull PWM with four full-bridge and comple- See Figure 13 for an example waveform of push-pull
mentary outputs is used for DC to AC inverters, Class PWM with four full-bridge and complementary outputs
D output drives and induction motor drive systems. operation.
This mode does not utilize PWM steering control, but it

FIGURE 13: PUSH-PULL WITH 4 FULL-BRIDGE AND COMPLEMENTARY OUTPUTS PWM MODE
1 2 3
PWM Cycle Number

Period Event

Rising Edge Event

Falling Edge Event

PSMCxA

PSMCxC
Rising Edge Dead Band
Rising Edge Dead Band

PSMCxE Falling Edge Dead Band Falling Edge Dead Band

PSMCxB

PSMCxD
Rising Edge Dead Band
PSMCxF Falling Edge Dead Band

Pulse-Skipping PWM synchronous rising edge event must occur within the
same single/multiple set of period events, otherwise no
The pulse-skipping PWM is used to generate a series output will be generated. This mode does not utilize
of fixed-length pulses that can be triggered at each dead-band delay or output steering control and the
period event. This type of PWM signal is useful for high output signal is limited to one output pin. See Figure 14
efficiency and Voltage mode boost converters. In order for an example waveform of pulse-skipping PWM.
for an output PWM signal to be asserted, an asynchro-
nous rising edge event must be active (1) and a

FIGURE 14: PULSE-SKIPPING PWM MODE


1 2 3 4 5 6 7 8 9 10 11 12
PWM Cycle Number
Period Event

Asynchronous
Rising Edge Event

Synchronous
Falling Edge Event

Falling Edge Event

PSMCxA

DS01468A-page 10 2012 Microchip Technology Inc.


AN1468

Pulse-Skipping PWM with dead-band delay control and the complementary


Complementary Output output is available on a separate output pin. See
Figure 15 for an example waveform of pulse-skipping
This Pulse-Skipping mode works exactly the same as with complementary output PWM.
the last mode, with one exception: a complementary
output signal is generated. Thus, this mode utilizes

FIGURE 15: PULSE-SKIPPING PWM MODE


1 2 3 4 5 6 7 8 9 10 11 12
PWM Cycle Number
Period Event

Asynchronous
Rising Edge Event

Synchronous
Falling Edge Event

Falling Edge Event

PSMCxA
Falling Edge Dead Band
Rising Edge Dead Band
PSMCxB

ECCP Compatible Full-Bridge PWM PWM output signals needed to drive a full-bridge drive
circuit in the forward and reverse directions, see
This mode of operation is designed to match the Figure 16.
Full-Bridge mode from the ECCP module. It is called
ECCP compatible, because this mode replicates the

FIGURE 16: EXAMPLE OF PWM DIRECTION CHANGE

Signal Period(1) Period

PxA (Active-High)

PxB (Active-High)
Pulse Width

PxC (Active-High)

PxD (Active-High)

Pulse Width

Note 1: The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle.
2: When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The modulated
PxB and PxD signals are inactive at this time. The length of this time is four Timer counts.

The Full-Bridge Compatible mode uses the same the forward and reverse direction changes. See
waveform events as the single-phase PWM mode to Figure 17 for an example waveform of ECCP
generate the output waveforms. There are both compatible full-bridge PWM.
Forward and Reverse modes available for this opera-
tion, again to match the ECCP implementation. This
mode utilizes dead-band delay control with respect to

2012 Microchip Technology Inc. DS01468A-page 11


AN1468

FIGURE 17: ECCP COMPATIBLE FULL-BRIDGE PWM MODE


1 2 3 4 5 6 7 8 9 10 11 12
PWM Cycle Number
Period Event

Rising Edge Event

Falling Edge Event


PSMCxA

PSMCxB

PSMCxA
Falling Edge Dead Band Rising Edge Dead Band
PSMCxC

PSMCxD
Forward Mode Reverse Mode

Variable Frequency Fixed Duty Cycle PWM Duty Cycle PWM. The Fractional Frequency Adjust
(FFA) is a method by which PWM resolution can be
This mode of operation is quite different from all of the improved on 50% fixed duty cycle signals. Higher
other modes. It uses only the period event for waveform resolution is achieved by altering the PWM period by a
generation. At each period event, the PWM output is single count for calculated intervals. This increased
toggled, producing a fixed duty cycle PWM signal. The resolution is based upon the PWM frequency averaged
rising edge and falling edge events are unused in this over a large number of PWM periods. So, after every
mode. This mode is useful for resonant converters and period event, the FFA adds the PSMCxFFA register
fluorescent dimming ballasts. The dead-band delay and value with the previously accumulated result. This
output steering controls are not utilized in this mode, addition causes an overflow and the period event time is
however, fractional frequency adjust can be used for increased by one. See Figure 19 for a simplified block
making fine period timing adjustments. See Figure 18 diagram of the fraction frequency adjust.
for an example waveform of Variable Frequency Fixed

FIGURE 18: VARIABLE FREQUENCY FIXED DUTY CYCLE PWM MODE


1 2 3 4 5 6 7 8 9 10 11 12
PWM Cycle Number
Period Event

Rising Edge Event Unused in this mode

Falling Edge Event Unused in this mode

PSMCxA

FIGURE 19: SIMPLIFIED BLOCK DIAGRAM OF THE FRACTIONAL FREQUENCY ADJUST (FFA)
PSMCxFFA<3:0> PSMCxPR<15:0>

6 6

carry
Accumulator<3:0> Comparator = Period Event

psmc_clk PSMCxTMR<15:0>

DS01468A-page 12 2012 Microchip Technology Inc.


AN1468

Variable Frequency Fixed Duty Cycle


PWM with Complementary Outputs
This mode is the same as the single output Fixed Duty
Cycle mode above, except a complementary output
with dead-band control is generated. See Figure 20 for
an example waveform of Variable Frequency Fixed
Duty Cycle with Complementary PWM.

FIGURE 20: VARIABLE FREQUENCY FIXED DUTY CYCLE WITH COMPLEMENTARY PWM
MODE
1 2 3 4 5 6 7 8 9 10 11 12
PWM Cycle Number
Period Event

Rising Edge Event Unused in this mode

Falling Edge Event Unused in this mode

PSMCxA

PSMCxB

3-Phase PWM
The 3-Phase mode of operation is used in 3-phase
power supply and motor drive applications configured
half-bridges, see Figure 21.

FIGURE 21: 3-PHASE DRIVE APPLICATION


PIC16F1783

A half-bridge configuration consists of two power driver outputs consist of a high-side driver and low-side driver
devices in series, between the positive power rail (high output. Now, in order for the motor to rotate forward, the
side) and negative power rail (low side). The three PSMC steering control register values are selected.
outputs come from the junctions between the two The timing speed at which these values are selected
drivers in each half-bridge. When the steering control will determine the speed of the motor, likewise when
selects a phase drive, power flows from the positive rail the PSMC steering register values are selected in
through a high-side power device to the load and back reverse. See Figure 22 for an example waveform of
to the power supply through a low-side power device. 3-phase PWM.
In this mode of operation, all six PSMC outputs are
used, but only two are active at a time. The two active

2012 Microchip Technology Inc. DS01468A-page 13


AN1468

FIGURE 22: 3-PHASE PWM MODE


0 1 2 3 4 5 6
3-Phase State
PSMC Steering
00h 01h 02h 04h 08h 10h 20h
Control Register
Period Event

Rising Edge Event

Falling Edge Event

PSMCxA (1H)

PSMCxB (1L)

PSMCxC (2H)

PSMCxD (2L)

PSMCxE (3H)

PSMCxE (3L)

OTHER PSMC FEATURES CONCLUSION


The Programmable Switch Mode Controller (PSMC) is
Auto-Shutdown a 16-bit PWM that is an ideal peripheral suited for
PSMC operation can be quickly terminated without power supply, lighting, and motor control applications,
software intervention by the auto-shutdown control. such as buck converters, boost converters, brushed
Auto-shutdown can be triggered by any combination of DC, brushless, 3-phase, etc. This peripheral brief
the comparator outputs, manually and/or externally to describes the basic function and modes of operation of
the microcontroller via an input pin. Auto-shutdown is a the PSMC, which can be applied to many real-world
method to immediately override the PSMC output applications. Currently, the PSMC peripheral is only
levels with specific overrides that allow for safe available on the PIC16(L)F1782 and PIC16(L)F1783
shutdown of the application. This feature also includes devices, however, stay tuned to www.microchip.com
a mechanism (auto-restart) to allow the application to for future devices that will have the PSMC on board.
restart under different conditions manually or automat- Finally, keep in mind that, in order to take advantage of
ically. all the benefits of this peripheral, the user must utilize
and/or optimize the other capabilities of the selected
PSMC Synchronization PIC MCU.

It is possible to synchronize the periods of two or more


PSMC modules together, provided that both modules
are on the same device. Synchronization is achieved
by sending a sync signal from the master PSMC mod-
ule to the desired slave modules. This sync signal gen-
erates a period event in each slave module, thereby
aligning all slaves with the master. This is useful when
an application requires different PWM signal genera-
tion from each module, but the waveforms must be
consistent within a PWM period.

PSMC Modulation
PSMC modulation is a method to stop/start PWM
operation of the PSMC without having to disable the
module. It also allows other modules to control the
operational period of the PSMC. This is also referred to
as Burst mode. This is a method to implement PWM
dimming for use in LED lighting, and for start-up and
shutdown in power supply design.

DS01468A-page 14 2012 Microchip Technology Inc.


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chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
suits, or expenses resulting from such use. No licenses are
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
conveyed, implicitly or otherwise, under any Microchip
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
intellectual property rights.
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
2012, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620766460

QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Companys quality system processes and procedures
are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping
== ISO/TS 16949 == devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchips quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

2012 Microchip Technology Inc. DS01468A-page 15


Worldwide Sales and Service
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Canada China - Xiamen
Tel: 905-673-0699 Tel: 86-592-2388138
Fax: 905-673-6509 Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
10/26/12
Fax: 86-756-3210049

DS01468A-page 16 2012 Microchip Technology Inc.

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