AD5933

1 MSPS, 12-Bit Impedance
Converter, Network Analyzer

Data Sheet AD5933
FEATURES GENERAL DESCRIPTION
Programmable output peak-to-peak excitation voltage The AD5933 is a high precision impedance converter system
to a maximum frequency of 100 kHz solution that combines an on-board frequency generator with
Programmable frequency sweep capability with a 12-bit, 1 MSPS, analog-to-digital converter (ADC). The
serial I2C interface frequency generator allows an external complex impedance to
Frequency resolution of 27 bits (<0.1 Hz) be excited with a known frequency. The response signal from
Impedance measurement range from 1 k to 10 M the impedance is sampled by the on-board ADC and a discrete
Capable of measuring of 100 to 1 k with additional Fourier transform (DFT) is processed by an on-board DSP
circuitry engine. The DFT algorithm returns a real (R) and imaginary (I)
Internal temperature sensor (2C) data-word at each output frequency.
Internal system clock option
Phase measurement capability Once calibrated, the magnitude of the impedance and relative
System accuracy of 0.5% phase of the impedance at each frequency point along the sweep
2.7 V to 5.5 V power supply operation is easily calculated. This is done off chip using the real and
Temperature range: 40C to +125C imaginary register contents, which can be read from the serial
16-lead SSOP package I2C interface.
Qualified for automotive applications A similar device, also available from Analog Devices, Inc., is the
AD5934, a 2.7 V to 5.5 V, 250 kSPS, 12-bit impedance converter,
APPLICATIONS
with an internal temperature sensor and is packaged in a 16-
Electrochemical analysis lead SSOP.
Bioelectrical impedance analysis
Impedance spectroscopy
Complex impedance measurement
Corrosion monitoring and protection equipment
Biomedical and automotive sensors
Proximity sensing
Nondestructive testing
Material property analysis
Fuel/battery cell condition monitoring
FUNCTIONAL BLOCK DIAGRAM

MCLK AVDD DVDD
DDS
CORE DAC
OSCILLATOR (27 BITS)
ROUT VOUT
SCL I2 C TEMPERATURE
INTERFACE SENSOR Z()
SDA
AD5933
REAL IMAGINARY RFB
REGISTER REGISTER
1024-POINT DFT
VIN
ADC GAIN
(12 BITS)
LPF
VDD/2
05324-001
AGND DGND
Figure 1.
Rev. E Document Feedback

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AD5933* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS DOCUMENTATION

View a parametric search of comparable parts. Application Notes
AN-1053: AD5933 Evaluation Board Example
EVALUATION KITS Measurement
AD5933 Evaluation Board AN-1252: How to Configure the AD5933/AD5934
AN-1389: Recommended Rework Procedure for the Lead
Frame Chip Scale Package (LFCSP)
AN-237: Choosing DACs for Direct Digital Synthesis
AN-280: Mixed Signal Circuit Technologies
AN-342: Analog Signal-Handling for High Speed and
Accuracy
AN-345: Grounding for Low-and-High-Frequency Circuits
AN-419: A Discrete, Low Phase Noise, 125 MHz Crystal
Oscillator for the AD9850
AN-423: Amplitude Modulation of the AD9850 Direct
Digital Synthesizer
AN-543: High Quality, All-Digital RF Frequency
Modulation Generation with the ADSP-2181 and the
AD9850 DDS
AN-557: An Experimenter's Project:
AN-587: Synchronizing Multiple AD9850/AD9851 DDS-
Based Synthesizers
AN-605: Synchronizing Multiple AD9852 DDS-Based
Synthesizers
AN-621: Programming the AD9832/AD9835
AN-632: Provisionary Data Rates Using the AD9951 DDS as
an Agile Reference Clock for the ADN2812 Continuous-
Rate CDR
AN-769: Generating Multiple Clock Outputs from the
AD9540
AN-772: A Design and Manufacturing Guide for the Lead
Frame Chip Scale Package (LFCSP)
AN-823: Direct Digital Synthesizers in Clocking
Applications Time
AN-837: DDS-Based Clock Jitter Performance vs. DAC
Reconstruction Filter Performance
AN-843: Measuring a Loudspeaker Impedance Profile
Using the AD5933
AN-847: Measuring a Grounded Impedance Profile Using
the AD5933
AN-851: A WiMax Double Downconversion IF Sampling
Receiver Design
AN-927: Determining if a Spur is Related to the DDS/DAC
REFERENCE MATERIALS
or to Some Other Source (For Example, Switching
Supplies) Technical Articles
AN-939: Super-Nyquist Operation of the AD9912 Yields a 400-MSample DDSs Run On Only +1.8 VDC
High RF Output Signal ADI Buys Korean Mobile TV Chip Maker
AN-953: Direct Digital Synthesis (DDS) with a Basics of Designing a Digital Radio Receiver (Radio 101)
Programmable Modulus
DDS Applications
Data Sheet
DDS Circuit Generates Precise PWM Waveforms
AD5933: 1 MSPS, 12-Bit Impedance Converter, Network
DDS Design
Analyzer Data Sheet
DDS Device Produces Sawtooth Waveform
Product Highlight
DDS Device Provides Amplitude Modulation
Impedance-to-Digital ConvertersCompact and Easy to
Use DDS IC Initiates Synchronized Signals
Introducing Digital Up/Down Converters: VersaCOMM DDS IC Plus Frequency-To-Voltage Converter Make Low-
Reconfigurable Digital Converters Cost DAC
User Guides DDS Simplifies Polar Modulation
UG-364: Evaluating the AD5933 1 MSPS, 12-Bit Impedance Digital Potentiometers Vary Amplitude In DDS Devices
Converter Network Analyzer Digital Up/Down Converters: VersaCOMM White Paper
Digital Waveform Generator Provides Flexible Frequency
SOFTWARE AND SYSTEMS REQUIREMENTS Tuning for Sensor Measurement
AD5933 - No-OS Driver for Microchip Microcontroller Improved DDS Devices Enable Advanced Comm Systems
Platforms Integrated DDS Chip Takes Steps To 2.7 GHz
AD5933 - No-OS Driver for Renesas Microcontroller Simple Circuit Controls Stepper Motors
Platforms
Speedy A/Ds Demand Stable Clocks
AD5933 IIO Impedance Converter and Network Analyzer
Synchronized Synthesizers Aid Multichannel Systems
Linux Driver
The Year of the Waveform Generator
AD5933 Software Evaluation
Two DDS ICs Implement Amplitude-shift Keying
AD5933 Pmod Xilinx FPGA Reference Design
Video Portables and Cameras Get HDMI Outputs
REFERENCE DESIGNS
CN0217
DESIGN RESOURCES
AD5933 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
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AD5933 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Register Map ................................................................................... 23
Applications ....................................................................................... 1 Control Register (Register Address 0x80, Register Address
General Description ......................................................................... 1 0x81)............................................................................................. 23
Functional Block Diagram .............................................................. 1 Start Frequency Register (Register Address 0x82, Register
Address 0x83, Register Address 0x84) .................................... 24
Revision History ............................................................................... 3
Frequency Increment Register (Register Address 0x85,
Specifications..................................................................................... 4 Register Address 0x86, Register Address 0x87) ..................... 25
I2C Serial Interface Timing Characteristics .............................. 6 Number of Increments Register (Register Address 0x88,
Absolute Maximum Ratings ............................................................ 7 Register Address 0x89) .............................................................. 25
ESD Caution .................................................................................. 7 Number of Settling Time Cycles Register (Register Address
Pin Configuration and Descriptions .............................................. 8 0x8A, Register Address 0x8B) ................................................. 25
Typical Performance Characteristics ............................................. 9 Status Register (Register Address 0x8F) .................................. 26
Terminology .................................................................................... 12 Temperature Data Register (16 BitsRegister Address 0x92,

Register Address 0x93) .............................................................. 26
System Description ......................................................................... 13
Real and Imaginary Data Registers (16 BitsRegister
Transmit Stage............................................................................. 14 Address 0x94, Register Address 0x95, Register Address 0x96,
Frequency Sweep Command Sequence ................................... 15 Register Address 0x97) .............................................................. 26
Receive Stage ............................................................................... 15 Serial Bus Interface ......................................................................... 27
DFT Operation ........................................................................... 15 General I2C Timing .................................................................... 27
System Clock ............................................................................... 16 Writing/Reading to the AD5933 .............................................. 28
Temperature Sensor ................................................................... 16 Block Write .................................................................................. 28
Temperature Conversion Details.............................................. 16 Read Operations ......................................................................... 29
Temperature Value Register ...................................................... 16 Typical Applications ....................................................................... 30
Temperature Conversion Formula ........................................... 16 Measuring Small Impedances ................................................... 30
Impedance Calculation .................................................................. 17 Biomedical: Noninvasive Blood Impedance Measurement .. 32
Magnitude Calculation .............................................................. 17 Sensor/Complex Impedance Measurement............................ 32
Gain Factor Calculation ............................................................ 17 Electro-Impedance Spectroscopy............................................. 33
Impedance Calculation Using Gain Factor ............................. 17 Layout and Configuration ............................................................. 34
Gain Factor Variation with Frequency .................................... 17 Power Supply Bypassing and Grounding ................................ 34
Two-Point Calibration ............................................................... 18 Evaluation Board ............................................................................ 35
Two-Point Gain Factor Calculation ......................................... 18 Using the Evaluation Board ...................................................... 35
Gain Factor Setup Configuration ............................................. 18 Prototyping Area ........................................................................ 35
Gain Factor Recalculation ......................................................... 18 Crystal Oscillator (XO) vs. External Clock ............................. 35
Gain Factor Temperature Variation ......................................... 19 Schematics ................................................................................... 36
Impedance Error......................................................................... 19 Outline Dimensions ....................................................................... 40
Measuring the Phase Across an Impedance ........................... 19 Ordering Guide .......................................................................... 40
Performing a Frequency Sweep .................................................... 22 Automotive Products ................................................................. 40
Rev. E | Page 2 of 40
Data Sheet AD5933
REVISION HISTORY
5/13Rev. D to Rev. E 2/10Rev. A to Rev. B
Added Automotive Information (Throughout) ............................ 1 Changes to General Description ..................................................... 1
Changed Sampling Rate from 250 kSPS to 1 MSPS ..................... 5 5/08Rev. 0 to Rev. A
Changes to Table 7 ..........................................................................21
Deleted Choosing a Reference for the AD5933 Section ............34 Changes to Layout .............................................................. Universal
Changes to Ordering Guide ...........................................................40 Changes to Figure 1 .......................................................................... 1
Changes to Table 1 ............................................................................ 4
12/11Rev. C to Rev. D Changes to Figure 17 ...................................................................... 13
Changes to Impedance Error Section ...........................................19 Changes to System Description Section....................................... 13
Removed Figure 26 and Figure 27; Changes to Figure 19 ...................................................................... 14
Renumbered Sequentially ..............................................................19 Changes to Figure 24 ...................................................................... 18
Removed Figure 28, Figure 29, Figure 30, Figure 31 ..................20 Changes to Impedance Error Section ........................................... 19
Changes to Figure 39 ......................................................................37 Added Measuring the Phase Across an Impedance Section ..... 21
Changes to Figure 40 ......................................................................38 Changes to Register Map Section ................................................. 24
Changes to Figure 41 ......................................................................39 Added Measuring Small Impedances Section ............................. 31
Changes to Figure 42 ......................................................................40 Changes to Table 18 ........................................................................ 35
8/10Rev. B to Rev. C Added Evaluation Board Section .................................................. 37
Changes to Ordering Guide ........................................................... 43
Changes to Impedance Error Section ...........................................19
Changes to Figure 45 ......................................................................38 9/05Revision 0: Initial Version
Changes to U4 Description in Table 19........................................42
AD5933 Data Sheet
SPECIFICATIONS
VDD = 3.3 V, MCLK = 16.776 MHz, 2 V p-p output excitation voltage @ 30 kHz, 200 k connected between Pin 5 and Pin 6; feedback
resistor = 200 k connected between Pin 4 and Pin 5; PGA gain = 1, unless otherwise noted.
Table 1.
Y Version 1
Parameter Min Typ Max Unit Test Conditions/Comments
SYSTEM
Impedance Range 1K 10 M 100 to 1 k requires extra buffer
circuitry, see the Measuring Small
Impedances section
Total System Accuracy 0.5 % 2 V p-p output excitation voltage at
30 kHz, 200 k connected between
Pin 5 and Pin 6
System Impedance Error Drift 30 ppm/C
TRANSMIT STAGE
Output Frequency Range 2 1 100 kHz
Output Frequency Resolution 0.1 Hz <0.1 Hz resolution achievable using
DDS techniques
MCLK Frequency 16.776 MHz Maximum system clock frequency
Internal Oscillator Frequency 3 16.776 MHz Frequency of internal clock
Internal Oscillator Temperature Coefficient 30 ppm/C
TRANSMIT OUTPUT VOLTAGE
Range 1
AC Output Excitation Voltage 4 1.98 V p-p See Figure 4 for output voltage
distribution
DC Bias 5 1.48 V DC bias of the ac excitation signal;
see Figure 5
DC Output Impedance 200 TA = 25C
Short-Circuit Current to Ground at VOUT 5.8 mA TA = 25C
Range 2
AC Output Excitation Voltage4 0.97 V p-p See Figure 6
DC Bias5 0.76 V DC bias of output excitation signal;
see Figure 7
DC Output Impedance 2.4 k
Short-Circuit Current to Ground at VOUT 0.25 mA
Range 3
DC Bias5 0.31 V DC bias of output excitation signal;
see Figure 9
DC Output Impedance 1 k
Range 4
DC Bias5 0.173 V DC bias of output excitation signal.
See Figure 11
DC Output Impedance 600
SYSTEM AC CHARACTERISTICS
Signal-to-Noise Ratio 60 dB
Total Harmonic Distortion 52 dB
Spurious-Free Dynamic Range
Wide Band (0 MHz to 1 MHz) 56 dB
Narrow Band (5 kHz) 85 dB
Data Sheet AD5933
Y Version 1
Parameter Min Typ Max Unit Test Conditions/Comments
RECEIVE STAGE
Input Leakage Current 1 nA To VIN pin
Input Capacitance 6 0.01 pF Pin capacitance between VIN and GND
Feedback Capacitance (CFB) 3 pF Feedback capacitance around current-
to-voltage amplifier; appears in
parallel with feedback resistor
ANALOG-TO-DIGITAL CONVERTER6
Resolution 12 Bits
Sampling Rate 1 MSPS ADC throughput rate
TEMPERATURE SENSOR
Accuracy 2.0 C 40C to +125C temperature range
Resolution 0.03 C
Temperature Conversion Time 800 s Conversion time of single temperature
measurement
LOGIC INPUTS
Input High Voltage (VIH) 0.7 VDD
Input Low Voltage (VIL) 0.3 VDD
Input Current 7 1 A TA = 25C
Input Capacitance 7 pF TA = 25C
POWER REQUIREMENTS
VDD 2.7 5.5 V
IDD (Normal Mode ) 10 15 mA VDD = 3.3 V
17 25 mA VDD = 5.5 V
IDD (Standby Mode) 11 mA VDD = 3.3 V; see the Control Register
(Register Address 0X80, Register
Address 0X81) section
16 mA VDD = 5.5 V
IDD (Power-Down Mode) 0.7 5 A VDD = 3.3 V
1 8 A VDD = 5.5 V
1
Temperature range for Y version = 40C to +125C, typical at 25C.
2
The lower limit of the output excitation frequency can be lowered by scaling the clock supplied to the AD5933.
3
Refer to Figure 14, Figure 15, and Figure 16 for the internal oscillator frequency distribution with temperature.
4
The peak-to-peak value of the ac output excitation voltage scales with supply voltage according to the following formula:
Output Excitation Voltage (V p-p) = [2/3.3] VDD
where VDD is the supply voltage.
5
The dc bias value of the output excitation voltage scales with supply voltage according to the following formula:
Output Excitation Bias Voltage (V) = [2/3.3] VDD
where VDD is the supply voltage.
6
Guaranteed by design or characterization, not production tested. Input capacitance at the VOUT pin is equal to pin capacitance divided by open-loop gain of current-
to-voltage amplifier.
7
The accumulation of the currents into Pin 8, Pin 15, and Pin 16.
AD5933 Data Sheet
I2C SERIAL INTERFACE TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.1
Table 2.
Parameter2 Limit at TMIN, TMAX Unit Description
fSCL 400 kHz max SCL clock frequency
t1 2.5 s min SCL cycle time
t2 0.6 s min tHIGH, SCL high time
t3 1.3 s min tLOW, SCL low time
t4 0.6 s min tHD, STA, start/repeated start condition hold time
t5 100 ns min tSU, DAT, data setup time
t63 0.9 s max tHD, DAT, data hold time
0 s min tHD, DAT, data hold time
t7 0.6 s min tSU, STA, setup time for repeated start
t8 0.6 s min tSU, STO, stop condition setup time
t9 1.3 s min tBUF, bus free time between a stop and a start condition
t10 300 ns max tF, rise time of SDA when transmitting
0 ns min tR, rise time of SCL and SDA when receiving (CMOS compatible)
t11 300 ns max tF, fall time of SCL and SDA when transmitting
0 ns min tF, fall time of SDA when receiving (CMOS compatible)
250 ns max tF, fall time of SDA when receiving
20 + 0.1 Cb4 ns min tF, fall time of SCL and SDA when transmitting
Cb 400 pF max Capacitive load for each bus line
1
See Figure 2.
2
Guaranteed by design and characterization, not production tested.
3
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH MIN of the SCL signal) to bridge the undefined falling edge of SCL.
4
Cb is the total capacitance of one bus line in picofarads. Note that tR and tF are measured between 0.3 VDD and 0.7 VDD.
SDA
t9 t3 t10 t11 t4
SCL
t4 t6 t2 t5 t7 t8
t1
05324-002
START REPEATED STOP

CONDITION START CONDITION
CONDITION
Figure 2. I2C Interface Timing Diagram
Data Sheet AD5933
ABSOLUTE MAXIMUM RATINGS

TA = 25C, unless otherwise noted.
Table 3. Stresses above those listed under Absolute Maximum Ratings

Parameter Rating may cause permanent damage to the device. This is a stress
DVDD to GND 0.3 V to +7.0 V rating only; functional operation of the device at these or any
AVDD1 to GND 0.3 V to +7.0 V other conditions above those indicated in the operational
AVDD2 to GND 0.3 V to +7.0 V section of this specification is not implied. Exposure to absolute
SDA/SCL to GND 0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect
VOUT to GND 0.3 V to VDD + 0.3 V device reliability.
VIN to GND 0.3 V to VDD + 0.3 V
MCLK to GND 0.3 V to VDD + 0.3 V ESD CAUTION
Operating Temperature Range
Extended Industrial (Y Grade) 40C to +125C
Storage Temperature Range 65C to +160C
Maximum Junction Temperature 150C
SSOP Package, Thermal Impedance
JA 139C/W
JC 136C/W
Reflow Soldering (Pb-Free)
Peak Temperature 260C
Time at Peak Temperature 10 sec to 40 sec
AD5933 Data Sheet
PIN CONFIGURATION AND DESCRIPTIONS

NC 1 16 SCL
NC 2 15 SDA
NC 3 14 AGND2
RFB 4 AD5933 13 AGND1
TOP VIEW
VIN 5 (Not to Scale) 12 DGND
VOUT 6 11 AVDD2
NC 7 10 AVDD1
MCLK 8 9 DVDD
NC = NO CONNECT
NOTES:
1. IT IS RECOMMENDED TO TIE ALL SUPPLY
CONNECTIONS (PIN 9, PIN 10, AND PIN 11)
AND RUN FROM A SINGLE SUPPLY BETWEEN
2.7V AND 5.5V. IT IS ALSO RECOMMENDED TO
05324-003
CONNECT ALL GROUND SIGNALS TOGETHER
(PIN 12, PIN 13, AND PIN 14).
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions

Pin No. Mnemonic Description
1, 2, 3, 7 NC No Connect.
4 RFB External Feedback Resistor. Connected from Pin 4 to Pin 5 and used to set the gain of the current-to-voltage
amplifier on the receive side.
5 VIN Input to Receive Transimpedance Amplifier. Presents a virtual earth voltage of VDD/2.
6 VOUT Excitation Voltage Signal Output.
8 MCLK The master clock for the system is supplied by the user.
9 DVDD Digital Supply Voltage.
10 AVDD1 Analog Supply Voltage 1.
11 AVDD2 Analog Supply Voltage 2.
12 DGND Digital Ground.
13 AGND1 Analog Ground 1.
14 AGND2 Analog Ground 2.
15 SDA I2C Data Input. Open-drain pins requiring 10 k pull-up resistors to VDD.
16 SCL I2C Clock Input. Open-drain pins requiring 10 k pull-up resistors to VDD.
Data Sheet AD5933
TYPICAL PERFORMANCE CHARACTERISTICS

35 30
MEAN = 1.9824 MEAN = 0.7543
SIGMA = 0.0072 SIGMA = 0.0099
30
25
25
NUMBER OF DEVICES
NUMBER OF DEVICES
20
20
15
15
10
10
5
5
0 0
05324-004
05324-007
1.92 1.94 1.96 1.98 2.00 2.02 2.04 2.06 0.68 0.70 0.72 0.74 0.76 0.78 0.80 0.82 0.84 0.86
VOLTAGE (V) VOLTAGE (V)
Figure 4. Range 1 Output Excitation Voltage Distribution, VDD = 3.3 V Figure 7. Range 2 DC Bias Distribution, VDD = 3.3 V
30 30
MEAN = 1.4807 MEAN = 0.3827
SIGMA = 0.0252 SIGMA = 0.00167
25 25
NUMBER OF DEVICES
NUMBER OF DEVICES
20 20
15 15
10 10
5 5
0 0
05324-005
05324-008
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 0.370 0.375 0.380 0.385 0.390 0.395 0.400
Figure 5. Range 1 DC Bias Distribution, VDD = 3.3 V Figure 8. Range 3 Output Excitation Voltage Distribution, VDD = 3.3 V
30 30
MEAN = 0.9862 MEAN = 0.3092
SIGMA = 0.0041 SIGMA = 0.0014
25 25
NUMBER OF DEVICES
NUMBER OF DEVICES
20 20
15 15
10 10
5 5
0 0
05324-006
05324-009
0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 0.290 0.295 0.300 0.305 0.310 0.315 0.320
Figure 6. Range 2 Output Excitation Voltage Distribution, VDD = 3.3 V Figure 9. Range 3 DC Bias Distribution, VDD = 3.3 V
AD5933 Data Sheet
30 15.8
MEAN = 0.1982 AVDD1, AVDD2, DVDD CONNECTED TOGETHER.
SIGMA = 0.0008 15.3 OUTPUT EXCITATION FREQUENCY = 30kHz
RFB, ZCALIBRATION = 100k
25
14.8
NUMBER OF DEVICES
14.3
20
13.8
IDD (mA)
15 13.3
12.8
10
12.3
11.8
5
11.3
0 10.8
05324-012
05324-010
0.192 0.194 0.196 0.198 0.200 0.202 0.204 0.206 0 2 4 6 8 10 12 14 16 18
VOLTAGE (V) MCLK FREQUENCY (MHz)
Figure 10. Range 4 Output Excitation Voltage Distribution, VDD = 3.3 V Figure 12. Typical Supply Current vs. MCLK Frequency
30 0.4
VDD = 3.3V
MEAN = 0.1792
TA = 25C
SIGMA = 0.0024
0.2 f = 32kHz
25
PHASE ERROR (Degrees)

0
NUMBER OF DEVICES
20
0.2
15
0.4
10
0.6
5 0.8
0 1.0
05324-013
05324-011
0.160 0.165 0.170 0.175 0.180 0.185 0.190 0.195 0.200 0.205 0 50 100 150 200 250 300 350 400
VOLTAGE (V) PHASE (Degrees)
Figure 11. Range 4 DC Bias Distribution, VDD = 3.3 V Figure 13. Typical Phase Error
Data Sheet AD5933
N = 106 12 N = 100
12 MEAN = 16.8292 MEAN = 16.7257
SD = 0.142904 SD = 0.137633
TEMP = 40C 10 TEMP = 125C
10
8
8
COUNT
COUNT
6
6
4
4
2 2
0 0
05324-016
05324-014
16.4 16.6 16.8 17.0 17.2 16.4 16.6 16.8 17.0 17.2
OSCILLATOR FREQUENCY (MHz) OSCILLATOR FREQUENCY (MHz)
Figure 14. Frequency Distribution of Internal Oscillator at 40C Figure 16. Frequency Distribution of Internal Oscillator at 125C
16 N = 100
MEAN = 16.7811
SD = 0.0881565
14
TEMP = 25C
12
10
COUNT
0
05324-015
16.4 16.6 16.8 17.0 17.2

OSCILLATOR FREQUENCY (MHz)
Figure 15. Frequency Distribution of Internal Oscillator at 25C
AD5933 Data Sheet
TERMINOLOGY
Total System Accuracy Signal-to-Noise Ratio (SNR)
The AD5933 can accurately measure a range of impedance SNR is the ratio of the rms value of the measured output signal
values to less than 0.5% of the correct impedance value for to the rms sum of all other spectral components below the
supply voltages between 2.7 V to 5.5 V. Nyquist frequency. The value for SNR is expressed in decibels.
Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion (THD)
Along with the frequency of interest, harmonics of the funda- THD is the ratio of the rms sum of harmonics to the funda-
mental frequency and images of these frequencies are present at mental, where V1 is the rms amplitude of the fundamental
the output of a DDS device. The spurious-free dynamic range and V2, V3, V4, V5, and V6 are the rms amplitudes of the
refers to the largest spur or harmonic present in the band of second through the sixth harmonics. For the AD5933, THD
interest. The wideband SFDR gives the magnitude of the largest is defined as
harmonic or spur relative to the magnitude of the fundamental
frequency in the 0 Hz to Nyquist bandwidth. The narrow-band V2 2 + V3 2 + V4 2 + V 5 2 V6 2
THD (dB) = 20 log
SFDR gives the attenuation of the largest spur or harmonic in a V1
bandwidth of 200 kHz, about the fundamental frequency.
Data Sheet AD5933
SYSTEM DESCRIPTION
MCLK
DDS
CORE DAC
OSCILLATOR (27 BITS)
ROUT VOUT
COS SIN
SCL
I2C TEMPERATURE
MICROCONTROLLER
INTERFACE SENSOR
SDA
Z()
REAL IMAGINARY
REGISTER REGISTER
AD5933
MAC CORE RFB

(1024 DFT)
PROGRAMMABLE
MCLK GAIN AMPLIFIER
WINDOWING
OF DATA VIN
ADC 5
(12 BITS) 1
LPF
05324-017
VDD/2
Figure 17. Block Overview
The AD5933 is a high precision impedance converter system The AD5933 permits the user to perform a frequency sweep with
solution that combines an on-board frequency generator with a a user-defined start frequency, frequency resolution, and number
12-bit, 1 MSPS ADC. The frequency generator allows an external of points in the sweep. In addition, the device allows the user to
complex impedance to be excited with a known frequency. The program the peak-to-peak value of the output sinusoidal signal as
response signal from the impedance is sampled by the on-board an excitation to the external unknown impedance connected
ADC and DFT processed by an on-board DSP engine. The DFT between the VOUT and VIN pins.
algorithm returns both a real (R) and imaginary (I) data-word at Table 5 gives the four possible output peak-to-peak voltages and
each frequency point along the sweep. The impedance magnitude the corresponding dc bias levels for each range for 3.3 V. These
and phase are easily calculated using the following equations: values are ratiometric with VDD. So for a 5 V supply
Magnitude = R 2 + I 2 5. 0
Output Excitation Voltage for Range 1 = 1.98 =3 V pp
3. 3
Phase = tan1(I/R)
5. 0
To characterize an impedance profile Z(), generally a frequency Output DC Bias Voltage for Range 1 = 1.48 = 2.24 V p p
3. 3
sweep is required, like that shown in Figure 18.
Table 5. Voltage Levels Respective Bias Levels for 3.3 V
Output Excitation
Range Voltage Amplitude Output DC Bias Level
1 1.98 V p-p 1.48 V
2 0.97 V p-p 0.76 V
IMPEDANCE
3 383 mV p-p 0.31 V

4 198 mV p-p 0.173 V
The excitation signal for the transmit stage is provided on-chip
using DDS techniques that permit subhertz resolution. The receive
stage receives the input signal current from the unknown impedance,
performs signal processing, and digitizes the result. The clock for
05324-018
the DDS is generated from either an external reference clock,

FREQUENCY which is provided by the user at MCLK, or by the internal
Figure 18. Impedance vs. Frequency Profile oscillator. The clock for the DDS is determined by the status of
Bit D3 in the control register (see Register Address 0x81 in the
Register Map section).
AD5933 Data Sheet
TRANSMIT STAGE Frequency Increment
As shown in Figure 19, the transmit stage of the AD5933 is made This is a 24-bit word that is programmed to the on-board RAM
up of a 27-bit phase accumulator DDS core that provides the at Register Address 0x85, Register Address 0x86, and Register
output excitation signal at a particular frequency. The input to Address 0x87 (see the Register Map). The required code loaded
the phase accumulator is taken from the contents of the start to the frequency increment register is the result of the formula
frequency register (see Register Address 0x82, Register Address shown in Equation 2, based on the master clock frequency and the
0x83, and Register Address 0x84). Although the phase accumu- required increment frequency output from the DDS.
lator offers 27 bits of resolution, the start frequency register has Frequency Increment Code =
the three most significant bits (MSBs) set to 0 internally; therefore,
the user has the ability to program only the lower 24 bits of the
quired Frequency Increment (2)
Re 2 27
start frequency register.
MCLK
R(GAIN)

4
PHASE
ACCUMULATOR DAC For example, if the user requires the sweep to have a resolution
05324-019
(27 BITS) VOUT
VBIAS of 10 Hz and has a 16 MHz clock signal connected to MCLK, the
code that needs to be programmed is given by
Figure 19. Transmit Stage
The AD5933 offers a frequency resolution programmable by the

user down to 0.1 Hz. The frequency resolution is programmed 10 Hz
Frequency Increment Code = 0x00014F
via a 24-bit word loaded serially over the I2C interface to the 16 MHz

frequency increment register. 4

The frequency sweep is fully described by the programming of The user programs the value of 0x00 to Register Address 0x85,
three parameters: the start frequency, the frequency increment, the value of 0x01 to Register Address 0x86, and the value of 0x4F
and the number of increments. to Register Address 0x87.
Start Frequency Number of Increments
This is a 24-bit word that is programmed to the on-board RAM This is a 9-bit word that represents the number of frequency
at Register Address 0x82, Register Address 0x83, and Register points in the sweep. The number is programmed to the on-board
Address 0x84 (see the Register Map section). The required code RAM at Register Address 0x88 and Register Address 0x89 (see the
loaded to the start frequency register is the result of the formula Register Map section). The maximum number of points that can
shown in Equation 1, based on the master clock frequency and the be programmed is 511.
required start frequency output from the DDS.
For example, if the sweep needs 150 points, the user programs
Start Frequency Code = the value of 0x00 to Register Address 0x88 and the value of 0x96
to Register Address 0x89.
Required Output Start Frequency (1)
2 27 Once the three parameter values have been programmed, the
MCLK sweep is initiated by issuing a start frequency sweep command to

4 the control register at Register Address 0x80 and Register Address
For example, if the user requires the sweep to begin at 30 kHz and 0x81 (see the Register Map section). Bit D2 in the status register
has a 16 MHz clock signal connected to MCLK, the code that (Register Address 0x8F) indicates the completion of the frequency
needs to be programmed is given by measurement for each sweep point. Incrementing to the next
frequency sweep point is under the control of the user. The
measured result is stored in the two register groups that follow:

30 kHz 27 0x94, 0x95 (real data) and 0x96, 0x97 (imaginary data) that should
Start Frequency Code = 2 0x0F5C28
16 MHz be read before issuing an increment frequency command to the

4 control register to move to the next sweep point. There is the

facility to repeat the current frequency point measurement by
The user programs the value of 0x0F to Register Address 0x82, the issuing a repeat frequency command to the control register. This
value of 0x5C to Register Address 0x83, and the value of 0x28 to has the benefit of allowing the user to average successive readings.
Register Address 0x84. When the frequency sweep has completed all frequency points,
Bit D3 in the status register is set, indicating completion of the
sweep. Once this bit is set, further increments are disabled.
Data Sheet AD5933
FREQUENCY SWEEP COMMAND SEQUENCE RECEIVE STAGE
The following sequence must be followed to implement a The receive stage comprises a current-to-voltage amplifier,
frequency sweep: followed by a programmable gain amplifier (PGA), antialiasing
1. Enter standby mode. Prior to issuing a start frequency sweep filter, and ADC. The receive stage schematic is shown in
command, the device must be placed in a standby mode by Figure 20. The unknown impedance is connected between the
issuing an enter standby mode command to the control VOUT and VIN pins. The first stage current-to-voltage amplifier
register (Register Address 0x80 and Register Address 0x81). configuration means that a voltage present at the VIN pin is a
In this mode, the VOUT and VIN pins are connected virtual ground with a dc value set at VDD/2. The signal current
internally to ground so there is no dc bias across the external that is developed across the unknown impedance flows into the
impedance or between the impedance and ground. VIN pin and develops a voltage signal at the output of the current-
2. Enter initialize mode. In general, high Q complex circuits to-voltage converter. The gain of the current-to voltage amplifier
require a long time to reach steady state. To facilitate the is determined by a user-selectable feedback resistor connected
measurement of such impedances, this mode allows the user between Pin 4 (RFB) and Pin 5 (VIN). It is important for the user
full control of the settling time requirement before entering to choose a feedback resistance value that, in conjunction with the
start frequency sweep mode where the impedance selected gain of the PGA stage, maintains the signal within the
measurement takes place. linear range of the ADC (0 V to VDD).
An initialize with a start frequency command to the control The PGA allows the user to gain the output of the current-to-
register enters initialize mode. In this mode the impedance voltage amplifier by a factor of 5 or 1, depending upon the status
is excited with the programmed start frequency, but no meas- of Bit D8 in the control register (see the Register Map section,
urement takes place. The user times out the required settling Register Address 0x80). The signal is then low-pass filtered and
time before issuing a start frequency sweep command to the presented to the input of the 12-bit, 1 MSPS ADC.
control register to enter the start frequency sweep mode. R RFB
3. Enter start frequency sweep mode. The user enters this mode 5R
C
by issuing a start frequency sweep command to the control
R
register. In this mode, the ADC starts measuring after the
programmed number of settling time cycles has elapsed. The VIN R
user can program an integer number of output frequency VDD/2 ADC
05324-020
LPF
cycles (settling time cycles) to Register Address 0x8A and
Register Address 0x8B before beginning the measurement Figure 20. Receive Stage
at each frequency point (see Figure 28).
The digital data from the ADC is passed directly to the DSP core
The DDS output signal is passed through a programmable gain of the AD5933, which performs a DFT on the sampled data.
stage to generate the four ranges of peak-to-peak output excitation
signals listed in Table 5. The peak-to-peak output excitation volt- DFT OPERATION
age is selected by setting Bit D10 and Bit D9 in the control register A DFT is calculated for each frequency point in the sweep. The
(see the Control Register (Register Address 0X80, Register AD5933 DFT algorithm is represented by
Address 0X81) section) and is made available at the VOUT pin. 1023
X( f ) = (x(n)(cos(n) j sin(n)))
n=0
where:
X(f) is the power in the signal at the Frequency Point f.
x(n) is the ADC output.
cos(n) and sin(n) are the sampled test vectors provided by the
DDS core at the Frequency Point f.
The multiplication is accumulated over 1024 samples for each
frequency point. The result is stored in two, 16-bit registers
representing the real and imaginary components of the result.
The data is stored in twos complement format.
AD5933 Data Sheet
SYSTEM CLOCK Table 6. Temperature Data Format
The system clock for the AD5933 can be provided in one of two Temperature Digital Output D13D0
ways. The user can provide a highly accurate and stable system 40C 11, 1011, 0000, 0000
clock at the external clock pin (MCLK). Alternatively, the AD5933 30C 11, 1100, 0100, 0000
provides an internal clock with a typical frequency of 16.776 MHz 25C 11, 1100, 1110, 0000
by means of an on-chip oscillator. 10C 11, 1110, 1100, 0000
0.03125C 11, 1111, 1111, 1111
The user can select the preferred system clock by programming
0C 00, 0000, 0000, 0000
Bit D3 in the control register (Register Address 0x81, see
+0.03125C 00, 0000, 0000, 0001
Table 11). The default clock option on power-up is selected to
+10C 00, 0001, 0100, 0000
be the internal oscillator.
+25C 00, 0011, 0010, 0000
The frequency distribution of the internal clock with temperature +50C 00, 0110, 0100, 0000
can be seen in Figure 14, Figure 15, and Figure 16. +75C 00, 1001, 0110, 0000
TEMPERATURE SENSOR +100C 00, 1100, 1000, 0000
+125C 00, 1111, 1010, 0000
The temperature sensor is a 13-bit digital temperature sensor with
+150C 01, 0010, 1100, 0000
a 14th bit that acts as a sign bit. The on-chip temperature sensor
allows an accurate measurement of the ambient device temper-
ature to be made. TEMPERATURE CONVERSION FORMULA
The measurement range of the sensor is 40C to +125C. At Positive Temperature = ADC Code (D)/32
+150C, the structural integrity of the device starts to deteriorate
Negative Temperature = (ADC Code (D) 16384)/32
when operated at voltage and temperature maximum specifica-
tions. The accuracy within the measurement range is 2C. where ADC Code uses all 14 bits of the data byte, including the
sign bit.
TEMPERATURE CONVERSION DETAILS
Negative Temperature = (ADC Code (D) 8192)/32
The conversion clock for the part is internally generated; no
external clock is required except when reading from and writing where ADC Code (D) is D13, the sign bit, and is removed from the
to the serial port. In normal mode, an internal clock oscillator ADC code.)
runs an automatic conversion sequence. 01, 0010, 1100, 0000
The temperature sensor block defaults to a power-down state.

To perform a measurement, a measure temperature command
DIGITAL OUTPUT
is issued by the user to the control register (Register Address 0x80

and Register Address 0x81). After the temperature operation is
complete (typically 800 s later), the block automatically 75C
00, 1001, 0110, 0000
powers down until the next temperature command is issued.
The user can poll the status register (Register Address 0x8F) to see
if a valid temperature conversion has taken place, indicating that
valid temperature data is available to read at Register Address 00, 0000, 0000, 0001
0x92 and Register Address 0x93 (see the Register Map section). 0.03125C
11, 1111, 1111, 1111 TEMPERATURE (C)
40C 150C
TEMPERATURE VALUE REGISTER
The temperature value register is a 16-bit, read-only register that 30C 11, 1100, 0100, 0000
stores the temperature reading from the ADC in 14-bit, twos

05324-021
complement format. The two MSB bits are dont cares. D13 is the
11, 1011, 0000, 0000
sign bit. The internal temperature sensor is guaranteed to a low
Figure 21. Temperature Sensor Transfer Function
value limit of 40C and a high value limit of +150C. The digital
output stored in Register Address 0x92 and Register Address 0x93
for the various temperatures is outlined in Table 6. The tempera-
ture sensor transfer characteristic is shown in Figure 21.
Data Sheet AD5933
IMPEDANCE CALCULATION
MAGNITUDE CALCULATION 1

200 k
The first step in impedance calculation for each frequency point Gain Factor = = 515.819 10 -12
9692.106
is to calculate the magnitude of the DFT at that point.
The DFT magnitude is given by
Magnitude = R 2 + I 2 IMPEDANCE CALCULATION USING GAIN FACTOR

The next example illustrates how the calculated gain factor
where: derived previously is used to measure an unknown impedance.
R is the real number stored at Register Address 0x94 and
For this example, assume that the unknown impedance = 510
Register Address 0x95.
k.
I is the imaginary number stored at Register Address 0x96 and
Register Address 0x97. After measuring the unknown impedance at a frequency of
30 kHz, assume that the real data and imaginary data registers
For example, assume the results in the real data and imaginary contain the following data:
data registers are as follows at a frequency point:
Real data register = 0xFA3F = 1473 decimal
Real data register = 0x038B = 907 decimal
Imaginary data register = 0x0DB3 = +3507 decimal
Imaginary data register = 0x0204 = 516 decimal
Magnitude = ((1473)2 + (3507)2 ) = 3802.863
Magnitude = (907 2 + 516 2 ) = 1043.506
Then the measured impedance at the frequency point is given
To convert this number into impedance, it must be multiplied
by
by
a scaling factor called the gain factor. The gain factor is 1
Impedance =
calculated during the calibration of the system with a known Gain Factor Magnitude
impedance connected between the VOUT and VIN pins. 1
= = 509.791 k
Once the gain factor has been calculated, it can be used in the 515.819273 10 12 3802.863
calculation of any unknown impedance between the VOUT and
VIN pins. GAIN FACTOR VARIATION WITH FREQUENCY
GAIN FACTOR CALCULATION Because the AD5933 has a finite frequency response, the gain
An example of a gain factor calculation follows, with the factor also shows a variation with frequency. This variation in
following assumptions: gain factor results in an error in the impedance calculation over
a frequency range. Figure 22 shows an impedance profile based
Output excitation voltage = 2 V p-p
on a single-point gain factor calculation. To minimize this error,
Calibration impedance value, ZCALIBRATION = 200 k the frequency sweep should be limited to as small a frequency
PGA Gain = 1 range as possible.
101.5
Current-to-voltage amplifier gain resistor = 200 k VDD = 3.3V
CALIBRATION FREQUENCY = 60kHz
Calibration frequency = 30 kHz 101.0 TA = 25C
MEASURED CALIBRATION IMPEDANCE = 100k
Then typical contents of the real data and imaginary data
registers after a frequency point conversion are: 100.5
IMPEDANCE (k)
Real data register = 0xF064 = 3996 decimal

100.0
Imaginary data register = 0x227E = +8830 decimal
99.5
Magnitude = (3996)2 + (8830)2 = 9692.106

99.0
1

Admittance Impedance
Gain Factor = = 98.5
05324-022
Code Magnitude 54 56 58 60 62 64 66
FREQUENCY (kHz)
Figure 22. Impedance Profile Using a Single-Point Gain Factor Calculation
AD5933 Data Sheet
TWO-POINT CALIBRATION GAIN FACTOR SETUP CONFIGURATION
Alternatively, it is possible to minimize this error by assuming When calculating the gain factor, it is important that the receive
that the frequency variation is linear and adjusting the gain stage operate in its linear region. This requires careful selection
factor with a two-point calibration. Figure 23 shows an of the excitation signal range, current-to-voltage gain resistor,
impedance profile based on a two-point gain factor calculation. and PGA gain.
101.5 CURRENT-TO-VOLTAGE
VDD = 3.3V GAIN SETTING RESISTOR
CALIBRATION FREQUENCY = 60kHz
101.0 TA = 25C RFB
ZUNKNOWN
100.5 VOUT
IMPEDANCE (k)
VIN ADC
05324-024
LPF
PGA
100.0 VDD/2 (1 OR 5)
Figure 24. System Voltage Gain

99.5
The gain through the system shown in Figure 24 is given by
99.0 Ouput Excitation Voltage Range
98.5 Gain Setting Re sistor

05324-023
54 56 58 60 62 64 66
PGA Gain
FREQUENCY (kHz) ZUNKNOWN
Figure 23. Impedance Profile Using a Two-Point Gain Factor Calculation
For this example, assume the following system settings:
TWO-POINT GAIN FACTOR CALCULATION VDD = 3.3 V
This is an example of a two-point gain factor calculation Gain setting resistor = 200 k
assuming the following:
Output excitation voltage = 2 V (p-p) ZUNKNOWN = 200 k
Calibration impedance value, ZUNKNOWN = 100.0 k PGA setting = 1
PGA gain = 1 The peak-to-peak voltage presented to the ADC input is

2 V p-p. However, if a PGA gain of 5 was chose, the voltage
Supply voltage = 3.3 V would saturate the ADC.
Current-to-voltage amplifier gain resistor = 100 k GAIN FACTOR RECALCULATION
Calibration frequencies = 55 kHz and 65 kHz The gain factor must be recalculated for a change in any of the
Typical values of the gain factor calculated at the two calibration following parameters:
frequencies read
Current-to-voltage gain setting resistor
Gain factor calculated at 55 kHz is 1.031224E-09 Output excitation voltage
Gain factor calculated at 65 kHz is 1.035682E-09 PGA gain
Difference in gain factor (GF) is 1.035682E-09
1.031224E-09 = 4.458000E-12
Frequency span of sweep (F) = 10 kHz
Therefore, the gain factor required at 60 kHz is given by
4.458000E - 12
5 kHz + 1.031224 10 -9
10 kHz

The required gain factor is 1.033453E-9.
The impedance is calculated as previously described.
Data Sheet AD5933
GAIN FACTOR TEMPERATURE VARIATION by calculating the magnitude of the real and imaginary compo-
The typical impedance error variation with temperature is in nents of the DFT given by the following formula:
the order of 30 ppm/C. Figure 25 shows an impedance profile Magnitude = R 2 + I 2
with a variation in temperature for 100 k impedance using a
two-point gain factor calibration. After each measurement, multiply it by the calibration term and
101.5 invert the product. The magnitude of the impedance is, therefore,
VDD = 3.3V
CALIBRATION FREQUENCY = 60kHz given by the following formula:
101.0
1
Impedance =
+125C Gain Factor Magnitude
100.5
IMPEDANCE (k)
Where gain factor is given by

100.0
1

+25C

Admittance Impedance
99.5
Gain Factor = =
40C
Code Magnitude
99.0
The user must calibrate the AD5933 system for a known
impedance range to determine the gain factor before any valid
98.5
measurement can take place. Therefore, the user must know the
05324-025
54 56 58 60 62 64 66
FREQUENCY (kHz) impedance limits of the complex impedance (ZUNKNOWN) for the
Figure 25. Impedance Profile Variation with Temperature Using a Two-Point sweep frequency range of interest. The gain factor is determined
Gain Factor Calibration by placing a known impedance between the input/output of the
IMPEDANCE ERROR AD5933 and measuring the resulting magnitude of the code.
The AD5933 system gain settings need to be chosen to place
It is important when reading the following section to note that
the excitation signal in the linear region of the on-board ADC.
the output impedance associated with the excitation voltages
was actually measured and then calibrated out for each Because the AD5933 returns a complex output code made up of
impedance error measurement. This was done using a Keithley real and imaginary components, the user can also calculate the
current source/sink and measuring the voltage. phase of the response signal through the AD5933 signal path.
The phase is given by the following formula:
ROUT (for example ,200 specified for a 1.98 V p-p in the
specification table) is only a typical specification and can vary Phase(rads) = tan1(I/R) (3)
from part to part. This method may not be achievable for large The phase measured by Equation 3 accounts for the phase shift
volume applications and in such cases, it is advised to use an introduced to the DDS output signal as it passes through the
extra low impedance output amplifier, as shown in Figure 4, to internal amplifiers on the transmit and receive side of the
improve accuracy. AD5933 along with the low-pass filter and also the impedance
Please refer to CN-0217 for impedance accuracy examples on connected between the VOUT and VIN pins of the AD5933.
the AD5933 product web-page. The parameters of interest for many users are the magnitude of
MEASURING THE PHASE ACROSS AN IMPEDANCE the impedance (|ZUNKNOWN|) and the impedance phase (Z).
The measurement of the impedance phase (Z) is a two step
The AD5933 returns a complex output code made up of sepa-
process.
rate real and imaginary components. The real component is
stored at Register Address 0x94 and Register Address 0x95 and The first step involves calculating the AD5933 system phase.
the imaginary component is stored at Register Address 0x96 The AD5933 system phase can be calculated by placing a
and Register Address 0x97 after each sweep measurement. resistor across the VOUT and VIN pins of the AD5933 and
These correspond to the real and imaginary components of calculating the phase (using Equation 3) after each measure-
the DFT and not the resistive and reactive components of the ment point in the sweep. By placing a resistor across the
impedance under test. VOUT and VIN pins, there is no additional phase lead or lag
introduced to the AD5933 signal path and the resulting phase
For example, it is a very common misconception to assume
is due entirely to the internal poles of the AD5933, that is, the
that if a user is analyzing a series RC circuit, the real value
system phase.
stored in Register Address 0x94 and Register Address 0x95
and the imaginary value stored at Register Address 0x96 Once the system phase has been calibrated using a resistor, the
and Register Address 0x97 correspond to the resistance and second step involves calculating the phase of any unknown
capacitive reactance, respectfully. However, this is incorrect impedance by inserting the unknown impedance between the
because the magnitude of the impedance (|Z|) can be calculated VIN and VOUT terminals of the AD5933 and recalculating the
AD5933 Data Sheet
new phase (including the phase due to the impedance) using The phase difference (that is, Z) between the phase response
the same formula. The phase of the unknown impedance (Z) of a capacitor and the system phase response using a resistor is
is given by the following formula: the impedance phase of the capacitor, Z (see Figure 27).
Z = ( unknown system) 100
90
where:
80
system is the phase of the system with a calibration resistor
connected between VIN and VOUT. 70
PHASE (Degrees)
unknown is the phase of the system with the unknown 60
impedance connected between VIN and VOUT. 50
Z is the phase due to the impedance, that is, the impedance 40

phase. 30
Note that it is possible to calculate the gain factor and to 20
calibrate the system phase using the same real and imaginary
10
component values when a resistor is connected between the
0
VOUT and VIN pins of the AD5933, for example, measuring
05324-033
0 15k 30k 45k 60k 75k 90k 105k 120k
the impedance phase (Z) of a capacitor. FREQUENCY (Hz)
Figure 27. Phase Response of a Capacitor

The excitation signal current leads the excitation signal voltage
across a capacitor by 90 degrees. Therefore, an approximate Also when using the real and imaginary values to interpret
90 degree phase difference exists between the system phase the phase at each measurement point, take care when using
responses measured with a resistor and that of the system phase the arctangent formula. The arctangent function returns the
responses measured with a capacitive impedance. correct standard phase angle only when the sign of the real and
imaginary values are positive, that is, when the coordinates lie
As previously outlined, if the user would like to determine the
phase angle of capacitive impedance (Z), the user first has to in the first quadrant. The standard angle is the angle taken
determine the system phase response ( system ) and subtract counterclockwise from the positive real x-axis. If the sign of the
this from the phase calculated with the capacitor connected real component is positive and the sign of the imaginary
between VOUT and VIN (unknown). component is negative, that is, the data lies in the second
quadrant, then the arctangent formula returns a negative angle
A plot showing the AD5933 system phase response calculated
and it is necessary to add a further 180 degrees to calculate the
using a 220 k calibration resistor (RFB = 220 k, PGA = 1)
correct standard angle. Likewise, when the real and imaginary
and the repeated phase measurement with a 10 pF capacitive
components are both negative, that is, when the coordinates lie
impedance is shown in Figure 26.
in the third quadrant, then the arctangent formula returns a
One important point to note about the phase formula used to positive angle and it is necessary to add 180 degrees from the
plot Figure 26 is that it uses the arctangent function that returns angle to return the correct standard phase. Finally, when the
a phase angle in radians and, therefore, it is necessary to convert real component is positive and the imaginary component is
from radians to degrees. negative, that is, the data lies in the fourth quadrant, then the
200 arctangent formula returns a negative angle. It is necessary to
180 add 360 degrees to the angle to calculate the correct phase
angle.
160 220k RESISTOR
Therefore, the correct standard phase angle is dependent upon
SYSTEM PHASE (Degrees)
140
120
the sign of the real and imaginary component and is summa-
rized in Table 7.
100
80
10pF CAPACITOR
60
40
20
0
05324-032
0 15k 30k 45k 60k 75k 90k 105k 120k

FREQUENCY (Hz)
Figure 26. System Phase Response vs. Capacitive Phase
Data Sheet AD5933
Once the magnitude of the impedance (|Z|) and the impedance Table 7. Phase Angle
phase angle (Z, in radians) are correctly calculated, it is possible Real Imaginary Quadrant Phase Angle
to determine the magnitude of the real (resistive) and imaginary Positive Positive First 180
(reactive) component of the impedance (ZUNKNOWN) by the tan 1 (I / R )

vector projection of the impedance magnitude onto the real Negative Positive Second 180
and imaginary impedance axis using the following formulas: 180 + tan 1 ( I / R )

The real component is given by Negative Negative Third 180
|ZREAL| = |Z| cos (Z) 180 + tan 1 ( I / R )

The imaginary component is given by Positive Negative Fourth 180
360 + tan 1 ( I / R )
|ZIMAG| = |Z| sin (Z)
AD5933 Data Sheet
PERFORMING A FREQUENCY SWEEP

PROGRAM FREQUENCY SWEEP PARAMETERS
INTO RELEVANT REGISTERS
(1) START FREQUENCY REGISTER
(2) NUMBER OF INCREMENTS REGISTER
(3) FREQUENCY INCREMENT REGISTER
PLACE THE AD5933 INTO STANDBY MODE.
RESET: BY ISSUING A RESET COMMAND TO

CONTROL REGISTER THE DEVICE IS PLACED
IN STANDBY MODE.
PROGRAM INITIALIZE WITH START

FREQUENCY COMMAND TO THE CONTROL
REGISTER.
AFTER A SUFFICIENT AMOUNT OF SETTLING

TIME HAS ELAPSED, PROGRAM START
FREQUENCY SWEEP COMMAND IN THE
CONTROL REGISTER.
POLL STATUS REGISTER TO CHECK IF

THE DFT CONVERSION IS COMPLETE.
N
Y
PROGRAM THE INCREMENT FREQUENCY OR

READ VALUES FROM REAL AND
THE REPEAT FREQUENCY COMMAND TO THE
IMAGINARY DATA REGISTER.
CONTROL REGISTER.
POLL STATUS REGISTER TO CHECK IF N

FREQUENCY SWEEP IS COMPLETE.
05324-034
PROGRAM THE AD5933
INTO POWER-DOWN MODE.
Figure 28. Frequency Sweep Flow Chart
Data Sheet AD5933
REGISTER MAP
Table 8.
Register Name Register Data Function
0x80 Control D15 to D8 Read/write
0x81 D7 to D0 Read/write
0x82 Start frequency D23 to D16 Read/write
0x85 Frequency increment D23 to D16 Read/write
0x88 Number of increments D15 to D8 Read/write
0x8A Number of settling time cycles D15 to D8 Read/write
0x8B D7 to D0 Read/write
0x8F Status D7 to D0 Read only
0x92 Temperature data D15 to D8 Read only
0x93 D7 to D0 Read only
0x94 Real data D15 to D8 Read only
0x96 Imaginary data D15 to D8 Read only
CONTROL REGISTER (REGISTER ADDRESS 0x80, Table 9. Control Register Map (D15 to D12)
REGISTER ADDRESS 0x81) D15 D14 D13 D12 Function
The AD5933 has a 16-bit control register (Register Address 0x80 0 0 0 0 No operation
and Register Address 0x81) that sets the AD5933 control 0 0 0 1 Initialize with start frequency
modes. The default value of the control register upon reset is 0 0 1 0 Start frequency sweep
as follows: D15 to D0 reset to 0xA000 upon power-up. 0 0 1 1 Increment frequency
0 1 0 0 Repeat frequency
The four MSBs of the control register are decoded to provide
1 0 0 0 No operation
control functions, such as performing a frequency sweep, 1 0 0 1 Measure temperature
powering down the part, and controlling various other 1 0 1 0 Power-down mode
functions defined in the control register map. 1 0 1 1 Standby mode
The user may choose to write only to Register Address 0x80 and 1 1 0 0 No operation
not to alter the contents of Register Address 0x81. Note that the 1 1 0 1 No operation
control register should not be written to as part of a block write
command. The control register also allows the user to program Table 10. Control Register Map (D10 to D9)
the excitation voltage and set the system clock. A reset command D10 D9 Range No. Output Voltage Range
to the control register does not reset any programmed values 0 0 1 2.0 V p-p typical
associated with the sweep (that is, start frequency, number of 0 1 4 200 mV p-p typical
increments, frequency increment). After a reset command, an 1 0 3 400 mV p-p typical
initialize with start frequency command must be issued to the 1 1 2 1.0 V p-p typical
control register to restart the frequency sweep sequence (see
Figure 28).
AD5933 Data Sheet
Table 11. Control Register Map (D11, D8 to D0) Power-Down Mode
Bits Description The default state on power-up of the AD5933 is power-down
D11 No operation mode. The control register contains the code 1010,0000,0000,0000
D8 PGA gain; 0 = 5, 1 = 1 (0xA000). In this mode, both the VOUT and VIN pins are
D7 Reserved; set to 0 connected internally to GND.
D6 Reserved; set to 0 Standby Mode
D5 Reserved; set to 0
D4 Reset This mode powers up the part for general operation; in standby
D3 External system clock; set to 1 mode the VIN and VOUT pins are internally connected to ground.
Internal system clock; set to 0 Output Voltage Range
D2 Reserved; set to 0 The output voltage range allows the user to program the
D1 Reserved; set to 0 excitation voltage range at VOUT.
D0 Reserved; set to 0
PGA Gain
Control Register Decode The PGA gain allows the user to amplify the response signal
Initialize with Start Frequency into the ADC by a multiplication factor of 5 or 1.
This command enables the DDS to output the programmed Reset
start frequency for an indefinite time. It is used to excite the A reset command allows the user to interrupt a sweep. The start
unknown impedance initially. When the output unknown frequency, number of increments, and frequency increment
impedance has settled after a time determined by the user, the register contents are not overwritten. An initialize with start
user must initiate a start frequency sweep command to begin frequency command is required to restart the frequency sweep
the frequency sweep. command sequence.
Start Frequency Sweep START FREQUENCY REGISTER (REGISTER
In this mode the ADC starts measuring after the programmed ADDRESS 0x82, REGISTER ADDRESS 0x83,
number of settling time cycles has elapsed. The user has the REGISTER ADDRESS 0x84)
ability to program an integer number of output frequency cycles The default value of the start frequency register upon reset is
(settling time cycles) to Register Address 0x8A and Register as follows: D23 to D0 are not reset on power-up. After a reset
Address 0x8B before the commencement of the measurement command, the contents of this register are not reset.
at each frequency point (see Figure 28).
The start frequency register contains the 24-bit digital represen-
Increment Frequency tation of the frequency from where the subsequent frequency
The increment frequency command is used to step to the next sweep is initiated. For example, if the user requires the sweep to
frequency point in the sweep. This usually happens after data start from frequency 30 kHz (using a 16.0 MHz clock), then the
from the previous step has been transferred and verified by the user programs the value of 0x0F to Register Address 0x82, the
DSP. When the AD5933 receives this command, it waits for the value of 0x5C to Register Address 0x83, and the value of 0x28 to
programmed number of settling time cycles before beginning Register Address 0x84. This ensures the output frequency starts
the ADC conversion process. at 30 kHz.
Repeat Frequency The code to be programmed to the start frequency register is
The AD5933 has the facility to repeat the current frequency

point measurement by issuing a repeat frequency command to 30 kHz 27
Start Frequency Code = 2 0 x0F5C28
the control register. This has the benefit of allowing the user to 16 MHz
average successive readings.
4

Measure Temperature
The measure temperature command initiates a temperature
reading from the part. The part does not need to be in power-
up mode to perform a temperature reading. The block powers
itself up, takes the reading, and then powers down again. The
temperature reading is stored in a 14-bit, twos complement
format at Register Address 0x92 and Register Address 0x93.
Data Sheet AD5933
FREQUENCY INCREMENT REGISTER (REGISTER
This register determines the number of frequency points in the
ADDRESS 0x85, REGISTER ADDRESS 0x86,
frequency sweep. The number of points is represented by a 9-bit
REGISTER ADDRESS 0x87)
word, D8 to D0. D15 to D9 are dont care bits. This register, in
The default value upon reset is as follows: D23 to D0 are not reset conjunction with the start frequency register and the increment
on power-up. After a reset command, the contents of this register frequency register, determines the frequency sweep range for
are not reset. the sweep operation. The maximum number of increments that
The frequency increment register contains a 24-bit represen- can be programmed is 511.
tation of the frequency increment between consecutive frequency NUMBER OF SETTLING TIME CYCLES
points along the sweep. For example, if the user requires an REGISTER (REGISTER ADDRESS 0x8A,
increment step of 10 Hz using a 16.0 MHz clock, the user REGISTER ADDRESS 0x8B)
should program the value of 0x00 to Register Address 0x85, the
value of 0x01 to Register Address 0x86m, and the value of 0x4F The default value upon reset is as follows: D10 to D0 are not
to Register Address 0x87. reset on power-up. After a reset command, the contents of this
register are not reset (see Table 13).
The formula for calculating the increment frequency is given by
This register determines the number of output excitation cycles
that are allowed to pass through the unknown impedance, after

10 Hz 27 receipt of a start frequency sweep, increment frequency, or
Frequency Increment Code = 2 0 x00014 F
16 MHz repeat frequency command, before the ADC is triggered to

4 perform a conversion of the response signal. The number of

settling time cycles register value determines the delay between
The user programs the value 0x00 to Register Address 0x85, the a start frequency sweep/increment frequency /repeat frequency
value 0x01 to Register Address 0x86, and the value 0x4F to command and the time an ADC conversion commences. The
Register Address 0x87. number of cycles is represented by a 9-bit word, D8 to D0. The
NUMBER OF INCREMENTS REGISTER (REGISTER value programmed into the number of settling time cycles
ADDRESS 0x88, REGISTER ADDRESS 0x89) register can be increased by a factor of 2 or 4 depending upon
the status of bits D10 to D9. The five most significant bits, D15
The default value upon reset is as follows: D8 to D0 are not reset
to D11, are dont care bits. The maximum number of output
on power-up. After a reset command, the contents of this
cycles that can be programmed is 511 4 = 2044 cycles. For
register are not reset.
example, consider an excitation signal of 30 kHz. The
Table 12. Number of Increments Register maximum delay between the programming of this frequency
Reg Bits Description Function Format and the time that this signal is first sampled by the ADC is
0x88 D15 to D9 Dont care Read or Integer number 511 4 33.33 s = 68.126 ms. The ADC takes 1024 samples,
write stored in binary and the result is stored as real data and imaginary data in
D8 Number of Read or format Register Address 0x94 to Register Address 0x97. The conversion
increments write process takes approximately 1 ms using a 16.777 MHz clock.
0x89 D8 to D0 Number of Read or Integer number
increments write stored in binary
format
Table 13. Number of Settling Times Cycles Register

Register Bits Description Function Format
0x8A D15 to D11 Dont care Read or write Integer number stored in
D10 to D9 2-bit decode binary format
D10 D9 Description
0 0 Default
0 1 No. of cycles 2
1 0 Reserved
1 1 No. of cycles 4
D8 MSB number of settling time cycles
0x8B D7 to D0 Number of settling time cycles Read or write
AD5933 Data Sheet
STATUS REGISTER (REGISTER ADDRESS 0x8F) Valid Real/Imaginary Data
The status register is used to confirm that particular measure- D1 is set when data processing for the current frequency point
ment tests have been successfully completed. Each of the bits is finished, indicating real/imaginary data available for reading.
from D7 to D0 indicates the status of a specific functionality of D1 is reset when a start frequency sweep/increment frequency/
the AD5933. repeat frequency DDS start/increment/repeat command is
issued. D1 is reset to 0 when a reset command is issued to the
Bit D0 and Bit D4 to Bit D7 are treated as dont care bits These
control register.
bits do not indicate the status of any measurement.
Frequency Sweep Complete
The status of Bit D1 indicates the status of a frequency point
impedance measurement. This bit is set when the AD5933 has D2 is set when data processing for the last frequency point in the
completed the current frequency point impedance measurement. sweep is complete. This bit is reset when a start frequency sweep
This bit indicates that there is valid real data and imaginary data command is issued to the control register. This bit is also reset
in Register Address 0x94 to Register Address 0x97. This bit is when a reset command is issued to the control register.
reset on receipt of a start frequency sweep, increment frequency, TEMPERATURE DATA REGISTER
repeat frequency, or reset command. This bit is also reset on (16 BITSREGISTER ADDRESS 0x92,
power-up. REGISTER ADDRESS 0x93)
The status of Bit D2 indicates the status of the programmed
These registers contain a digital representation of the temper-
frequency sweep. This bit is set when all programmed incre-
ments to the number of increments register are complete. This ature of the AD5933. The values are stored in 16-bit, twos
bit is reset on power-up and on receipt of a reset command. complement format. Bit D15 and Bit D14 are dont care bits.
Bit 13 is the sign bit. To convert this number to an actual
Table 14. Status Register (Register Address 0x8F) temperature, refer to the Temperature Conversion Formula
Control Word Function section.
0000 0001 Valid temperature measurement REAL AND IMAGINARY DATA REGISTERS (16
0000 0010 Valid real/imaginary data BITSREGISTER ADDRESS 0x94, REGISTER
0000 0100 Frequency sweep complete ADDRESS 0x95, REGISTER ADDRESS 0x96,
0000 1000 Reserved
REGISTER ADDRESS 0x97)
0001 0000 Reserved
0010 0000 Reserved The default value upon reset is as follows: these registers are not
0100 0000 Reserved reset on power-up or on receipt of a reset command. Note that
1000 0000 Reserved the data in these registers is valid only if Bit D1 in the status
register is set, indicating that the processing at the current
Valid Temperature Measurement frequency point is complete.
The valid temperature measurement control word is set when a These registers contain a digital representation of the real
valid temperature conversion is complete indicating that valid and imaginary components of the impedance measured for
temperature data is available for reading at Register Address the current frequency point. The values are stored in 16-bit,
0x92 and Register Address 0x93. It is reset when a temperature twos complement format. To convert this number to an actual
measurement takes place as a result of a measure temperature impedance value, the magnitude(Real2 + Imaginary2)must
command having been issued to the control register (Register be multiplied by an admittance/code number (called a gain
Address 0x80 and Register Address 0x81) by the user. factor) to give the admittance, and the result inverted to give
impedance. The gain factor varies for each ac excitation
voltage/gain combination.
Data Sheet AD5933
SERIAL BUS INTERFACE

Control of the AD5933 is carried out via the I2C-compliant Data is sent over the serial bus in sequences of nine clock
serial interface protocol. The AD5933 is connected to this bus pulses, eight bits of data followed by an acknowledge bit, which
as a slave device under the control of a master device. The can be from the master or slave device. Data transitions on the
AD5933 has a 7-bit serial bus slave address. When the device is data line must occur during the low period of the clock signal
powered up, it has a default serial bus address, 0001101 (0x0D). and remain stable during the high period, because a low-to-
high transition when the clock is high may be interpreted as a
GENERAL I2C TIMING
stop signal. If the operation is a write operation, the first data
Figure 29 shows the timing diagram for general read and write byte after the slave address is a command byte. This tells the
operations using the I2C-compliant interface. slave device what to expect next. It may be an instruction telling
The master initiates data transfer by establishing a start condition, the slave device to expect a block write, or it may be a register
defined as a high-to-low transition on the serial data line address that tells the slave where subsequent data is to be
(SDA), while the serial clock line (SCL) remains high. This written. Because data can flow in only one direction as defined
indicates that a data stream follows. The slave responds to the by the R/W bit, it is not possible to send a command to a slave
start condition and shifts in the next 8 bits, consisting of a 7-bit device during a read operation. Before performing a read
slave address (MSB first) plus an R/W bit that determines operation, it is sometimes necessary to perform a write
the direction of the data transferthat is, whether data is operation to tell the slave what sort of read operation to
written to or read from the slave device (0 = write, 1 = read). expect and/or the address from which data is to be read.
The slave responds by pulling the data line low during the low When all data bytes have been read or written, stop conditions
period before the ninth clock pulse, known as the acknowledge are established. In write mode, the master pulls the data line
bit, and holding it low during the high period of this clock high during the 10th clock pulse to assert a stop condition. In
pulse. All other devices on the bus remain idle while the read mode, the master device releases the SDA line during the
selected device waits for data to be read from or written to it. low period before the ninth clock pulse, but the slave device
If the R/W bit is 0, then the master writes to the slave device. does not pull it low. This is known as a no acknowledge. The
If the R/W bit is 1, the master reads from the slave device. master then takes the data line low during the low period
before the 10th clock pulse, then high during the 10th clock
pulse to assert a stop condition.
SCL
SDA 0 0 0 1 1 0 1 R/W D7 D6 D5 D4 D3 D2 D1 D0
05324-035
START CONDITION SLAVE ADDRESS BYTE ACKNOWLEDGE BY REGISTER ADDRESS ACKNOWLEDGE BY
BY MASTER AD5933 MASTER/SLAVE
Figure 29. Timing Diagram
AD5933 Data Sheet
WRITING/READING TO THE AD5933
05324-036
SLAVE REGISTER REGISTER
S W A A A P
ADDRESS ADDRESS DATA
The interface specification defines several different protocols
Figure 30. Writing Register Data to Register Address
for different types of read and write operations. This section
describes the protocols used in the AD5933. The figures in this The write byte protocol is also used to set a pointer to an
section use the abbreviations shown in Table 15. address (see Figure 31). This is used for a subsequent single-
byte read from the same address or block read or block write
Table 15. I2C Abbreviation Table starting at that address.
Abbreviation Condition
To set a register pointer, the following sequence is applied:
S Start
P Stop 1. The master device asserts a start condition on SDA.
R Read 2. The master sends the 7-bit slave address followed by the
W Write write bit (low).
A Acknowledge 3. The addressed slave device asserts an acknowledge on
A No acknowledge write byte/command byte SDA.
4. The master sends a pointer command code (see Table 16;
User Command Codes
a pointer command = 1011 0000).
The command codes in Table 16 are used for reading/writing to 5. The slave asserts an acknowledge on SDA.
the interface. They are further explained in this section, but are 6. The master sends a data byte (a register address to where
grouped here for easy reference. the pointer is to point).
7. The slave asserts an acknowledge on SDA.
Table 16. Command Codes
8. The master asserts a stop condition on SDA to end the
Command Code
Code Name Code Description
transaction.
1010 0000 Block This command is used when writing POINTER REGISTER
05324-037
SLAVE
S W A COMMAND A ADDRESS A P
write multiple bytes to the RAM; see the ADDRESS
1011 0000 TO POINT TO
Block Write section.
Figure 31. Setting Address Pointer to Register Address
1010 0001 Block This command is used when reading
read multiple bytes from RAM/memory; BLOCK WRITE
see the Block Read section.
In this operation, the master device writes a block of data to a
1011 0000 Address This command enables the user to set
pointer the address pointer to any location in slave device (see Figure 32). The start address for a block write
the memory. The data contains the must previously have been set. In the case of the AD5933 this is
address of the register to which the done by setting a pointer to set the register address.
pointer should be pointing reworded
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
Write Byte/Command Byte
write bit (low).
In this operation, the master device sends a byte of data to the 3. The addressed slave device asserts an acknowledge on SDA.
slave device. The write byte can either be a data byte write to a 4. The master sends an 8-bit command code (1010 0000) that
register address or can be a command operation. To write data tells the slave device to expect a block write.
to a register, the command sequence is as follows (see Figure 30): 5. The slave asserts an acknowledge on SDA.
1. The master device asserts a start condition on SDA. 6. The master sends a data byte that tells the slave device the
2. The master sends the 7-bit slave address followed by the number of data bytes to be sent to it.
write bit (low). 7. The slave asserts an acknowledge on SDA.
3. The addressed slave device asserts an acknowledge on SDA. 8. The master sends the data bytes.
4. The master sends a register address. 9. The slave asserts an acknowledge on SDA after each
5. The slave asserts an acknowledge on SDA. data byte.
6. The master sends a data byte. 10. The master asserts a stop condition on SDA to end the
7. The slave asserts an acknowledge on SDA. transaction.
transaction.
05324-038
SLAVE BLOCK NUMBER

S W A A A BYTE 0 A BYTE 1 A BYTE 2 A P
ADDRESS WRITE BYTES WRITE
Figure 32. Writing a Block Write
Data Sheet AD5933
READ OPERATIONS Block Read
The AD5933 uses two I2C read protocols: receive byte and In this operation, the master device reads a block of data from a
block read. slave device (see Figure 34). The start address for a block read
must previously have been set by setting the address pointer.
Receive Byte
1. The master device asserts a start condition on SDA.
In the AD5933, the receive byte protocol is used to read a single 2. The master sends the 7-bit slave address followed by the
byte of data from a register address whose address has previously write bit (low).
been set by setting the address pointer. 3. The addressed slave device asserts an acknowledge on SDA.
In this operation, the master device receives a single byte from a 4. The master sends a command code (1010 0001) that tells
slave device as follows (see Figure 33): the slave device to expect a block read.
1. The master device asserts a start condition on SDA. 5. The slave asserts an acknowledge on SDA.
2. The master sends the 7-bit slave address followed by the 6. The master sends a byte-count data byte that tells the slave
read bit (high). how many data bytes to expect.
3. The addressed slave device asserts an acknowledge on SDA. 7. The slave asserts an acknowledge on SDA.
4. The master receives a data byte. 8. The master asserts a repeat start condition on SDA. This is
5. The master asserts a no acknowledge on SDA (the slave required to set the read bit high.
needs to check that master has received data). 9. The master sends the 7-bit slave address followed by the
6. The master asserts a stop condition on SDA and the read bit (high).
transaction ends. 10. The slave asserts an acknowledge on SDA.
11. The master receives the data bytes.
05324-039
S
SLAVE
ADDRESS
R A
REGISTER
DATA
A P 12. The master asserts an acknowledge on SDA after each
data byte.
Figure 33. Reading Register Data
13. A no acknowledge is generated after the last byte to signal
the end of the read.
transaction.
05324-040
SLAVE BLOCK NUMBER SLAVE
S W A A A S R A BYTE 0 A BYTE 1 A BYTE 2 A P
ADDRESS READ BYTES READ ADDRESS
Figure 34. Performing a Block Read
AD5933 Data Sheet
TYPICAL APPLICATIONS
MEASURING SMALL IMPEDANCES The value of the output series resistance depends upon the
The AD5933 is capable of measuring impedance values up to selected output excitation range at VOUT and has a tolerance
10 M if the system gain settings are chosen correctly for the from device to device like all discrete resistors manufactured in
impedance subrange of interest. a silicon fabrication process. Typical values of the output series
resistance are outlined in Table 17.
If the user places a small impedance value (500 over the
sweep frequency of interest) between the VOUT and VIN pins, Table 17. Output Series Resistance (ROUT) vs. Excitation Range
it results in an increase in signal current flowing through the Parameter Value (Typ) Output Series Resistance Value
impedance for a fixed excitation voltage in accordance with Range 1 2 V p-p 200 typ
Ohms law. The output stage of the transmit side amplifier Range 2 1 V p-p 2.4 k typ
available at the VOUT pin may not be able to provide the Range 3 0.4 V p-p 1.0 k typ
required increase in current through the impedance. To have a Range 4 0.2 V p-p 600 typ
unity gain condition about the receive side I-V amplifier, the
Therefore, to accurately calibrate the AD5933 to measure small
user needs to have a similar small value of feedback resistance
impedances, it is necessary to reduce the signal current by
for system calibration as outlined in the Gain Factor Setup
attenuating the excitation voltage sufficiently and also account
Configuration section. The voltage presented at the VIN pin is
hard biased at VDD/2 due to the virtual earth on the receive for the ROUT value and factor it into the gain factor calculation
side I-V amplifier. The increased current sink/source (see the Gain Factor Calculation section).
requirement placed on the output of the receive side I-V Measuring the ROUT value during device characterization is
amplifier may also cause the amplifier to operate outside of achieved by selecting the appropriate output excitation range at
the linear region. This causes significant errors in subsequent VOUT and sinking and sourcing a known current at the pin
impedance measurements. (for example, 2 mA) and measuring the change in dc voltage.
The output series resistance can be calculated by measuring the
The value of the output series resistance, ROUT, (see Figure 35)
at the VOUT pin must be taken into account when measuring inverse of the slope (that is, 1/slope) of the resultant I-V plot.
small impedances (ZUNKNOWN), specifically when the value of A circuit that helps to minimize the effects of the issues
the output series resistance is comparable to the value of the previously outlined is shown in Figure 35. The aim of this
impedance under test (ZUNKNOWN). If the ROUT value is unac- circuit is to place the AD5933 system gain within its linear
counted for in the system calibration (that is, the gain factor range when measuring small impedances by using an additional
calculation) when measuring small impedances, there is an external amplifier circuit along the signal path. The external
introduced error into any subsequent impedance measurement amplifier attenuates the peak-to-peak excitation voltage at
that takes place. The introduced error depends on the relative VOUT by a suitable choice of resistors (R1 and R2), thereby
magnitude of the impedance being tested compared to the value reducing the signal current flowing through the impedance and
of the output series resistance. minimizing the effect of the output series resistance in the
2V p-p impedance calculations.
TRANSMIT SIDE
OUTPUT AMPLIFIER R1 In the circuit shown in Figure 35, ZUNKNOWN recognizes the
ROUT VOUT R2 output series resistance of the external amplifier which is
DDS
typically much less than 1 with feedback applied depending
VDD
AD8531 upon the op amp device used (for example, AD820, AD8641,
20k
AD820 AD8531) as well as the load current, bandwidth, and gain.
VDD/2 AD8641
RFB 20k
AD8627
1F
RFB
PGA I-V VIN ZUNKNOWN

05324-048
VDD/2
Figure 35. Additional External Amplifier Circuit for Measuring Small

Impedances
Data Sheet AD5933
The key point is that the output impedance of the external To attenuate the excitation voltage at VOUT, choose a ratio
amplifier in Figure 35 (which is also in series with ZUNKNOWN) of R1/R2. With the values of R1 = 4 k and R2 = 20 k,
has a far less significant effect on gain factor calibration and attenuate the signal by 1/5th of 2 V p-p = 400 mV. The
subsequent impedance readings in comparison to connecting maximum current flowing through the impedance is 400 mV/
the small impedance directly to the VOUT pin (and directly in 90 = 4.4 mA.
series with ROUT). The external amplifier buffers the unknown The system is subsequently calibrated using the usual method
impedance from the effects of ROUT and introduces a smaller with a midpoint impedance value of 100 , a calibration
output impedance in series with ZUNKNOWN. resistor, and a feedback resistor at a midfrequency point in the
For example, if the user measures ZUNKNOWN that is known to sweep. The dynamic range of the input signal to the receive side
have a small impedance value within the range of 90 to of the AD5933 can be improved by increasing the value of the
110 over the frequency range of 30 kHz to 32 kHz, the I-V gain resistor at the RFB pin. For example, increasing the I-V
user may not be in a position to measure ROUT directly in gain setting resistor at the RFB pin increases the peak-to-peak
the factory/lab. Therefore, the user may choose to add on signal presented to the ADC input from 400 mV (RFB = 100 )
an extra amplifier circuit like that shown in Figure 35 to the to 2 V p-p (RFB = 500 ).
signal path of the AD5933. The user must ensure that the The gain factor calculated is for a 100 resistor connected
chosen external amplifier has a sufficiently low output series between VOUT and VIN, assuming the output series resistance
resistance over the bandwidth of interest in comparison to the of the external amplifier is small enough to be ignored.
impedance range under test (for an op amp selection guide, see
www.analog.com/opamps). Most amplifiers from Analog When biasing the circuit shown in Figure 35, note that the
Devices have a curve of closed loop output impedance vs. receive side of the AD5933 is hard-biased about VDD/2 by
frequency at different amplifier gains to determine the output design. Therefore, to prevent the output of the external
series impedance at the frequency of interest. amplifier (attenuated AD5933 Range 1 excitation signal) from
saturating the receive side amplifiers of the AD5933, a voltage
The system settings are equal to VDD/2 must be applied to the noninverting terminal
VDD = 3.3 V of the external amplifier.
VOUT = 2 V p-p
R2 = 20 k
R1 = 4 k
Gain setting resistor = 500
ZUNKNOWN = 100
PGA setting = 1
AD5933 Data Sheet
BIOMEDICAL: NONINVASIVE BLOOD IMPEDANCE SENSOR/COMPLEX IMPEDANCE MEASUREMENT
MEASUREMENT The operational principle of a capacitive proximity sensor is
When a known strain of a virus is added to a blood sample based on the change of a capacitance in an RLC resonant
that already contains a virus, a chemical reaction takes place circuit. This leads to changes in the resonant frequency of the
whereby the impedance of the blood under certain conditions RLC circuit, which can be evaluated as shown Figure 37.
changes. By characterizing this effect across different frequencies, It is first required to tune the RLC circuit to the area of
it is possible to detect a specific strain of virus. For example, a resonance. At the resonant frequency, the impedance of the
strain of the disease exhibits a certain characteristic impedance RLC circuit is at a maximum. Therefore, a programmable
at one frequency but not at another; therefore, the requirement frequency sweep and tuning capability is required, which is
is to sweep different frequencies to check for different viruses. provided by the AD5933.
The AD5933, with its 27-bit phase accumulator, allows for
CHANGE IN
subhertz frequency tuning. RESONANT
FREQUENCY RESONANCE DUE
TO APPROACHING
The AD5933 can be used to inject a stimulus signal through OBJECT
the blood sample via a probe. The response signal is analyzed,
PROXIMITY IMPEDANCE ()
and the effective impedance of the blood is tabulated. The
AD5933 is ideal for this application because it allows the user
to tune to the specific frequency required for each test.
1 16 ADuC702x
TOP VIEW
2 15 (Not to Scale)
AD5933
3 TOP VIEW 14
RFB (Not to Scale) FO
05324-042
4 13
FREQUENCY (Hz)
5 12
Figure 37. Detecting a Change in Resonant Frequency
6 11
An example of the use of this type of sensor is for a train
7 10
PROBE proximity measurement system. The magnetic fields of the
8 9 train approaching on the track change the resonant frequency
to an extent that can be characterized. This information can be
7V sent back to a mainframe system to show the train location
2
ADR43x
6 on the network.
0.1F 10F
Another application for the AD5933 is in parked vehicle detec-
05324-041
tion. The AD5933 is placed in an embedded unit connected to

Figure 36. Measuring a Blood Sample for a Strain of Virus a coil of wire underneath the parking location. The AD5933
outputs a single frequency within the 80 kHz to 100 kHz
frequency range, depending upon the wire composition. The
wire can be modeled as a resonant circuit. The coil is calibrated
with a known impedance value and at a known frequency. The
impedance of the loop is monitored constantly. If a car is parked
over the coil, the impedance of the coil changes and the
AD5933 detects the presence of the car.
Data Sheet AD5933
ELECTRO-IMPEDANCE SPECTROSCOPY 100k 75
The AD5933 has found use in the area of corrosion monitoring.

Corrosion of metals, such as aluminum and steel, can damage 10k
industrial infrastructures and vehicles such as aircraft, ships, 50
PHASE ANGLE
and cars. This damage, if left unattended, may lead to premature
MODULUS
failure requiring expensive repairs and/or replacement. In 1k
many cases, if the onset of corrosion can be detected, it can
be arrested or slowed, negating the requirement for repairs or 25
replacement. At present, visual inspection is employed to detect 100
corrosion; however, this is time consuming, expensive, and
cannot be employed in hard-to-access areas.
An alternative to visual inspection is automated monitoring 10 0
05324-043
0.1 1 10 100 1k 10k 100k
using corrosion sensors. Monitoring is cheaper, less time FREQUENCY (Hz)
consuming, and can be deployed where visual inspections are Figure 38. Bode Plot for Aluminum Corrosion Sensor
impossible. Electrochemical impedance spectroscopy (EIS) has
been used to interrogate corrosion sensors, but at present large To make accurate measurements of these values, the impedance
laboratory test instruments are required. The AD5933 offers an needs to be measured over a frequency range of 0.1 Hz to 100 kHz.
accurate and compact solution for this type of measurement, To ensure that the measurement itself does not introduce a
enabling the development of field deployable sensor systems corrosive effect, the metal needs to be excited with minimal
that can measure corrosion rates autonomously. voltage, typically in the 20 mV range. A nearby processor
or control unit such as the ADuC702x would log a single
Mathematically, the corrosion of aluminum is modeled using an impedance sweep from 0.1 kHz to 100 kHz every 10 minutes
RC network that typically consists of a resistance, RS, in series and download the results back to a control unit. To achieve
with a parallel resistor and capacitor, RP and CP. A system metal system accuracy from the 0.1 kHz to 1 kHz range, the system
would typically have values as follows: RS is 10 to 10 k, clock needs to be scaled down from the 16.776 MHz nominal
RP 1 is k to 1 M, and CP is 5 F to 70 F. Figure 38 shows clock frequency to 500 kHz, typically. The clock scaling can be
a typical Bode plot, impedance modulus, and phase angle vs. achieved digitally using an external direct digital synthesizer
frequency, for an aluminum corrosion sensor. like the AD9834 as a programmable divider, which supplies a
clock signal to MCLK and which can be controlled digitally by
the nearby microprocessor.
AD5933 Data Sheet
LAYOUT AND CONFIGURATION

POWER SUPPLY BYPASSING AND GROUNDING The power supply line itself should have as large a trace as
When accuracy is important in a circuit, carefully consider the possible to provide a low impedance path and reduce glitch
power supply and ground return layout on the board. The effects on the supply line. Clocks and other fast switching
printed circuit board containing the AD5933 should have digital signals should be shielded from other parts of the board
separate analog and digital sections, each having its own area by digital ground. Avoid crossover of digital and analog signals
of the board. If the AD5933 is in a system where other devices if possible. When traces cross on opposite sides of the board,
require an AGND-to-DGND connection, the connection ensure that they run at right angles to each other to reduce
should be made at one point only. This ground point should feedthrough effects on the board. The best board layout
be as close as possible to the AD5933. technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only, and the
The power supply to the AD5933 should be bypassed with signal traces are placed on the solder side. However, this is not
10 F and 0.1 F capacitors. The capacitors should be physically always possible with a two-layer board.
as close as possible to the device, with the 0.1 F capacitor
ideally right up against the device. The 10 F capacitors are
the tantalum bead type. It is important that the 0.1 F capacitor
have low effective series resistance (ESR) and effective series
inductance (ESI); common ceramic types of capacitors are
suitable. The 0.1 F capacitor provides a low impedance path
to ground for high frequencies caused by transient currents
due to internal logic switching.
Data Sheet AD5933
EVALUATION BOARD
The AD5933 evaluation board allows designers to evaluate USING THE EVALUATION BOARD
the high performance AD5933 impedance converter with The AD5933 evaluation board is a test system designed to
minimum effort. simplify the evaluation of the AD5933. The evaluation board
The evaluation board interfaces to the USB port of a PC. It is data sheet is also available with the evaluation board that gives
possible to power the entire board from the USB port. full information on operating the evaluation board. Further
The impedance converter evaluation kit includes a populated evaluation information is available from www.analog.com.
and tested AD5933 printed circuit board. The EVAL-AD5933EB PROTOTYPING AREA
kit is shipped with a CD-ROM that includes self-installing
An area is available on the evaluation board for the user to add
software. Connect the PC to the evaluation board using the
additional circuits to the evaluation test set. Users may want to
supplied cable.
include switches for multiple calibration use.
The software is compatible with Microsoft Windows 2000 and
CRYSTAL OSCILLATOR (XO) vs. EXTERNAL CLOCK
Windows XP and Windows 7.
A 16 MHz oscillator is included on the evaluation board.
A schematic of the evaluation board is shown in Figure 39 and
However, this oscillator can be removed and, if required,
Figure 40.
an external CMOS clock can be connected to the part.
AD5933 Data Sheet
SCHEMATICS
05324-044
Figure 39. EVAL-AD5933EBZ USB Schematic
Data Sheet AD5933
05324-045
Figure 40. EVAL-AD5933EBZ Schematic
AD5933 Data Sheet
05324-046
Figure 41. Linear Regulator on the EVAL-AD5933EB Evaluation Board
Data Sheet AD5933
05324-047
Figure 42. Decoupling on the EVAL-AD5933EB Evaluation Board
AD5933 Data Sheet
OUTLINE DIMENSIONS
6.50
6.20
5.90
16 9
5.60
5.30
5.00 8.20
7.80
1 7.40
8
1.85 0.25
2.00 MAX 1.75 0.09
1.65
8 0.95
0.05 MIN 0.38
SEATING 4 0.75
COPLANARITY 0.22 PLANE
0.65 BSC 0 0.55
0.10
060106-A
COMPLIANT TO JEDEC STANDARDS MO-150-AC
Figure 43. 16-Lead Shrink Small Outline Package [SSOP]

(RS-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2 Temperature Range Package Description Package Option
AD5933YRSZ 40C to +125C 16-Lead Shrink Small Outline Package (SSOP) RS-16
AD5933YRSZ-REEL7 40C to +125C 16-Lead Shrink Small Outline Package (SSOP) RS-16
AD5933WYRSZ-REEL7 40C to +125C 16-Lead Shrink Small Outline Package (SSOP) RS-16
EVAL-AD5933EBZ 40C to +125C Evaluation Board
1
Z = RoHS Compliant Part.
2
W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The AD5933W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
20052013 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D05324-0-5/13(E)

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1 MSPS, 12-Bit Impedance

Converter, Network Analyzer

FUNCTIONAL BLOCK DIAGRAM

Rev. E Document Feedback

COMPARABLE PARTS DOCUMENTATION

SAMPLE AND BUY

Terminology .................................................................................... 12 Temperature Data Register (16 BitsRegister Address 0x92,

START REPEATED STOP

Figure 2. I2C Interface Timing Diagram

ABSOLUTE MAXIMUM RATINGS

Table 3. Stresses above those listed under Absolute Maximum Ratings

PIN CONFIGURATION AND DESCRIPTIONS

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

TYPICAL PERFORMANCE CHARACTERISTICS

PHASE ERROR (Degrees)

VOLTAGE (V) PHASE (Degrees)

16.4 16.6 16.8 17.0 17.2

Figure 15. Frequency Distribution of Internal Oscillator at 25C

MAC CORE RFB

Figure 17. Block Overview

3 383 mV p-p 0.31 V

the DDS is generated from either an external reference clock,

The AD5933 offers a frequency resolution programmable by the

user can program an integer number of output frequency VDD/2 ADC

The temperature sensor block defaults to a power-down state.

is issued by the user to the control register (Register Address 0x80

stores the temperature reading from the ADC in 14-bit, twos

Magnitude = R 2 + I 2 IMPEDANCE CALCULATION USING GAIN FACTOR

Real data register = 0xF064 = 3996 decimal

Figure 22. Impedance Profile Using a Single-Point Gain Factor Calculation

Figure 24. System Voltage Gain

98.5 Gain Setting Re sistor

Calibration impedance value, ZUNKNOWN = 100.0 k PGA setting = 1

PGA gain = 1 The peak-to-peak voltage presented to the ADC input is

Where gain factor is given by

impedance connected between VIN and VOUT. 50

Z is the phase due to the impedance, that is, the impedance 40

Figure 27. Phase Response of a Capacitor

0 15k 30k 45k 60k 75k 90k 105k 120k

Figure 26. System Phase Response vs. Capacitive Phase

PERFORMING A FREQUENCY SWEEP

PLACE THE AD5933 INTO STANDBY MODE.

RESET: BY ISSUING A RESET COMMAND TO

PROGRAM INITIALIZE WITH START

AFTER A SUFFICIENT AMOUNT OF SETTLING

POLL STATUS REGISTER TO CHECK IF

PROGRAM THE INCREMENT FREQUENCY OR

POLL STATUS REGISTER TO CHECK IF N

Figure 28. Frequency Sweep Flow Chart

Table 13. Number of Settling Times Cycles Register

SERIAL BUS INTERFACE

Figure 29. Timing Diagram

SLAVE BLOCK NUMBER

Figure 32. Writing a Block Write

Figure 34. Performing a Block Read

PGA I-V VIN ZUNKNOWN

Figure 35. Additional External Amplifier Circuit for Measuring Small

tion. The AD5933 is placed in an embedded unit connected to

The AD5933 has found use in the area of corrosion monitoring.