Scribd Logo
Upload

Welcome to Scribd!

  • 500 views

    4-Bit Asynchronous Up Counter: Program

    Uploaded by

    sindhura
    This document describes the code for 4-bit asynchronous up and down counters. The up counter increments the output signal tmp by 1 on each rising clock edge unless the clear signal is asserted, in which case tmp is set to 0000. The down counter decrements tmp by 1 on each clock edge unless clear is asserted, then tmp is set to 1111. Both counters output the signal tmp as their 4-bit output Q.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    4-Bit Asynchronous Up Counter: Program

    Uploaded by

    sindhura
    500 views2 pages
    This document describes the code for 4-bit asynchronous up and down counters. The up counter increments the output signal tmp by 1 on each rising clock edge unless the clear signal is asserted, in which case tmp is set to 0000. The down counter decrements tmp by 1 on each clock edge unless clear is asserted, then tmp is set to 1111. Both counters output the signal tmp as their 4-bit output Q.

    Original Title

    11 prog.docx

    Copyright

    © © All Rights Reserved

    Available Formats

    DOCX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document describes the code for 4-bit asynchronous up and down counters. The up counter increments the output signal tmp by 1 on each rising clock edge unless the clear signal is asserted, in which case tmp is set to 0000. The down counter decrements tmp by 1 on each clock edge unless clear is asserted, then tmp is set to 1111. Both counters output the signal tmp as their 4-bit output Q.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    500 views2 pages

    4-Bit Asynchronous Up Counter: Program

    Uploaded by

    sindhura
    This document describes the code for 4-bit asynchronous up and down counters. The up counter increments the output signal tmp by 1 on each rising clock edge unless the clear signal is asserted, in which case tmp is set to 0000. The down counter decrements tmp by 1 on each clock edge unless clear is asserted, then tmp is set to 1111. Both counters output the signal tmp as their 4-bit output Q.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    You are on page 1of 2

    4-bit asynchronous up counter:

    Program:
    library IEEE;

    use ieee.std_logic_1164.all;

    use ieee.std_logic_unsigned.all;

    entity counter is

    port(Clock, CLR : in std_logic;

    Q : out std_logic_vector(3 downto 0));

    end counter;

    architecture archi of counter is

    signal tmp: std_logic_vector(3 downto 0);

    begin

    process (Clock, CLR)

    begin

    if (CLR='1') then

    tmp <= "0000";

    elsif (Clock'event and Clock='1') then

    tmp <= tmp + 1;

    end if;

    end process;

    Q <= tmp;

    end archi;
    4 bit asynchronous down counter:

    Program:
    library ieee;

    use ieee.std_logic_1164.all;

    use ieee.std_logic_unsigned.all;

    entity counter is

    port(Clock, CLR : in std_logic;

    Q : out std_logic_vector(3 downto 0));

    end counter;

    architecture archi of counter is

    signal tmp: std_logic_vector(3 downto 0);

    begin

    process (Clock, CLR)

    begin

    if (CLR='1') then

    tmp <= "1111";

    elsif (Clock'event and Clock='1') then

    tmp <= tmp - 1;

    end if;

    end process;

    Q <= tmp;

    end archi;

    You might also like