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4 Bit Synchronous Up Counter (Verilog) : Program

This document contains code for a 4-bit synchronous up counter and a 4-bit synchronous down counter in Verilog. The up counter increments its 4-bit register tmp by 1 on each clock pulse C unless a load signal SLOAD is active, in which case tmp is set to 1010. The down counter decrements its 4-bit register tmp by 1 on each clock pulse C if a signal S is active, otherwise tmp is set to 1111. Both counters assign their 4-bit register to the output Q.

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734 views2 pages

4 Bit Synchronous Up Counter (Verilog) : Program

This document contains code for a 4-bit synchronous up counter and a 4-bit synchronous down counter in Verilog. The up counter increments its 4-bit register tmp by 1 on each clock pulse C unless a load signal SLOAD is active, in which case tmp is set to 1010. The down counter decrements its 4-bit register tmp by 1 on each clock pulse C if a signal S is active, otherwise tmp is set to 1111. Both counters assign their 4-bit register to the output Q.

Uploaded by

sindhura
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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4 bit synchronous up counter (verilog):

Program:
module counter (C, SLOAD, Q);

input C, SLOAD;

output [3:0] Q;

reg [3:0] tmp;

always @(posedge C)

begin

if (SLOAD)

tmp = 4'b1010;

else

tmp = tmp + 1'b1;

end

assign Q = tmp;

endmodule

4 bit synchronous down counter:


Program:
module counter (C, S, Q);

input C, S;

output [3:0] Q;

reg [3:0] tmp;

always @(posedge C)

begin

if (S)

tmp = 4'b1111;

else

tmp = tmp - 1'b1;

end

assign Q = tmp;

endmodule

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