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Verilog Keywords

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74 views

Verilog Keywords

verilog

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Anonymous eWMnRr70q
Copyright
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List of Keywords, System Tasks, and Compiler Directives = C.1 Keywords Keywords are predefined, nonescaped identifiers that define the language constructs. An escaped identifier is never treated as a keyword. All keywords are defined in lowercase. The list is sorted in alphabetical order. Oey gn gage Drea begin but butifo butift deassign default, defparan disable eage else end endattribute endcase enéfunction endmodule endprimitive | endspecity endtable endtask event for force forever fork function highzo nighz1 it initial inout input integer join large macronodule medium nodule and negedge mos nor not notif0 notift | or output paraneter mos | poseage primitive pullo pullt pulldown pullup renos real realtime reg release repeat znnos zpmos rtran reranifo ztranifl scalared signed emall specify specparan strength strongd strongl supply0 supplyt table task time tran tranifo eranié1 ray trio eril eriand trior trireg unsigned vectored wait wana weakd weak1 while wire wor =c C.2 System Tasks and Functions The following is a list of keywords frequently used by Verilog simulators for names of system tasks and functions. Not all system tasks and functions are explained in this book. For details, refer to Verilog HDL Language Reference Manual This list is sorted in alphabetical order. sbitstoreal Scountdrivers $display Sfclose Sidisplay Sfopen S£strobe Sfwrite Sfinish Sgetpattern Shistory Sincsave Sinpue Sitor Skey slist Siog Smonitor Smonitorott §monitoron Snokey C.3 Compiler Directives The following is a list of keywords frequently used by Verilog simulators for specifying compiler directives. Only the most frequently used directives are discussed in the book. For details, refer to Verilog HDL Language Reference Manual. ‘This list is sorted in alphabetical order. ‘accelerate ‘autoexpand_vectornets ‘celldefine Sdefault_nettype “define ‘define selse sendcelldefine endif sendprotect endprotected ‘expand_vectorners “itaee include noaccelerate noexpand_vectornet's ‘noremove_gatenanes ‘nounconnected_drive rotect ‘protected *renove_gatenames ‘remove_netnames ‘resetall ‘timescale ‘unconnected drive en Verilog HDL: A Guide to Digital Design and Synthesis Formal Syntax Definition D= The following items summarize the format of the formal syntax descriptions: 1. Whitespace may be used to separate lexical tokens. 2. Angle brackets surround each description item and are nor literal symbols; that, is, they do not appear in a source example of a syntax item, 3. in lowercase is a syntax construct item defined by other syntax construct items or by lexical token items (see next item) 4, in uppercase is a lexical token item. Its definition is a terminal node in the description hierarchy; that is, its definition does not contain any syntax construct items ? is an optional item. * is zero, one, or more items, + is one or more items. <,>* is a comma-separated list of items with at least one item in the list. 9. if [condition] is a condition placed on one of several definitions. 10. ::= gives a syntax definition to an item. LL, Ils introduces an alternative syntax definition. 12, name is a literal (a keyword). For example, the definition .= event stipulates that the keyword “event” precedes the name of an event in an event declaration, 13. (+) places parenthesis symbols in a definition. These parentheses are literals required by the syntax being defined. Other literal symbols can also appear in a definition (for example, . and :) In Verilog syntax, a period (.) may not be preceded or followed by a space. 45

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