Introduction to VLSI Circuits and Systems

Chapter 07
Electronic Analysis of CMOS Logic Gates

Dept. of Electronic Engineering
National Chin-Yi University of Technology
Fall 2007

Introduction to VLSI Circuits and Systems, NCUT 2007

 Outline
DC Characteristic of the CMOS Inverter
Inverter Switching Characteristic
Power Dissipation
DC Characteristic: NAND and NOR Gates
NAND and NOR Transient Response
Analysis of Complex Logic Gates
Gate Design for Transient Performance
Transmission Gates and Pass Transistors

Introduction to VLSI Circuits and Systems, NCUT 2007

 The Inverter Circuit
The CMOS inverter gives the basic for calculating
the electrical characteristic of logic gates
The conduction states of Mn and Mp is determined by
input voltage Vin
Two types of calculations: DC analysis and transient
analysis

DC analysis
Provide a direct mapping of the input to the output,
such that to determine Vout

Transient analysis
The input voltage is an explicit function of time Vin(t)
corresponding to a changing logic value

Figure 7.1 The CMOS inverter circuit

Introduction to VLSI Circuits and Systems, NCUT 2007

 DC Analysis of Inverter
The DC characteristics of the inverter are portrayed
in the voltage transfer characteristic (VTC), which
is a plot of Vout as a function of Vin
Simply, the output high voltage of the circuits as

VOH = VDD (7.1) (Vin = 0)

(a) Low input voltage
The output low voltage

VOL = 0 V (7.2) (Vin = VDD)

The logic swing at the output is

VL = VOH VOL = VDD (7.3) (full-rail output)

Since this is equal to the full value of the power

supply, this is called a full-rail output (b) High input voltage

Figure 7.2 VOH and VOL for the inverter

Introduction to VLSI Circuits and Systems, NCUT 2007

 VTC of the Inverter
Starting with an input voltage of Vin = 0V and then
increasing it up to a value of Vin = VDD
VGSn = Vin
(7.4)
VSGp = VDD Vin
Mp goes into cutoff when
Vin = VDD VTp (7.5)
The logic 0 and 1 voltage ranges are defined by the changing
slope of the VTC
A logic 0 input voltage (input low voltage)

0 Vin VIL (7.6)

A logic 1 input voltage (input high voltage)

VIH Vin VDD (7.7)

The voltage noise margins give a quantitative measure of how
stable the inputs are with respect to coupled electromagnetic
signal interface, there are

VNM H = VOH VIH Figure 7.3 Voltage transfer

(7.8) curve for the NOT gate
VNM L = VIL VOL
Introduction to VLSI Circuits and Systems, NCUT 2007
 Definition of Noise Margins
V(y)
Slope = -1
V
OH
"1"
V
OH
NMH
V
Slope = -1 Noise Margin High IH
Undefined
VOL Region
Noise Margin Low
NML V
V V V(x) IL
IL IH V
OL
"0"
V
"1" OH
V Gate Output Gate Input
IH
VNM H = VOH VIH
Undefined (7.8)
Region
VNM L = VIL VOL
V
IL
"0"
V
OL

Introduction to VLSI Circuits and Systems, NCUT 2007

 Midpoint Voltage VM
W
'n
I Dn = I Dp (Let Vin = Vout = VM) n L n
(7.9) = (7.15)
p W
'p
L p

Vsat = VGSn VTn = VM VTn 'n

(7.10) 2 to 3
'p (7.16)

'n n
VDSn > Vsat = VM VTn (7.11) = = (7.17)
'p p

n p Symmetrical inverter principle

(VM VTn ) 2 = (VDD VM VTp ) 2 (7.12)
2 2
1
VM = VDD (7.18)
2
n
(V VTn ) = V DD VM VTp (7.13)
p M 1
2

n 2 VDD VTp
= (7.19)
p 1V V
n
VDD VTp + 2
DD Tn
V
p Tn
VM = (7.14)
n
1+ n = p (7.20) Figure 7.4 Inverter voltage
p
for VM calculation

Introduction to VLSI Circuits and Systems, NCUT 2007

 VTC Variation
In Figure 7.5(a), the pFET has a width of
about Wp2Wn
VM = (VDD/2)

In Figure 7.5(b), the pFET has a width of

about WpWn
VM < (VDD/2) (a) Large pFET design (b) Equal aspect ratios

At the physical level, the relative device Figure 7.5 Comparison of the layouts

sizes contained in the ratio (n/p)

determine the switching points

Figure 7.6 Dependence of VM on the

device ratio
Introduction to VLSI Circuits and Systems, NCUT 2007
 Outline
DC Characteristic of the CMOS Inverter
Inverter Switching Characteristic
Power Dissipation
DC Characteristic: NAND and NOR Gates
NAND and NOR Transient Response
Analysis of Complex Logic Gates
Gate Design for Transient Performance
Transmission Gates and Pass Transistors

Introduction to VLSI Circuits and Systems, NCUT 2007

 Switching Characteristic
High-speed digital system design requires that
logic gates introduce a minimum amount of time
delay when the inputs change
The output 1-to-0 transition introduces a fall time
delay of tf
The output 0-to-1 transition introduces a rise time
delay of tr

The rise time and fall time can be calculated by

analyzing the electronic transitions of the
circuits
parasitic resistance
parasitic capacitances of the transistors

Figure 7.7 General switching waveforms

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 RC Model of Inverter
Both FETs can be replaced by their switch equivalents,
which results in the simplified RC model
W
Given the aspect ratios W and
L n L p
1
Rn =
n (VDD VTn )
(7.28)
1
Rp =
p (VDD VTp )
(a) FET circuit

Finding the capacitance CDn and CDp at the output node

1
C Dn = CGSn + C DBn = Cox L'W n +C jn An + C jswn Pn
2 (7.29)
1
C Dp = CGSp + C DBp = Cox L'W p +C jp App + C jswp Pp
2

It is significant that increasing the channel width of

a FET increases the parasitic capacitance values (b) RC switch model equivalent

Figure 7.8 RC switch model

equivalent for the CMOS inverter

Introduction to VLSI Circuits and Systems, NCUT 2007

 Fan-out (FO)
The fan-out gates act as a load to the
driving circuit because of their input
capacitance Cin
Therefore, the total input capacitance is
(Figure 7.9(a))
(b) Loading
(a) Single stage
Cin = CGp + CGn (7.30) due to fan-out
Figure 7.9 Input capacitance and load effects
In Figure 7.9(b), the external load capacitance
CL is
CL = 3Cin (7.31)

In Figure 7.10 where the total output

capacitance is defined as (b) Complete
(a) External load
switch model
Cout = CFET + CL (7.32)
Figure 7.10 Evolution of the
C FET = C Dn + C Dp (7.33) inverter switching model
Introduction to VLSI Circuits and Systems, NCUT 2007
 Fall Time Calculation
Initially, Vout(0) = VDD, and Vin = 0 V and is switched to
Vin = VDD at time t = 0; we time shift this event to occur
at t = 0
The current leaving the capacitor is
dVout Vout
i = Cout = (7.42)
dt Rn
(a) Discharge circuit
The differential equation for the discharge events
t

n
Vout (t ) = VDD e , where n = RnCout (7.43, 44)

V
t = n ln DD (7.45)
Vout
t f = t y tx
V V
= n ln DD n ln DD (7.46)
0.1VDD 0.9VDD (b) Output waveform
= n ln(9 ) Figure 7.12 Discharge circuit
for the fall time calculation
t f 2.2 n (t HL = t f ) (7.48, 49)
Introduction to VLSI Circuits and Systems, NCUT 2007
 The Rise Time
Initially, Vout(0) = 0 V, and Vin = VDD and is switched to
Vin = 0 V at t = 0; we time shift this event to occur at t =
0
The charge current is given by
dVout VDD Vout
i = Cout = (7.50)
dt Rp

The differential equation for the charge events (a) Charge circuit

t
p

Vout (t ) = VDD 1 e , where p = R pCout (7.51, 52)

t r = t v tu (7.53)

tr = ln (9 ) p 2.2 p (7.54)
1 1
f max = = (7.55)
t HL + t LH tr + t f
(b) Output waveform
fmax is the largest frequency that can be applied to the
gate and still allow the output to settle to a definable Figure 7.13 Rise time calculation

state
Introduction to VLSI Circuits and Systems, NCUT 2007
 Propagation Delay (1/2)
The propagation delay time tp is often used to
estimate the reaction delay time from input to
output
tp =
(t pf + t pr )
(7.64)
2
tpf is the output fall time from the maximum level to the
50% voltage line, i.e., from VDD to (VDD/2)

t pf = ln (2 ) n (7.65)

tpr is the propagation rise time from 0 V to (VDD/2)

t pr = ln (2 ) p (7.65)

t p 0.35( n + p ) (7.66)
Figure 7.14 Propagation time definitions

Commonly used in basic logic simulation programs

because does not provide detailed information on
the rise and fall times as individual quantities

Introduction to VLSI Circuits and Systems, NCUT 2007

 Propagation Delay (2/2)
The rise and fall time equations provide the
basic for high-speed CMOS design

Cout = CFET + CL (7.67) Case II: When CL 0,

2. 2
p = 2. 2 R p = (7.71)
tr 2.2 R p (C FET + C L ) p (VDD VTp )
(7.68)
t f 2.2 Rn (C FET + C L )
2.2
n = 2.2 Rn = (7.72)
tr = tr 0 + pC L n (VDD VTn )
(7.69)
t f = t f 0 + nC L
W
p = p '
Case I: When CL = 0, L p
tr = tr 0 2.2 R p C FET (7.73)
(7.70) W
t f = t f 0 2.2 RnC FET n = n '
L n
Figure 7.15 General behavior
of the rise and fall time

Introduction to VLSI Circuits and Systems, NCUT 2007

 Delay Definitions

Vin

50%

t
t t
pHL pLH
Vout
90%

50%

10% t
tf tr

Introduction to VLSI Circuits and Systems, NCUT 2007

 Outline
DC Characteristic of the CMOS Inverter
Inverter Switching Characteristic
Power Dissipation
DC Characteristic: NAND and NOR Gates
NAND and NOR Transient Response
Analysis of Complex Logic Gates
Gate Design for Transient Performance
Transmission Gates and Pass Transistors

Introduction to VLSI Circuits and Systems, NCUT 2007

 Power Dissipation (1/2)
The current IDD flowing from the power supply
to ground gives a dissipated power of
P = VDD I DD (7.85)

Since VDD is assumed to be a constant

P = PDC + Pdyn (7.86) Figure 7.16 Origin of power

Where PDC is the DC term and Pdyn is due to dissipation calculation
dynamic switching events

DC contribution
PDC = VDD I DDQ (7.87)
Where IDDQ is leakage current

Leakage current is very small, therefore, the

value of PDC is thus quite small
(a) VTC (b) DC current
However, leakage power on today is critical for
low-power Design Figure 7.17 DC current flow

Introduction to VLSI Circuits and Systems, NCUT 2007

 Power Dissipation (2/2)
Dynamic power dissipation Pdyn
1
f = (7.88)
T
Pdyn arises from the observation that a complete
cycle effectively creates a path for current to flow
from the power supply to ground
(a) Input voltage
Qe = CoutVDD (7.89)

The average power dissipation over a single cycle

with a period T is

Q
Pav = VDD I DD = VDD e (7.90)
T

Psw = C outVDD f
2
(7.91)

(b) Charge (c) Discharge

P = V DD I DDQ + C out V 2
DD f (7.92)
Figure 7.18 Circuit for finding the
transient power dissipation
DC term dynamic power
term
Introduction to VLSI Circuits and Systems, NCUT 2007
 Outline
DC Characteristic of the CMOS Inverter
Inverter Switching Characteristic
Power Dissipation
DC Characteristic: NAND and NOR Gates
NAND and NOR Transient Response
Analysis of Complex Logic Gates
Gate Design for Transient Performance
Transmission Gates and Pass Transistors

Introduction to VLSI Circuits and Systems, NCUT 2007

 NAND Analysis (1/2)

Figure 7.19 NAND2 logic circuit Figure 7.21 Layout of NAND2 for VM calculation

(a) Transition table (b) VTC family (a) Separate transistors (b) Single equivalent FET

Figure 7.20 NAND 2 VTC analysis Figure 7.22 Simplification of the

series-connected nFETs
Introduction to VLSI Circuits and Systems, NCUT 2007
 NAND Analysis (2/2)
Find VM for the case of simultaneous
switching, where the nFET and pFET
transconductance are (n/2) and 2p

( n / 2) (2 )
2
(VM VTn ) =
2

2
p
(V DD VM VTp )
2
(7.93)
(a) Separate transistors (b) Single equivalent FET

1 n Figure 7.23 Simplification of the

VDD VTp + VTn series-connected nFETs
2 p
VM = (7.94)
1 n
1+
2 p

1 n
VDD VTp + VTn
N p
VM = (7.95)
1 n
1+
N p
Figure 7.24 Simplified VM circuit
for the NAND2 gate

Introduction to VLSI Circuits and Systems, NCUT 2007

 NOR Analysis

(2 n ) ( / 2)
2
(VM VTn ) =
2 p

2
(V DD VM VTp )
2
(7.96)

n
VDD VTp + 2 VTn
p
VM = (7.97)

1+ 2 n
p
Figure 7.27 NOR23 VM
Figure 7.25 NOR2 circuit
calculation
n
VDD VTp + N VTn
p
VM = (7.98)
n
1+ N
p

PDC = V DD I DDQ (7.99)

(a) Transition table (b) VTC family

Psw = C out V DD f gate
2
(7.100)
Figure 7.26 NOR 2 VTC analysis

Introduction to VLSI Circuits and Systems, NCUT 2007

 Outline
DC Characteristic of the CMOS Inverter
Inverter Switching Characteristic
Power Dissipation
DC Characteristic: NAND and NOR Gates
NAND and NOR Transient Response
Analysis of Complex Logic Gates
Gate Design for Transient Performance
Transmission Gates and Pass Transistors

Introduction to VLSI Circuits and Systems, NCUT 2007

 NAND Switching Times (1/2)
Figure 7.28
C out = C FET + C L (7. 101)

CFET = CDn + 2CDp (7. 102)

1 1
RP = , Rn = (7. 103)
p (V DD VTp n (V DD VTn )
Figure 7.28 NAND2 circuit for
transient calculations
Figure 7.29 (a)
t / p (7. 104)
Vout (t ) = VDD [1 e ]

where p = R p C out (7. 105)

t r 2.2 p (7. 106)

t r = t0 + 0C L (7. 107)
(a) Charge circuit (b) Discharge circuit
t 0 = 2.2 R p C FET (7. 108)
Figure 7.29 NAND2 subcircuits for
0 = 2.2 R p (7. 109) estimating rise and fall times
Introduction to VLSI Circuits and Systems, NCUT 2007
NAND Switching Times (2/2)

Vout (t ) = V DD e t / n (7. 110) n = Rn (2C out + C X ) (7. 120 from 7.111)

n = C out ( Rn + Rn ) + C X Rn (7. 111) C eff = 2C out + C X (7. 121)

n = n1 + n 2 (7. 112) n = C out (2 Rn ) + C X Rn (7. 122)

where n1 = C out ( Rn + Rn ) (7. 113)

n 2 = C X Rn (7. 114)

t f 2.2 n (7. 115)

t f 2.2[(C FET + C L )( 2 Rn ) + C X Rn ] (7. 116)

t f = t1 + 1 C L (7. 117)

t1 = 2.2 Rn (2C FET + C X ) (7. 118)

(b) Discharge circuit

1 = 4.4 Rn (7. 119)

Introduction to VLSI Circuits and Systems, NCUT 2007

 NOR Switching Times (1/2)
Figure 7.30

C out = C FET + C L (7. 123)

C FET = 2C Dn + C Dp (7. 124)

Figure 7.31 (a) Figure 7.30 NOR2 circuit for

switch time calculations
Vout (t ) = V DD e t / n (7. 125)

n = Rn C out (7. 126)

t f 2.2 n (7. 127)

t f = t1 + 1 C L (7. 128)
(a) Discharge circuit (b) Charge circuit
t1 = 2.2 Rn C FET (7. 129)
Figure 7.31 Subcircuits for the
1 = 2.2 Rn (7. 130) NOR2 transient calculations
Introduction to VLSI Circuits and Systems, NCUT 2007
 NOR Switching Times (2/2)
Figure 7.31 (b)
t / p
Vout (t ) = VDD [1 e ] (7. 131)

1 = C out ( R p + R p ) (7. 132)

2 = Cy Rp (7. 133)

p = 1 + 2 (7. 134)
= C out (2 R p ) + C y R p

t r = 2.2 p (7. 135)

(b) Charge circuit
tr = t0 + 0CL (7. 136)

where t 0 = 2.2 R p (2C FET + C y ) (7. 137)

0 = 4 .4 R p (7. 138)
Introduction to VLSI Circuits and Systems, NCUT 2007
 Outline
DC Characteristic of the CMOS Inverter
Inverter Switching Characteristic
Power Dissipation
DC Characteristic: NAND and NOR Gates
NAND and NOR Transient Response
Analysis of Complex Logic Gates
Gate Design for Transient Performance
Transmission Gates and Pass Transistors

Introduction to VLSI Circuits and Systems, NCUT 2007

Analysis of Complex Logic Gates
f = x ( y + z) (7. 141) p = R p C p + 2 R p C out (7. 149)

W W W tr = t0 + 0C L (7. 150)
= = (7. 142)
L nx L ny L nz
t 0 = 2.2 R p (C p + 2C FET ) (7. 151)
C out = C FET + C L (7. 143)

0 = 2 .2 R p (7. 152)
n = Rn C n + 2 Rn C out (7. 144)

t f = 2.2 n
= 2.2 Rn [C n + 2(C FET + C L )] (7. 145)
= t1 + 1C L
where t1 = 2.2 Rn (C n + 2C FET ) (7. 146)

1 = 2.2 Rn (7. 147)

W W W Figure 7.32 Complex logic gate circuit

= = (7. 148)
L px L py L pz Introduction to VLSI Circuits and Systems, NCUT 2007
 Power Dissipation
Power dissipation in a simple inverter
P = VDD I DDQ + C outVDD f
2
(7. 153)

We introduce the activity coefficient a that

represents the probability that an output 0 1 Figure 7.33 Truth tables for
transition takes place during one period determining activity coefficients

3 1 3
Pdyn = aC outVDD f
2
(7. 154) a NAND 2 = = (7. 158)
4 4 16

N
7
Pdyn = ai C iViV DD f (7. 155) a NOR 3 = = a NAND 3 (7. 159)
i =1 64

1
a = p 0 p1 (7. 156) a XNOR 2 = = a XOR 2 (7. 160)
4

3 1 3
a NOR 2 = = (7. 157)
4 4 16
Introduction to VLSI Circuits and Systems, NCUT 2007
 Outline
DC Characteristic of the CMOS Inverter
Inverter Switching Characteristic
Power Dissipation
DC Characteristic: NAND and NOR Gates
NAND and NOR Transient Response
Analysis of Complex Logic Gates
Gate Design for Transient Performance
Transmission Gates and Pass Transistors

Introduction to VLSI Circuits and Systems, NCUT 2007

 Gate Design for Transient
Performance (1/2)
W (Inverter reference starting) 1 2
= k' =
L n (VDD VTn ) N (V DD VTn )

1 1
Rp = , Rn = N = 2 n
p (VDD VTp ) n (V DD VTn )

W W
n = p = 2
L N L n
(a) Inverter
W W
= r N = n (NOR2 vs Inverter)
L p L n

kn ' 1 2
where r = =
kp' p (VDD VTp ) P (V DD VTp )

P = p (NAND2 vs Inverter) P = 2 p

R = RN + RN W W
= 2
L P L p
where R N =
1 (b) NAND2 (c) NOR2
N (V DD VTn )
Figure 7.34 Relative FET sizing
R = Rn = 2 R N
Introduction to VLSI Circuits and Systems, NCUT 2007
 Gate Design for Transient
Performance (2/2)
Extend to large chains as Figure 7.35
N = 3 n , P = p (7. 177)

W W W W
= 3 , = (7. 178)
L N L n L P L p
N = n , P = 3 p (7. 179) (a) NAND3 (b) NOR3
W W W W Figure 7.35 Sizing for 3-input gates
= , = 3 (7. 180)
L N L n L P L p

Figure 7.36

f = (a b + c d ) x (7. 181)

N = 3 n = N 1 (7. 182)

P = 2 p (7. 183)

P1 = p (7. 184)
Figure 7.36 Sizing of a complex logic gate
P1 = P = 2 P (7. 185)
Introduction to VLSI Circuits and Systems, NCUT 2007
 Outline
DC Characteristic of the CMOS Inverter
Inverter Switching Characteristic
Power Dissipation
DC Characteristic: NAND and NOR Gates
NAND and NOR Transient Response
Analysis of Complex Logic Gates
Gate Design for Transient Performance
Transmission Gates and Pass Transistors

Introduction to VLSI Circuits and Systems, NCUT 2007

 Transmission Gates

RTG = max( Rn , R p ) (7. 186)

C in = C S ,n + C D , p (7. 187)

Large ratio of (W/L) decrease the resistance, but

a large W implies large capacitances (a) Circuit

(b) RC model

Figure 7.37 Transmission gate modeling

Introduction to VLSI Circuits and Systems, NCUT 2007

 Pass Transistor
Pass FETs can be used in place of transmission
gates in most circuits
Less area and wiring, but cannot pass the entire
voltage range

t / 2 n
Vout (t ) = Vmax (7. 188) t f = ln(19) n 2.94 n (7. 195)
1 + t / 2 n
t r 6t f (7. 196) Figure 7.38 nFET pass transistor
where Vmax = V DD VTn (7. 189)

lim Vout (t ) = Vmax (7. 190) t r = 2.94 p (7. 197)

t

n = Rn C out (7. 191) where p = R p C out (7. 198)

t r = 18 n (7. 192) Vmin = VTp (7. 199)

2e (t / n )
Vout (t ) = Vmax (7. 193) t f = 18 p (7. 200)
( t / n )
1+ e
Figure 7.39 Voltage waveforms
lim Vout (t ) = 0 (7. 194) for a nFET pass transistor
t

Introduction to VLSI Circuits and Systems, NCUT 2007