Computer Organisation and

Architecture

Processor Organisation and

Architecture
 Topics to be covered
CPU Architecture
Register Organisation
Instruction Formats
 Things CPU must do.....
Fetch Instructions CPU reads instruction from
memory.
Decode (Interpret)Instructions instruction is
decoded to determine what action is required.
Fetch data- reading data from memory or I/O
module.
Process data some ALU operations.
Write data result of instruction may require
data to be written on to memory or I/O module.
Need of a small internal memory
It must remember the location of the last
instruction so that it can know where to get an
instruction it needs.
To store instruction and data temporarily when
an instruction is being executed.
Internal memory consisting of a set of storage
locations called Registers.
Within the CPU there is a set of registers that
function as a level of memory above main
memory and cache in the hierarchy.
 Example of a CPU activities
mul x, y, product

Fetch the instruction code from memory.

Decode the instruction. This reveals that it's a
multiply instruction, and that the operands are in
memory locations x, y, and product.
Fetch x and y from memory.
Multiply x and y, storing the result in a CPU
register.
Save the result from the CPU to memory location
product.
Structure of CPU
CPU Internal Structure : ALU , Internal
CPU Bus and Control Unit
ALU: Status flags ,shifter , complementer,
arthimetic and boolean logic.
Internal CPU bus to pass data back and forth
between components of the CPU.
Control Unit: managing operations of all CPU
components.
Registers: Temporary storage or working
space.
 Register Organisation
CPU must have some working space (temporary storage) called
registers to remember things:
Data being operated on
Pointers to memory(code,stack,data)
Machine code of current instruction
It functions as a level of memory above main memory and cache in
the hierarchy.
Number and functions may vary between processor designs.
One of the major design decisions.
These registers in the CPU perform two roles :
User Visible Registers : allow for operations with minimal
interaction with the main memory.
Control and Status Registers : with correct privileges ,can be set by
programmer . Lesser privileges may provide read-only capability.
Different Microprocessor Register
Organisation
 Segment and offset registers of 8086

Contents Of Registers inside 8086 processor are:

CS: 4000;SS:6000;ES:7000;DS:5000;SI:2350;SP:1306;
IP:1250;DI:8260;BP:1508
1.Calculate the starting and ending addresses of each segment?
2.Calculate the address of the present memory location in each
segment?
3.What is the effective address of stack segment area in
sequential mode and random access mode?
 User Visible Registers
These Registers can be used during
assembly language programming.
Compiler too makes use of these register to
generate an efficient code.
Types:
General Purpose
Data
Address
Condition Codes
 General Purpose Registers
It can be assigned to a variety of functions by the programmer.
Can be used for data or addressing purpose (Indirect).
Example:data: accumulator .....mov AX,04 H
Example: Indirect addressing:Base register....... mov CX,[BX] where
BX=FFFF H ....address calculated=DS*10+BX
If you use them as general purpose:
Increase flexibility and programmer options
Increase instruction size & complexity
If you use them as specialised registers:
Smaller (faster) instructions
less flexibility
Normally number varies from 4-32 from low processors to higher
end processors.
Ex: In 8086:AX,BX,CX,DX
Why do almost all new architectures
use GPRs?
Registers are much faster than memory (even
cache)
Register values are available immediately
When memory isnt ready, processor must wait (stall)
Registers are convenient for variable storage
Compiler assigns some variables just to registers
Ex: while executing a loop CX=can hold the count value.
 Data registers
May be used only to hold data and cannot be
employed in the circulation of any operand
address.
Data registers should be able to hold values of
most data types , some machine allows two
continuous registers to be used as one for
holding double length values.
Ex:In 8086 AX=AH:AL
 Address Registers
May be used for a particular addressing mode ( the
way in which the operand of an instruction is
specified).
Registers that must hold addresses obviously must be
at least long enough to hold the target address.
A)Segment registers: hold the starting address of various
segment areas.ex:SS,DS,ES,CS
B) Index Registers : These are used for index addressing
Ex:SI,DI
C) Pointer Registers: In case of an user visible stack
addressing ,these points to the stack in the memory.
Ex : SP ,BP(exception :IP)
 Condition Codes Registers
Sets of individual bits each time with a unique
purpose.(ex:result of last operation was zero)
Branch instructions can read flag values to determine
the outcome of last operation (ex:branch if result was
not equal)
Most are set automatically as a result of operation .
Ex:carry ,zero,parity
Some processors allow user to set or clear them
explicitly. Ex: STC: Set carry flag, CLC: clear carry flag
Collected into group and referred to as a single
register(CCR),which makes storing easier on stack if
required.
 Control and Status Registers
There are a variety of CPU registers that are
employed to control the operations of CPU ,
most of these on most machine are not visible
to the user.
Some of these may be visible to machine
instruction execution in a control or OS mode.
 Control Register
Four registers are used for movement of data between CPU
and memory
Program counter (PC) :
contains the address of the next instruction to be fetched.
automatically increments as a part of operation as current
instruction.
Can also be changed as a result of jump instruction.
Instruction Register (IR) :
contains the instruction most recently fetched.
where the instruction decoder examines opcode to figure
out what to do next.
Memory address register (MAR) :
contains the current address of a location in memory
which either holds data or instruction.
Memory buffer register (MBR) :
contains last word read from memory (instruction or data)
may also contain word to be stored to memory.
 Status Registers
All CPU designs includes a register or set of registers often known
as the Program Status word (Flag) that contains status
information.
The PSW contains condition codes and other status information .
It includes: Sign of last result, Zero ,Carry ,equal,
Overflow ,Interrupt enable/disable, Supervisor
Sign contain the sign bit of the result of latest arithmetic
operation.
Zero set when the result is Zero
Carry set if an operation resulted in a carry into or borrow out of
high order bit used for multiword arithmetic operations.
Equal set if a logical compare result in equality.
Overflow used to indicate arithmetic overflow.
Interrupt enable/disable used to enable/disable interrupts.
Supervisor CPU executes in supervisory /user mode
 Important Terminologies
Instruction : is an order given to a processor by
a program.
Instruction Set:The complete collection of
instructions that are understood by a CPU.
Machine language: binary representation of
operations and (addresses of) arguments.
Assembly language: mnemonic representation for
humans, e.g.,
Ex: ADD R1,R2,R3
 Instruction Format
Elements of an instruction:
Includes opcode.
Includes (implicit or explicit) operand(s) : source
and destination.
Ex: ADD AX,BX(explicit) and MUL BX(implicit)
Usually more than one instruction format in an
instruction set.
Instruction Format : Layout of bits in an
instruction.
Instruction Format based on number
of address referred
Three Addresses:
Not common
Needs very long words to hold everything
Normally arithmetic or logical instruction
Ex:ADD R1,R2,R3 and AND R1,R2,R3
Two Addresses:
One address doubles as operand and result
Reduces length of instruction
Very common in instruction sets.
In 8086:EX: ADD AX,BX and OR AX,DX
 Instruction Format based on number
of address referred
One address:
When only a single reference is allowed in an instruction
,another reference must be included as a part of the
instruction.
Traditionally these are accumulator based operations
In 8086:Ex: MUL BX: multiplies AX*BX ,result in DX:AX and
DIV BL: Divides AX/BL ,remainder in AH and quotient in AL
Zero Address:
All addresses are implicit or implied.
In 8086:Ex:STC:Set carry flag and PUSHF(Push flags onto
stack ) or POPF(Pop flags off stack)
 Design Issues in deciding the
Instruction Format
Instruction Length:
Longer instruction length gives more opcodes and more operands which
makes programming easier for programmer but requires more space to
store it ie. increases memory size.
Length of the instruction should match the speed of processor ie. If
instructions are short then they can be accessed in one clock cycle.
Increase in instruction length increases the processor complexity.
The instruction length should be equal to or multiple of the memory
transfer length ie. data bus width.
Gives trade-off between powerful instruction set and saving space.
Instruction length can be fixed or variable.
Variable instruction length : Provides flexibility ,gives optimum memory
storage but may increase the CPU complexity.
 Design Issues in deciding the
Instruction Format
Allocation of bits for different fields in an
instruction:
Increase in the number of bits for opcodes increases the no .
of instructions. As the no. of CPU registers increase ,the
opcodes also increase.
More operand fields (or bits in it) increases more data
handling.
When the fields are related to registers rather than memory ,
execution speed increases.