VLSI Technology and Application

Title : VLSI Technology and Applications

Code : 15B11EC414
L-T-P : 3 10
Credits : 4
Pre-requisites : Basic semiconductor devices
Syllabus
 EVALUATION SYSTEM
1. Test 1 1h 20
2. Test 2 1h 20
3. Test - 3 2h 35
4. Attendance 10
5. Tutorial & Assignments 10
6. Discipline 5
Total 100
 GRADES
A+ Outstanding
A Excellent
B+ Very Good
B Good
C+ Average
C Below Average
D Marginal
F Fail
 ATTENDANCE
Min. Requirement : 80 %

Otherwise F Grade will be awarded,

Irrespective of your performance in Tests.

Evolution of VLSI
and
VLSI Design Flow
 Historical overview

1954, 1st Silicon Transistor, cost $2.50.

1961, 1st IC( FF circuit), cost $50.

1961-1966 : SSI era, 90-150 Tr/C, FF, Gates.

1967-1971 : MSI, 100-1000 Tr/C, Adders, counters and 1K
RAM chip by Intel.

1972-1978 : LSI, 1K-20K Tr/C, 4-8bit Ps, ROM.

1978-1985 : VLSI, 20K-500K Tr/C, 16-32bit Ps,
sophisticated peripherals.
 Moores Law
Gordon
Moore
predicted
that number
of transistors
per chip will
increase at an
exponential
rate.

Transistor
counts have
doubled
every 18
months
 Beyond Moores Law

Moore, in an attempt to keep his law effective, formulated

Moore's Second Law, which says that facility costs increase on a
semi-log scale.
Or

Every additional doubling of device complexity increases

manufacturing costs exponentially.
 Clock Frequency

10000

1000 2X every 2 years

P6
Frequency (Mhz)

100
Pentium proc
486
10 8085 386
8086 286

1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
Courtesy, Intel
 Power Dissipation

100

P6
Pentium proc
Power (Watts)

10
486
8086 286
386
8085
1 8080
8008
4004

0.1
1971 1974 1978 1985 1992 2000
Year

Courtesy, Intel
 Disciplines contributed towards
VLSI Design
Solid-state physics.
Materials science.
Lithography and fab.
Device modeling.
Architecture.
Algorithms.
CAD tools.
Circuit design & layout.
 Why VLSI??

Less die area, compactness

Less power consumption

Less testing requirements at the system level

Higher speed, due to reduced interconnect length

Significant cost savings

 VLSI Issues
VLSI Fact #1:
So much to do, so little time
VLSI fact #2

Theres a lot that needs checking

Circuit must operate at all corners verified at building

block level.

Logic must be correct, operate reliably verified at RTL/gate

level.

Chip has to interoperate with system verified at behavioural

level.

Chip has to be manufacturable and verified at mask level, at

tester.
VLSI fact #3

One cant explore the behaviour of the circuit under all

possible conditions

Some of the bugs arise from unanticipated interactions

which, by definition, one never thinks of testing.

Its not clear when one is done looking for bugs!

Time pressures mean that most searches stop too soon.

Solution ???????

Choose a simple clocking scheme

Disallow un-clocked feedback
 Dealing with complexity

Divide-and-conquer: limit the number of components you

deal with at any one time.

Group several components into larger components:

transistors form gates;
gates form functional units;
functional units form processing elements;
etc.
 VLSI Design Cycle

System Specification Circuit Design

Architectural Design Physical Design

Functional Design Fabrication

Logic Design Packaging

 VLSI Design Cycle cont

System Specification Specification of the size, speed, power

and functionality of the VLSI system.

Architectural Design Decisions on the architecture, e.g.,

RISC/CISC, pipeline structure, cache size, etc.

Such decisions can provide an accurate estimation of the

system performance, die size, power consumption, etc.
 VLSI Design Cycle cont

Functional Design Identify main functional units and their

interconnections. No details of implementation.
 VLSI Design Cycle cont

Logic Design Design the logic, e.g., boolean expressions,

control flow, word width, register allocation, etc.

The outcome is called an RTL (Register Transfer Level)

description. RTL is expressed in a HDL (Hardware Description
Language), e.g., VHDL and Verilog.

X = (AB+CD)(E+F)
Y= (A(B+C) + Z + D)
 VLSI Design Cycle cont.

Circuit Design Design the circuit including gates, transistors,

interconnections, etc. The outcome is called a netlist.
 VLSI Design Cycle cont.

Component hierarchy

top

i1 xxx i2
 VLSI Design Cycle cont.

Physical Design Convert the netlist into a geometric

representation. The outcome is called a layout.
 VLSI Design Cycle cont.
Fabrication Process includes lithography, polishing,
deposition, diffusion, etc., to produce a chip.

Packaging Put together the chips on a PCB (Printed Circuit

Board) or an MCM (Multi-Chip Module)
The fermi potential, is the difference (in volts) between Ef and Efi and is given
by

The potential s is called the surface potential; it is the difference (in volts)
between Ef measured in the bulk semiconductor and Ef; measured at the
surface. The surface potential is the potential difference across the space charge
layer.
When
The electron concentration at the surface is the same as the hole
concentration in the bulk material. This condition is known as
threshold inversion point. The applied gate voltage creating this
condition is known as the threshold voltage.
Question
Question
The flatband voltage is the applied gate voltage such that there is no
band bending in the semiconductor and, as a result, zero net space
charge in this region.
There is zero net charge in the semiconductor and we can assume
that an equivalent fixed surface charge density exists in the oxide.