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Vlsi Design

This document outlines the syllabus for a course on VLSI design. The syllabus covers 5 units: [1] basic electrical properties of MOS and BiCMOS circuits, [2] VLSI design processes and layout diagrams, [3] gate-level design including logic gates and timing, [4] data path subsystem design such as adders and multipliers, and [5] array subsystems, integrated circuit design including PLA/FPGA, and CMOS testing techniques.

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Shoukath Ali
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127 views1 page

Vlsi Design

This document outlines the syllabus for a course on VLSI design. The syllabus covers 5 units: [1] basic electrical properties of MOS and BiCMOS circuits, [2] VLSI design processes and layout diagrams, [3] gate-level design including logic gates and timing, [4] data path subsystem design such as adders and multipliers, and [5] array subsystems, integrated circuit design including PLA/FPGA, and CMOS testing techniques.

Uploaded by

Shoukath Ali
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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VLSI DESIGN (A60432)

SYLLABUS:-

INTRODUCTION : Introduction to IC Technology MOS, PMOS, NMOS,


CMOS & BiCMOS technologies

Unit-I BASIC ELECTRICAL PROPERTIES :Basic Electrical Properties of MOS and


BiCMOS Circuits: Ids-Vds relationships, MOS transistor threshold Voltage, gm,
gds, figure of merit Wo; Pass transistor, NMOS Inverter, Various pull ups, CMOS
Inverter analysis and design, Bi-CMOS Inverters.

VLSI CIRCUIT DESIGN PROCESSES : VLSI Design Flow, MOS Layers,


Stick Diagrams, Design Rules and Layout, 2 um CMOS Design rules for wires,
Unit-II
Contacts and Transistors Layout Diagrams for NMOS and CMOS Inverters and
Gates, Scaling of MOS circuits.

GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic,
Unit-III Alternate gate circuits, Time delays, Driving large Capacitive Loads, Wiring
Capacitances, Fan-in and fan-out, Choice of layers
DATA PATH SUBSYSTEM DESIGN: Subsystem Design, Shifters, Adders,
ALUs, Multipliers, Parity generators, Comparators, Zero/One Detectors, Counters
Unit-IV
ARRAY SUB SYSTEMS: SRAM, DRAM, ROM, Serial access memories,
Content addressable memory

SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN: PLAs, FPGAs,


CPLDs, Standard Cells, Programmable Array Logic, Design Approach,
Parameters influencing low power design.
Unit-V
CMOS TESTING : CMOS Testing, Need for testing, Test Principles, Design
Strategies for test, Chip level Test Techniques, System-level Test Techniques,
Layout Design for improved Testability.

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