Fundamental Algorithms

for System Modeling,

Analysis, and Optimization

Edward A. Lee, Jaijeet Roychowdhury,

Sanjit A. Seshia
UC Berkeley
EECS 144/244
Fall 2010

Copyright 2010, E. A. Lee, J. Roychowdhury, S. A.

Seshia, All rights reserved

Lec 15: Testing for Fault Detection/Diagnosis

Thanks to K.-T. Cheng, S. Devadas, K. Keutzer for some slides

Fault Detection and Diagnosis

A fault is the adjudged or hypothesized cause of a
system failure.
Fault detection (is there a fault?) and diagnosis (where is
the fault?) are key steps in system design and
maintenance.

Integrated Circuits
Faults: manufacturing defects or electrical effects
Control Systems (e.g. chemical process plants)
Faulty sensors or actuators, operator error, mechanical failures
Cyber-Physical Systems (e.g., cars, spacecraft)
Faulty sensors/actuators, mechanical failures,

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 Fault Detection and Diagnosis

Propagation
(observability)

OUTPUTS
INPUTS

Vc VE
Component
X
...

...
Activation
(controllability)
Overall System

Observability and Controllability

Controllability
A system with internal state x is called controllable if
the state can be modified by changing the input to the
system.
E.g., for circuits: put a 0 or 1 at an arbitrary internal
node

Observability
A system with internal state x is called observable if
the state can be determined by observing the outputs
of the system.
E.g., for circuits, observe the 0-1 value of an internal
node from system outputs.
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 Manufacture Testing in ICs
?
Apply a sequence of input vectors to a circuit
Observe the output response and compare the
response with a precomputed or expected
response
Any discrepancy is said to constitute an error, the
cause of which is a physical defect

a 0 d

b
1
FAB

s clk

Defects and Fault models

Manufacturing defects can manifest in a variety of ways:
Bridging
Contaminants
Shorts
Opens
Transistors stuck-open
These need to be reduced to models:
Single stuck-at-1, stuck-at-0
Multiple stuck-at-1, stuck-at-0
Delay fault models:
Gate
Path
single-stuck-at fault model ubiquitous
some use of delay fault modeling
6
 Defect Model: Stuck-At Faults

A a b
B f1

C f2
D

Any input or internal wire in circuit can be

stuck-at-1 or stuck-at-0
Single stuck-at-fault model: In the faulty
circuit, a single line/wire is S-a-0 or S-a-1
Multiple stuck-at fault model: In the faulty
circuit any subset of wires are S-a-0/S-a-1
(in any combination)

Outline of Topics
Basics & Terminology

Single stuck-at faults and path sensitization

Boolean Satisfiability-based technique

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Formal Problem Definition
Given a combinational circuit on n variables x1, x2, , xn
with m outputs f1, f2, , fm
Let g be an internal net that is stuck at 0

Then, we wish to find values of x1, x2, , xn such that

g(x1, x2, , xn) = 1
and there exists some j in 1,2,m, such that
fj(x1, x2, , xn) takes different values depending on
whether g is stuck at 0 or not.

How does the definition change for g stuck at 1 ?

Problem: What about the Flip-Flops?

Solution 1: Unroll the sequential ckt in time

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[Murray & Hayes, IEEE Computer, 1996]
Solution 2: Add scan logic
add additional state to flip-flops
(15 - 20% area overhead)

Scan-chain Scan Flip-flops Scan-chain

inputs Combinational outputs

Logic

[See Murray & Hayes, IEEE Computer, 1996]

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Outline of Topics
Basics & Terminology

Single stuck-at faults and path sensitization

Boolean Satisfiability-based technique

12
Single Stuck-At Faults

A fault is assumed to occur only on a single net.

G
x1
a
x2 Z = x1 x2 + x2 x3
b
x3

x1 G
a a s-a-1 Z = ?
x2
x3 b G s-a-1 Z = ?

This model is used because it has been found to be

statistically correlated with defect-free circuits
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Single Stuck-At Faults

A fault is assumed to occur only on a single net.

G
x1
a
x2 Z = x1 x2 + x2 x3
b
x3

x1 G
a a s-a-1 Z = x1 + x2x3
x2
x3 b G s-a-1 Z = x2x3

This model is used because it has been found to be

statistically correlated with defect-free circuits
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Activation and Path Sensitization
In order for an input vector X to detect a fault h
s-a-D, D = 0,1 the input X must cause the
signal h in the normal (fault-free) circuit to
take the value D.

x2 h s-a-1
x
x3
x1
f
x4

To activate the fault i.e., detect h s-a-1

we first need to make h = 0. How?

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Fault Activation

x2 G1 h
x 0/1
x3 G3 0/1
x1 G5
G2 f
G4
0/1
x4

h s-a-1, for h to be 0, need x2 = x3 = 0 ( x 2 x3 )

The condition is necessary but not sufficient.

Error signal must be propagated to output
(must affect the output value).

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Fault Propagation
The error signal must be propagated along
some path from its origin to an output
x2 G1 h
x 0/1
x3 G3
x1 G5
G2 f
G4
x4

h s-a-1, for h to be 0, need x2 = x3 = 0 ( x 2 x3 )

How to propagate the fault?

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Fault Propagation
The error signal must be propagated along
some path from its origin to an output
x2 G1 h
x 0/1
x3 G3 0/1
x1 G5
G2 1 f
G4
0/1
x4 0

h s-a-1, for h to be 0, need x2 = x3 = 0 ( x 2 x3 )

Only one path G3, G5

In order to propagate an error through AND
gate G3, other input x1 = 1. To propagate
through G5, need G4 = 0, x1 + x4
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Formal Problem Definition, Revisited
Given a combinational circuit on n variables x1, x2, , xn
with m outputs f1, f2, , fm
Let g be an internal net that is stuck at 0

Then, we wish to find values of x1, x2, , xn such that

g(x1, x2, , xn) = 1 ACTIVATION (Controllability)
and there exists some j in 1,2,m, such that
fj(x1, x2, , xn) takes different values depending on
whether g is stuck at 0 or not.
PROPAGATION
(Observability)

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Single Path Sensitization (SPS)

1. Activate: Specify inputs so as to generate the
appropriate value (0 for s-a-1, 1 for s-a-0) at the
site of the fault.

2. Propagate: Select a path from the site of the

fault to an output and specify additional signal
values to propagate the fault signal along this
path to the output
(error propagation).

3. Justify: Specify input values so as to produce

the signal values specified in (2)
(line justification).

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Sensitization Example
G2 G5
D
f1
A G1
B x G6
C h s-a-1 f2
G3 G4
E
h s-a-1
Activate?

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Sensitization Example
G2 G5
D
f1
A G1 h
B x G6
C
f2
G3 G4
E
h s-a-1
Activate: To generate h = 0, need A = B = C = 1
Propagate?

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Sensitization Example
G2 G5
D
f1
A G1 h
B x G6
C
f2
G3 G4
E
h s-a-1
To generate h = 0, need A = B = C = 1
Have a choice of propagating through G5 or via G6.
Propagating through G5 requires G2 = 1
A = D = 0 Contradiction
Propagating through G6 requires G4 = 1 C = 1, E = 0.
A valid test vector is ABCE
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Line Justification
B G3
H
A
F 1
G2 G4

1
C
D x
0 E s-a-1 G1

E s-a-1 E = 0
C = D = 1 to propagate through G1.
To propagate through G4, need G2 = G3 = 1
How do we justify these values?
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Line Justification - 2
B G3
H
A
F 1
G2 G4

1
C G1
D x
0 E s-a-1
Attempt to line justify G2 = G3 = 1
G3 = 1 possible if A = F = 1 or B = H = 1
If A = C = 1, then G2 = 0.
G3 = 1 B = H = 1
G2 = 1 needs A = 0 or F = 0
Tests are ABCDEH, BCDEFH
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Redundancy
Not all faults result in failures!
Existence of a fault does not change the
functionality of a circuit redundant fault

x1
s-a-1 f
x x1 f
x2 x2

f = x1 + x1 x2 f = x1 + x2

A test generation algorithm is deemed complete

if it either finds a test for any fault or proves
its redundancy, upon terminating.

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Completeness of SPS method ?
G2
C
G3 G6
G1 d
A f
x G4
B s-a-0
G5
E

d s-a-0 A = B = 1
Propagate along G3, G6 C = 1
G2 = G4 = G5 = 1
For G4 = 1 either its top input = 0 or E = 0
If G1 = 0 fault is not activated (dont want to force G1 = 0)
If E = 0 (B must be 1) G5 = 0 Inconsistency
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Completeness of SPS? - 2
G2
C
G3 G6
d f
A x G4
B s-a-0
G5
E

Propagation along G4, G6 also results in

inconsistencies by symmetric argument
Is there no test?
How about C = E = 1?
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 Multiple Path Sensitization

1
G2
1
0/1
1 d 1/0 G3 G6 f
x
1 s-a-0 G4 1/0
0/1
1 G5
1
Error propagates down two paths G3, G6 and G4, G6
to output (G3, G4 values are correlated)
Its natural to work backwards (justifying) and
forwards (propagating) from point of fault
activation but this focuses on sensitizing a
single path
Attempting to sensitize a single path will not find a
test for this fault
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Note on the D-Algebra/ D-calculus

Need to be able to deal with an arbitrary

error at the inputs to a gate
D represents a signal which has value 1 in
normal circuit, and value 0 in faulty
circuit.
D 0/1
D D D D D 0
D D D

D 0 D D D 0
0 1 0

D, D behave like Boolean variables

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Outline of Topics
Basics & Terminology

Single stuck-at faults and path sensitization

Boolean Satisfiability-based technique

31

Another approach to ATPG (Larrabee, 1989)

The ATPG problem (automatic test pattern generation)

The CIRCUIT-SAT problem

The Boolean Satisfiability (SAT) problem

CIRCUIT-SAT

ATPG SAT

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The ATPG problem
Circuit C
A logic circuit
1 a 1
h A fault point
0 b f
0(1)
0 c A fault value
1 d s-a-1
i
g 0(1)
f , s a 1
0 e 1

Does there exist a value assignment to the primary

inputs which distinguishes the faulty and correct
circuits ?

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The CIRCUIT-SAT problem

a
h
b f
c

d g i
e

Does there exist a value assignment to the

primary inputs which causes the primary output
to assume logic value 1 ?

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ATPG as a CIRCUIT-SAT problem
Can we find an input value in which the faulty circuit and
the good circuit differ?

hf
if
1

a t = 1?
h
b f
c
d g
e
i Circuit CATPG

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The Boolean Satisfiability (SAT) problem

Given a formula, f :
Defined over a set of variables, V (a,b,c)
Comprised of a conjunction (AND) of clauses (C1,C2,C3)
Each clause is a disjunction (OR) of literals of the
variables V
Does there exist an assignment of Boolean values to
the variables, V which sets at least one literal in each
clause to 1 ?

Example : ( a b c)( a c )( a b c ) a=b=c=1

C1 C2 C3
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CIRCUIT-SAT as a SAT problem
A set of clauses representing the functionality of each
gate
A unit literal (i) clause asserting the output to be 1

a (b f )( c f )(b c f )
h
b f ( d g )( e g )( d e g )
c ( a h )( f h )( a f h )
d g i ( h i )( g i )( h g i )
e
(i )

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Solving the SAT problem

NP-complete problem, yet efficient techniques exist to
solve probems encountered in practice

We will review some of these methods in the next lecture

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Current Status on Manufacture Test
Practical approach to test: use scan achieve 99%+
stuck-at coverage
Single stuck-at-fault testing for combinational logic is a
``solved problem
Despite the fact that it is NP-complete
After 20+ years of research
Results applied to combinational-equivalence
checking

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