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Pci

The document discusses the peripheral component interconnect (PCI) bus standard. PCI is a high-bandwidth processor-independent bus used for connecting I/O devices. It supports both single and multiple processor systems and uses synchronous timing and centralized arbitration. Data transfers on PCI use address and data phases, and arbitration for bus access uses a request-grant handshake with the central arbiter.

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49 views6 pages

Pci

The document discusses the peripheral component interconnect (PCI) bus standard. PCI is a high-bandwidth processor-independent bus used for connecting I/O devices. It supports both single and multiple processor systems and uses synchronous timing and centralized arbitration. Data transfers on PCI use address and data phases, and arbitration for bus access uses a request-grant handshake with the central arbiter.

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ef.manu
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PCI

The peripheral component interconnect (PCI) is a popular high-


bandwidth, processor-independent bus that can function as a
mezzanine or peripheral bus. Compared with other common bus
specifications, PCI delivers better system performance for high-
speed I/O subsystems (e.g., graphic display adapters, network
interface controllers, disk controllers, and so on).The current
standard allows the use of up to 64 data lines at 66 MHz. PCI is
specifically designed to meet economically the I/O requirements
of modern systems. PCI is designed to support a variety of
microprocessor-based configurations, including both single- and
multiple-processor systems. Accordingly, it provides a general-
purpose set of functions. It makes use of synchronous timing and
a centralized arbitration scheme.

In the above figure a combined DRAM controller and bridge to the


PCI bus provides tight coupling with the processor and the ability
to deliver data at high speeds. The bridge acts as a data buffer so
that the speed of the PCI bus may differ from that of the
processors I/O capability. In a multiprocessor system (Figure
3.22b), one or more PCI configurations may be connected by
bridges to the processors system bus.

PCI Bus Structure


PCI may be configured as a 32- or 64-bit bus and it contains 49
mandatory signal lines. These are divided into the following
functional groups:

System pins: Include the clock and reset pins.


Address and data pins: Include 32 lines that are time
multiplexed for addresses and data.
Interface control pins: Control the timing of transactions and
provide coordination among initiators and targets
Arbitration pins: They are not shared pins and each PCI
master has its own pair of arbitration lines that connect it
directly to the PCI bus arbiter.
Error reporting pins: Used to report parity and other errors.

In addition, the PCI specification defines 51 optional signal lines,


divided into following functional groups

Interrupt pins: These are provided for PCI devices that must
generate requests for service and each PCI device has its
own interrupt line or lines to an interrupt controller.
Cache support pins: These pins are needed to support a
memory on PCI that can be cached in the processor or
another device
64-bit bus extension pins: Include 32 lines that are time
multiplexed for addresses and data and that are combined
with the mandatory address/data lines to form a 64-bit
address/data bus
JTAG/boundary scan pins: These signal lines support testing
procedures defined in IEEE Standard 1149.1.

PCI Commands
Bus activity occurs in the form of transactions between
an initiator, or master, and a target. When a bus master
acquires control of the bus, it determines the type of
transaction that will occur next. During the address phase
of the transaction, the C/BE lines are used to signal the
transaction type. The main command groups are given
below:

Interrupt Acknowledge: a read command intended for


the device that functions as an interrupt controller on
the PCI bus. Byte enable(BE) lines indicate the size of
the interrupt identifier to be returned
Special Cycle: By the initiator to broadcast a
message to one or more targets.
I/O Read, I/O Write : are used to transfer data
between the initiator and an I/O controller
Memory Read, Memory Write: are used to specify the
transfer of a burst of data, occupying one or more
clock cycles. PCI bus supports the PCI protocol for
transfers between memory and cache
Memory Read: Bursting 2 data transfer cycles or less
Memory Read Line : Bursting 3 to 12 data transfers
Memory Read Multiple: Bursting more than 12 data
transfers
Memory Write and Invalidate : Transfers data in one
or more cycles to memory
Configuration Read, Configuration Write : commands
enable a master to read and update configuration
parameters in a device connected to the PCI
Dual address Cycle: used by an initiator to indicate
that it is using 64-bit addressing.
Data Transfers
Every data transfer on the PCI bus is a single transaction
consisting of one address phase and one or more data phases.

Eg: Read Operation

All events are synchronized to the falling transitions of the clock,


which occur in the middle of each clock cycle

STEPS:

a. Once a bus master has gained control of the bus, it may


begin the transaction by asserting FRAME. The initiator also
puts the start address on the address bus, and the read
command on the C/BE lines.
b. At the start of clock 2, the target device will recognize its
address on the AD lines
c. The initiator ceases driving the AD bus. The initiator changes
the information on the C/BE lines to designate which AD lines
are to be used for transfer for the currently addressed data.
The initiator also asserts IRDY to indicate that it is ready for
the first data item.
d. The selected target asserts DEVSEL to indicate that it has
recognized its address and will respond. It places the
requested data on the AD lines and asserts TRDY to indicate
that valid data are present on the bus.
e. The initiator reads the data at the beginning of clock 4 and
changes the byte enable lines as needed in preparation for
the next read.
f. The target needs some time to prepare the second block of
data for transmission.Therefore, it deasserts TRDY to signal
the initiator that there will not be new data during the
coming cycle
g. During clock 6, the target places the third data item on the
bus. the initiator is not yet ready to read the data item. It
therefore deasserts IRDY.
h. The initiator knows that the third data transfer is the last,
and so it deasserts FRAME
i. The initiator deasserts IRDY, returning the bus to the idle
state

Arbitration
PCI makes use of a centralized, synchronous arbitration scheme in
which each master has a unique request (REQ) and grant (GNT)
signal. These signal lines are attached to a central arbiter and a
simple requestgrant handshake is used to grant access to the
bus.
The arbiter can use a first-come-first-served approach, a round-
robin approach, or some sort of priority scheme. A PCI master
must arbitrate for each transaction that it wishes to perform,
where a single transaction consists of an address phase followed
by one or more contiguous data phases. Notice that arbitration
can take place at the same time that the current bus master is
performing a data transfer. Therefore, no bus cycles are lost in
performing arbitration. This is referred to as hidden arbitration

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