0% found this document useful (0 votes)
136 views31 pages

DDL Codes Labs

The document describes VHDL models for various digital logic gates and components. It includes models for basic gates like AND, OR, XOR, drivers, as well as more complex components like multiplexers, decoders, and a tri-state driver. For each component, two different VHDL descriptions are provided using either behavioral modeling with if/else statements or direct logic functions.

Uploaded by

saim
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
136 views31 pages

DDL Codes Labs

The document describes VHDL models for various digital logic gates and components. It includes models for basic gates like AND, OR, XOR, drivers, as well as more complex components like multiplexers, decoders, and a tri-state driver. For each component, two different VHDL descriptions are provided using either behavioral modeling with if/else statements or direct logic functions.

Uploaded by

saim
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
You are on page 1/ 31

(-----DRIVER-----)

-- driver (ESD book figure 2.3)


--
-- two descriptions provided
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------
entity Driver is
port( x: in std_logic;
F: out std_logic
);
end Driver;
----------------------------------------
architecture behv1 of Driver is
begin
process(x)
begin
-- compare to truth table
if (x='1') then
F <= '1';
else
F <= '0';
end if;
end process;
end behv1;
architecture behv2 of Driver is
begin
F <= x;
end behv2;
(-----OR GATE-----)

-- OR gate (ESD book figure 2.3)


--
-- two descriptions provided
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity OR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end OR_ent;
---------------------------------------
architecture OR_arch of OR_ent is
begin
process(x, y)
begin
-- compare to truth table
if ((x='0') and (y='0')) then
F <= '0';
else
F <= '1';
end if;
end process;
end OR_arch;
architecture OR_beh of OR_ent is
begin
F <= x or y;
end OR_beh;

(-----AND GATE-----)
-- AND gate (ESD book figure 2.3)
-- two descriptions provided
--------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------
entity AND_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end AND_ent;
--------------------------------------------------
architecture behav1 of AND_ent is
begin
process(x, y)
begin
-- compare to truth table
if ((x='1') and (y='1')) then
F <= '1';
else
F <= '0';
end if;
end process;
end behav1;
architecture behav2 of AND_ent is
begin
F <= x and y;
end behav2;

(-----XOR GATE-----)

-- XOR gate (ESD figure 2.3)


--
-- two descriptions provided
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity XOR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end XOR_ent;
--------------------------------------
architecture behv1 of XOR_ent is
begin
process(x, y)
begin
-- compare to truth table
if (x/=y) then
F <= '1';
else
F <= '0';
end if;
end process;
end behv1;
architecture behv2 of XOR_ent is
begin
F <= x xor y;
end behv2;

(-----NOR GATE-----)

-- NOR gate (ESD figure 2.3)


--
-- two descriptions provided
-----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------
entity NOR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end NOR_ent;
------------------------------------------
architecture behv1 of NOR_ent is
begin
process(x, y)
begin
-- compare to truth table
if (x='0' and y='0') then
F <= '1';
else
F <= '0';
end if;
end process;
end behv1;
architecture behv2 of NOR_ent is
begin
F <= x nor y;
end behv2;

(-----NAND GATE-----)

-- NAND gate (ESD figure 2.3)


--
-- two descriptions provided
-----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------
entity NAND_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end NAND_ent;
------------------------------------------
architecture behv1 of NAND_ent is
begin
process(x, y)
begin
-- compare to truth table
if (x='1' and y='1') then
F <= '0';
else
F <= '1';
end if;
end process;
end behv1;
-----------------------------------------
architecture behv2 of NAND_ent is
begin
F <= x nand y;
end behv2;

(-----XNOR GATE-----)

-- XOR gate (ESD figure 2.3)


--
-- two descriptions provided
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity XNOR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end XNOR_ent;
---------------------------------------
architecture behv1 of XNOR_ent is
begin
process(x, y)
begin
-- compare to truth table
if (x/=y) then
F <= '0';
else
F <= '1';
end if;
end process;
end behv1;
architecture behv2 of XNOR_ent is
begin
F <= x xnor y;
end behv2;

(-----Combinational Logic-----)

-- Combinational Logic Design


-- (ESD book figure 2.4)
-- by Weijun Zhang, 04/2001
--
-- A simple example of VHDL Structure Modeling
-- we might define two components in two separate files,
-- in main file, we use port map statement to instantiate
-- the mapping relationship between each components
-- and the entire circuit.
------------------------------------------------------------
library ieee; -- component #1
use ieee.std_logic_1164.all;
entity OR_GATE is
port( X: in std_logic;
Y: in std_logic;
F2: out std_logic
);
end OR_GATE;
architecture behv of OR_GATE is
begin
process(X,Y)
begin
F2 <= X or Y; -- behavior des.
end process;
end behv;
-------------------------------------------------------------
library ieee; -- component #2
use ieee.std_logic_1164.all;
entity AND_GATE is
port( A: in std_logic;
B: in std_logic;
F1: out std_logic
);
end AND_GATE;
architecture behv of AND_GATE is
begin
process(A,B)
begin
F1 <= A and B; -- behavior des.
end process;
end behv;
--------------------------------------------------------------
library ieee; -- top level circuit
use ieee.std_logic_1164.all;
use work.all;
entity comb_ckt is
port( input1: in std_logic;
input2: in std_logic;
input3: in std_logic;
output: out std_logic
);
end comb_ckt;
architecture struct of comb_ckt is
component AND_GATE is -- as entity of AND_GATE
port( A: in std_logic;
B: in std_logic;
F1: out std_logic
);
end component;
component OR_GATE is -- as entity of OR_GATE
port( X: in std_logic;
Y: in std_logic;
F2: out std_logic
);
end component;
signal wire: std_logic; -- signal just like wire
begin
-- use sign "=>" to clarify the pin mapping
Gate1: AND_GATE port map (A=>input1, B=>input2, F1=>wire);
Gate2: OR_GATE port map (X=>wire, Y=>input3, F2=>output);
end struct;

(-----Tri-State Driver-----)

-- VHDL model for tri state driver


-- by Weijun Zhang, 05/2001
--
-- this friver often used to control system outputs
---------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tristate_dr is
port( d_in: in std_logic_vector(7 downto 0);
en: in std_logic;
d_out: out std_logic_vector(7 downto 0)
);
end tristate_dr;
architecture behavior of tristate_dr is
begin
process(d_in, en)
begin
if en='1' then
d_out <= d_in;
else
-- array can be created simply by using vector
d_out <= "ZZZZZZZZ";
end if;
end process;
end behavior;

(-----Signal/Variable Example-----)

-- Signal vs. Variable (sig_var.vhd)


-- Look at the outputs in simulation waveform
-- for same computation, we get two different results
--
-- by Weijun Zhang, 05/2001
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity sig_var is
port( d1, d2, d3: in std_logic;
res1, res2: out std_logic);
end sig_var;
architecture behv of sig_var is
signal sig_s1: std_logic;
begin
proc1: process(d1,d2,d3)
variable var_s1: std_logic;
begin
var_s1 := d1 and d2;
res1 <= var_s1 xor d3;
end process;

proc2: process(d1,d2,d3)
begin
sig_s1 <= d1 and d2;
res2 <= sig_s1 xor d3;
end process;
end behv;

(----- Multiplexor-----)

-------------------------------------------------
-- VHDL code for 4:1 multiplexor
-- (ESD book figure 2.5)
-- by Weijun Zhang, 04/2001
--
-- Multiplexor is a device to select different
-- inputs to outputs. we use 3 bits vector to
-- describe its I/O ports
-------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------
entity Mux is
port( I3: in std_logic_vector(2 downto 0);
I2: in std_logic_vector(2 downto 0);
I1: in std_logic_vector(2 downto 0);
I0: in std_logic_vector(2 downto 0);
S: in std_logic_vector(1 downto 0);
O: out std_logic_vector(2 downto 0)
);
end Mux;
-------------------------------------------------
architecture behv1 of Mux is
begin
process(I3,I2,I1,I0,S)
begin
-- use case statement
case S is
when "00" => O <= I0;
when "01" => O <= I1;
when "10" => O <= I2;
when "11" => O <= I3;
when others => O <= "ZZZ";
end case;
end process;
end behv1;
architecture behv2 of Mux is
begin
-- use when.. else statement
O <= I0 when S="00" else
I1 when S="01" else
I2 when S="10" else
I3 when S="11" else
"ZZZ";
end behv2;
--------------------------------------------------

(----- Decoder-----)

-------------------------------------------------
-- 2:4 Decoder (ESD figure 2.5)
-- by Weijun Zhang, 04/2001
--
-- decoder is a kind of inverse process
-- of multiplexor
-------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------
entity DECODER is
port( I: in std_logic_vector(1 downto 0);
O: out std_logic_vector(3 downto 0)
);
end DECODER;
-------------------------------------------------
architecture behv of DECODER is
begin
-- process statement
process (I)
begin
-- use case statement
case I is
when "00" => O <= "0001";
when "01" => O <= "0010";
when "10" => O <= "0100";
when "11" => O <= "1000";
when others => O <= "XXXX";
end case;
end process;
end behv;
architecture when_else of DECODER is
begin
-- use when..else statement
O <= "0001" when I = "00" else
"0010" when I = "01" else
"0100" when I = "10" else
"1000" when I = "11" else
"XXXX";
end when_else;
--------------------------------------------------

(----- Adder-----)

--------------------------------------------------------
-- VHDL code for n-bit adder (ESD figure 2.5)
-- by Weujun Zhang, 04/2001
--
-- function of adder:
-- A plus B to get n-bit sum and 1 bit carry
-- we may use generic statement to set the parameter
-- n of the adder.
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------
entity ADDER is
generic(n: natural :=2);
port( A: in std_logic_vector(n-1 downto 0);
B: in std_logic_vector(n-1 downto 0);
carry: out std_logic;
sum: out std_logic_vector(n-1 downto 0)
);
end ADDER;
--------------------------------------------------------
architecture behv of ADDER is
-- define a temparary signal to store the result
signal result: std_logic_vector(n downto 0);
begin
-- the 3rd bit should be carry
result <= ('0' & A)+('0' & B);
sum <= result(n-1 downto 0);
carry <= result(n);
end behv;
--------------------------------------------------------

(----- Comparator-----)

---------------------------------------------------
-- n-bit Comparator (ESD book figure 2.5)
-- by Weijun Zhang, 04/2001
--
-- this simple comparator has two n-bit inputs &
-- three 1-bit outputs
---------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
---------------------------------------------------
entity Comparator is
generic(n: natural :=2);
port( A: in std_logic_vector(n-1 downto 0);
B: in std_logic_vector(n-1 downto 0);
less: out std_logic;
equal: out std_logic;
greater: out std_logic
);
end Comparator;
---------------------------------------------------
architecture behv of Comparator is
begin
process(A,B)
begin
if (A<B) then
less <= '1';
equal <= '0';
greater <= '0';
elsif (A=B) then
less <= '0';
equal <= '1';
greater <= '0';
else
less <= '0';
equal <= '0';
greater <= '1';
end if;
end process;
end behv;
---------------------------------------------------

(-----ALU-----)

---------------------------------------------------
-- Simple ALU Module (ESD book Figure 2.5)
-- by Weijun Zhang, 04/2001
--
-- ALU stands for arithmatic logic unit.
-- It perform multiple operations according to
-- the control bits.
-- we use 2's complement subraction in this example
-- two 2-bit inputs & carry-bit ignored
---------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
---------------------------------------------------
entity ALU is
port( A: in std_logic_vector(1 downto 0);
B: in std_logic_vector(1 downto 0);
Sel: in std_logic_vector(1 downto 0);
Res: out std_logic_vector(1 downto 0)
);
end ALU;
---------------------------------------------------
architecture behv of ALU is
begin
process(A,B,Sel)
begin
-- use case statement to achieve
-- different operations of ALU
case Sel is
when "00" =>
Res <= A + B;
when "01" =>
Res <= A + (not B) + 1;
when "10" =>
Res <= A and B;
when "11" =>
Res <= A or B;
when others =>
Res <= "XX";
end case;
end process;
end behv;
----------------------------------------------------

(-----Multiplier-----)

--------------------------------------------------------
-- Example of doing multiplication showing
-- (1) how to use variable with in process
-- (2) how to use for loop statement
-- (3) algorithm of multiplication
--
-- by Weijun Zhang, 05/2001
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- two 4-bit inputs and one 8-bit outputs
entity multiplier is
port( num1, num2: in std_logic_vector(1 downto 0);
product: out std_logic_vector(3 downto 0)
);
end multiplier;
architecture behv of multiplier is
begin
process(num1, num2)
variable num1_reg: std_logic_vector(2 downto 0);
variable product_reg: std_logic_vector(5 downto 0);
begin
num1_reg := '0' & num1;
product_reg := "0000" & num2;
-- use variables doing computation
-- algorithm is to repeat shifting/adding
for i in 1 to 3 loop
if product_reg(0)='1' then
product_reg(5 downto 3) := product_reg(5 downto 3)
+ num1_reg(2 downto 0);
end if;
product_reg(5 downto 0) := '0' & product_reg(5 downto 1);
end loop;
-- assign the result of computation back to output signal
product <= product_reg(3 downto 0);
end process;
end behv;

(-----Simple Latch-----)

--------------------------------------------
-- Simple D Latch (ESD book Chapter 2.3.1)
-- by Weijun Zhang, 04/2001
--
-- latch is simply controlled by enable bit
-- but has nothing to do with clock sigal
-- notice this difference from flip-flops
--------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
--------------------------------------------
entity D_latch is
port( data_in: in std_logic;
enable: in std_logic;
data_out: out std_logic
);
end D_latch;
--------------------------------------------
architecture behv of D_latch is
begin
-- compare this to D flipflop
process(data_in, enable)
begin
if (enable='1') then
-- no clock signal here
data_out <= data_in;
end if;
end process;
end behv;
--------------------------------------------

(-----D Flip-Flop-----)

---------------------------------------------
-- D Flip-Flop (ESD book Chapter 2.3.1)
-- by Weijun Zhang, 04/2001
--
-- Flip-flop is the basic component in
-- sequential logic design
-- we assign input signal to the output
-- at the clock rising edge
---------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use work.all;
---------------------------------------------
entity dff is
port( data_in: in std_logic;
clock: in std_logic;
data_out: out std_logic
);
end dff;
----------------------------------------------
architecture behv of dff is
begin
process(data_in, clock)
begin
-- clock rising edge
if (clock='1' and clock'event) then
data_out <= data_in;
end if;
end process;
end behv;
----------------------------------------------

(-----JK Flip-Flop-----)

----------------------------------------------
-- JK Flip-Flop with reset
-- (ESD book Chapter 2.3.1)
-- by Weijun Zhang, 04/2001
--
-- the description of JK Flip-Flop is based
-- on functional truth table
-- concurrent statement and signal assignment
-- are using in this example
----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------
entity JK_FF is
port ( clock: in std_logic;
J, K: in std_logic;
reset: in std_logic;
Q, Qbar: out std_logic
);
end JK_FF;
-----------------------------------------------
architecture behv of JK_FF is
-- define the useful signals here
signal state: std_logic;
signal input: std_logic_vector(1 downto 0);
begin
-- combine inputs into vector
input <= J & K;
p: process(clock, reset) is
begin
if (reset='1') then
state <= '0';
elsif (rising_edge(clock)) then
-- compare to the truth table
case (input) is
when "11" =>
state <= not state;
when "10" =>
state <= '1';
when "01" =>
state <= '0';
when others =>
null;
end case;
end if;
end process;
-- concurrent statements
Q <= state;
Qbar <= not state;
end behv;
-------------------------------------------------
(-----Register-----)

---------------------------------------------------
-- n-bit Register (ESD book figure 2.6)
-- by Weijun Zhang, 04/2001
--
-- KEY WORD: concurrent, generic and range
---------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------
entity reg is
generic(n: natural :=2);
port( I: in std_logic_vector(n-1 downto 0);
clock: in std_logic;
load: in std_logic;
clear: in std_logic;
Q: out std_logic_vector(n-1 downto 0)
);
end reg;
----------------------------------------------------
architecture behv of reg is
signal Q_tmp: std_logic_vector(n-1 downto 0);
begin
process(I, clock, load, clear)
begin
if clear = '0' then
-- use 'range in signal assigment
Q_tmp <= (Q_tmp'range => '0');
elsif (clock='1' and clock'event) then
if load = '1' then
Q_tmp <= I;
end if;
end if;
end process;
-- concurrent statement
Q <= Q_tmp;
end behv;
---------------------------------------------------
(-----Shift Register-----)

---------------------------------------------------
-- 3-bit Shift-Register/Shifter
-- (ESD book figure 2.6)
-- by Weijun Zhang, 04/2001
--
-- reset is ignored according to the figure
---------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
---------------------------------------------------
entity shift_reg is
port( I: in std_logic;
clock: in std_logic;
shift: in std_logic;
Q: out std_logic
);
end shift_reg;
---------------------------------------------------
architecture behv of shift_reg is
-- initialize the declared signal
signal S: std_logic_vector(2 downto 0):="111";
begin
process(I, clock, shift, S)
begin
-- everything happens upon the clock changing
if clock'event and clock='1' then
if shift = '1' then
S <= I & S(2 downto 1);
end if;
end if;
end process;
-- concurrent assignment
Q <= S(0);
end behv;
----------------------------------------------------

(----- Counter-----)
----------------------------------------------------
-- VHDL code for n-bit counter (ESD figure 2.6)
-- by Weijun Zhang, 04/2001
--
-- this is the behavior description of n-bit counter
-- another way can be used is FSM model.
----------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
----------------------------------------------------
entity counter is
generic(n: natural :=2);
port( clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(n-1 downto 0)
);
end counter;
----------------------------------------------------
architecture behv of counter is
signal Pre_Q: std_logic_vector(n-1 downto 0);
begin
-- behavior describe the counter
process(clock, count, clear)
begin
if clear = '1' then
Pre_Q <= Pre_Q - Pre_Q;
elsif (clock='1' and clock'event) then
if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;
-- concurrent assignment statement
Q <= Pre_Q;
end behv;
-----------------------------------------------------

(-----FSM Model-----)

-----------------------------------------------------
-- VHDL FSM (Finite State Machine) modeling
-- (ESD book Figure 2.7)
-- by Weijun Zhang, 04/2001
--
-- FSM model consists of two concurrent processes
-- state_reg and comb_logic
-- we use case statement to describe the state
-- transistion. All the inputs and signals are
-- put into the process sensitive list.
-----------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
-----------------------------------------------------
entity seq_design is
port( a: in std_logic;
clock: in std_logic;
reset: in std_logic;
x: out std_logic
);
end seq_design;
-----------------------------------------------------
architecture FSM of seq_design is
-- define the states of FSM model
type state_type is (S0, S1, S2, S3);
signal next_state, current_state: state_type;
begin
-- cocurrent process#1: state registers
state_reg: process(clock, reset)
begin
if (reset='1') then
current_state <= S0;
elsif (clock'event and clock='1') then
current_state <= next_state;
end if;
end process;
-- cocurrent process#2: combinational logic
comb_logic: process(current_state, a)
begin
-- use case statement to show the
-- state transistion
case current_state is
when S0 => x <= '0';
if a='0' then
next_state <= S0;
elsif a ='1' then
next_state <= S1;
end if;
when S1 => x <= '0';
if a='0' then
next_state <= S1;
elsif a='1' then
next_state <= S2;
end if;
when S2 => x <= '0';
if a='0' then
next_state <= S2;
elsif a='1' then
next_state <= S3;
end if;
when S3 => x <= '1';
if a='0' then
next_state <= S3;
elsif a='1' then
next_state <= S0;
end if;
when others =>
x <= '0';
next_state <= S0;
end case;
end process;
end FSM;
-----------------------------------------------------

(-----RAM Module-----)

--------------------------------------------------------------
-- a simple 4*4 RAM module (ESD book Chapter 5)
-- by Weijun Zhang
--
-- KEYWORD: array, concurrent processes, generic, conv_integer
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------
entity SRAM is
generic( width: integer:=4;
depth: integer:=4;
addr: integer:=2);
port( Clock: in std_logic;
Enable: in std_logic;
Read: in std_logic;
Write: in std_logic;
Read_Addr: in std_logic_vector(addr-1 downto 0);
Write_Addr: in std_logic_vector(addr-1 downto 0);
Data_in: in std_logic_vector(width-1 downto 0);
Data_out: out std_logic_vector(width-1 downto 0)
);
end SRAM;
--------------------------------------------------------------
architecture behav of SRAM is
-- use array to define the bunch of internal temparary signals
type ram_type is array (0 to depth-1) of
std_logic_vector(width-1 downto 0);
signal tmp_ram: ram_type;
begin
-- Read Functional Section
process(Clock, Read)
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Read='1' then
-- buildin function conv_integer change the type
-- from std_logic_vector to integer
Data_out <= tmp_ram(conv_integer(Read_Addr));
else
Data_out <= (Data_out'range => 'Z');
end if;
end if;
end if;
end process;
-- Write Functional Section
process(Clock, Write)
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Write='1' then
tmp_ram(conv_integer(Write_Addr)) <= Data_in;
end if;
end if;
end if;
end process;
end behav;
----------------------------------------------------------------

(-----ROM Module-----)
--------------------------------------------------------------
-- 32*8 ROM module (ESD Book Chapter 5)
-- by Weijun Zhang, 04/2001
--
-- ROM model has predefined content for read only purpose
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ROM is
port( Clock : in std_logic;
Reset : in std_logic;
Enable : in std_logic;
Read : in std_logic;
Address : in std_logic_vector(4 downto 0);
Data_out: out std_logic_vector(7 downto 0)
);
end ROM;
--------------------------------------------------------------
architecture Behav of ROM is
type ROM_Array is array (0 to 31)
of std_logic_vector(7 downto 0);
constant Content: ROM_Array := (
0 => "00000001", -- Suppose ROM has
1 => "00000010", -- prestored value
2 => "00000011", -- like this table
3 => "00000100", --
4 => "00000101", --
5 => "00000110", --
6 => "00000111", --
7 => "00001000", --
8 => "00001001", --
9 => "00001010", --
10 => "00001011", --
11 => "00001100", --
12 => "00001101", --
13 => "00001110", --
14 => "00001111", --
OTHERS => "11111111" --
);
begin
process(Clock, Reset, Read, Address)
begin
if( Reset = '1' ) then
Data_out <= "ZZZZZZZZ";
elsif( Clock'event and Clock = '1' ) then
if Enable = '1' then
if( Read = '1' ) then
Data_out <= Content(conv_integer(Address));
else
Data_out <= "ZZZZZZZZ";
end if;
end if;
end if;
end process;
end Behav;
--------------------------------------------------------------

(-----GCD Caculator -----)

-----------------------------------------------------
-- Behvaior Design of GCD calculator
-- by Weijun Zhang, 05/2001
-----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.all;
-----------------------------------------------------
entity gcd1 is
port( Data_X: in unsigned(3 downto 0);
Data_Y: in unsigned(3 downto 0);
Data_out: out unsigned(3 downto 0)
);
end gcd1;
architecture behv of gcd1 is
begin
process(Data_X, Data_Y)
variable tmp_X, tmp_Y: unsigned(3 downto 0);
begin
tmp_X := Data_X;
tmp_Y := Data_Y;
for i in 0 to 15 loop
if (tmp_X/=tmp_Y) then
if (tmp_X < tmp_Y) then
tmp_Y := tmp_Y - tmp_X;
else
tmp_X := tmp_X - tmp_Y;
end if;
else
Data_out <= tmp_X;
end if;
end loop;
end process;
end behv;
-----------------------------------------------------

(-----Four Bit Adder Illustrating a hierarchical VHDL model-----)


-- Example of a four bit adder
library ieee;
use ieee.std_logic_1164.all;
-- definition of a full adder
entity FULLADDER is
port (a, b, c: in std_logic;
sum, carry: out std_logic);
end FULLADDER;
architecture fulladder_behav of FULLADDER is
begin
sum <= (a xor b) xor c ;
carry <= (a and b) or (c and (a xor b));
end fulladder_behav;
-- 4-bit adder
library ieee;
use ieee.std_logic_1164.all;
entity FOURBITADD is
port (a, b: in std_logic_vector(3 downto 0);
Cin : in std_logic;
sum: out std_logic_vector (3 downto 0);
Cout, V: out std_logic);
end FOURBITADD;
architecture fouradder_structure of FOURBITADD is
signal c: std_logic_vector (4 downto 0);
component FULLADDER
port(a, b, c: in std_logic;
sum, carry: out std_logic);
end component;
begin
FA0: FULLADDER
port map (a(0), b(0), Cin, sum(0), c(1));
FA1: FULLADDER
port map (a(1), b(1), C(1), sum(1), c(2));
FA2: FULLADDER
port map (a(2), b(2), C(2), sum(2), c(3));
FA3: FULLADDER
port map (a(3), b(3), C(3), sum(3), c(4));
V <= c(3) xor c(4);
Cout <= c(4);
end fouradder_structure;

(----- Full Adder composed of two Half Adders, modeled with two processes P1 and
P2.------)
library ieee;
use ieee.std_logic_1164.all;
entity FULL_ADDER is
port (A, B, Cin : in std_logic;
Sum, Cout : out std_logic);
end FULL_ADDER;
architecture BEHAV_FA of FULL_ADDER is
signal int1, int2, int3: std_logic;
begin
-- Process P1 that defines the first half adder
P1: process (A, B)
begin
int1<= A xor B;
int2<= A and B;
end process;
-- Process P2 that defines the second half adder and the OR -- gate
P2: process (int1, int2, Cin)
begin
Sum <= int1 xor Cin;
int3 <= int1 and Cin;
Cout <= int2 or int3;
end process;
end BEHAV_FA;

(-----entity MUX_4_1a is-----)

port (S1, S0, A, B, C, D: in std_logic;


Z: out std_logic);
end MUX_4_1a;
architecture behav_MUX41a of MUX_4_1a is
begin
P1: process (S1, S0, A, B, C, D)
begin
if (( not S1 and not S0 )= 1 ) then
Z <= A;
elsif (( not S1 and S0) = 1 ) then
Z<=B;
elsif ((S1 and not S0) = 1 ) then
Z <=C;
else
Z<=D;
end if;
end process P1;
end behav_MUX41a;
A slightly different way of modeling the same multiplexer is shown below,
if S1= 0 and S0= 0 then
Z <= A;
elsif S1= 0 and S0= 1 then
Z <= B;
elsif S1= 1 and S0= 0 then
Z <= C;
elsif S1= 1 and S0= 1 then
Z <= D;
end if;
(-----An example of a case statement using an enumerated type follows. It gives
an output D=1 when the signal GRADES has a value between 51 and 60, C=1 for grad
es between 61 and 70, the when others covers all the other grades and result in
an F=1.
library ieee;
use ieee.std_logic_1164.all;
entity GRD_201 is
port(VALUE: in integer range 0 to 100;
A, B, C, D: out bit);
end GRD_201;
architecture behav_grd of GRD_201 is
begin
process (VALUE)
A <= 0 ;
B <= 0 ;
C <= 0 ;
D <= 0 ;
F <= 0 ;
begin
case VALUE is
when 51 to 60 =>
D <= 1 ;
when 61 to 70 | 71 to 75 =>
C <= 1 ;
when 76 to 85 =>
B <= 1 ;
when 86 to 100 =>
A <= 1 ;
when others =>
F <= 1 ;
end case;
end process;
end behav_grd;
We used the vertical bar ( | ) which is equivalent to the or operator, to illustra
te how to express a range of values. This is a useful operator to indicate range
s that are not adjacent (e.g. 0 to 4 | 6 to 10).
Another example using the case construct is a 4-to-1 MUX.
entity MUX_4_1 is
port ( SEL: in std_logic_vector(2 downto 1);
A, B, C, D: in std_logic;
Z: out std_logic);
end MUX_4_1;
architecture behav_MUX41 of MUX_4_1 is
begin
PR_MUX: process (SEL, A, B, C, D)
begin
case SEL is
when 00 => Z <= A;
when 01 => Z <= B;
when 10 => Z <= C;
when 11 => Z <= D;
when others => Z <= X ;
end case;
end process PR_MUX;
end behav_MUX41;
(------Example of a basic loop to implement a counter that counts from 0 to 31
entity COUNT31 is--------)
port ( CLK: in std_logic;
COUNT: out integer);
end COUNT31;
architecture behav_COUNT of COUNT31 is
begin
P_COUNT: process
variable intern_value: integer :=0;
begin
COUNT <= intern_value;
loop
wait until CLK= 1 ;
intern_value:=(intern_value + 1) mod 32;
COUNT <= intern_value;
end loop;
end process P_COUNT;
end behav_COUNT;

(-----Example of a Four bit Adder using concurrent/behavioral modeling-----)

library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ADD4 is
port (
A: in STD_LOGIC_VECTOR (3 downto 0);
B: in STD_LOGIC_VECTOR (3 downto 0);
CIN: in STD_LOGIC;
SUM: out STD_LOGIC_VECTOR (3 downto 0);
COUT: out STD_LOGIC
);
end ADD4;
architecture ADD4_concurnt of ADD4 is
-- define internal SUM signal including the carry
signal SUMINT: STD_LOGIC_VECTOR(4 downto 0);
begin
-- <<enter your statements here>>
SUMINT <= ('0' & A) + ('0' & B) + ("0000" & CIN);
COUT <= SUMINT(4);
SUM <= SUMINT(3 downto 0);
end ADD4_concurnt;
(------VHDL file for a sequence detector (1011) implemented as a Mealy Machine
library ieee;
use ieee.std_logic_1164.all;
entity myvhdl is
port (CLK, RST, X: in STD_LOGIC;
Z: out STD_LOGIC);
end;
architecture myvhdl_arch of myvhdl is
-- SYMBOLIC ENCODED state machine: Sreg0
type Sreg0_type is (S1, S2, S3, S4);
signal Sreg0: Sreg0_type;
begin
--concurrent signal assignments
Sreg0_machine: process (CLK)
begin
if CLK'event and CLK = '1' then
if RST='1' then
Sreg0 <= S1;
else
case Sreg0 is
when S1 =>
if X='0' then
Sreg0 <= S1;
elsif X='1' then
Sreg0 <= S2;
end if;
when S2 =>
if X='1' then
Sreg0 <= S2;
elsif X='0' then
Sreg0 <= S3;
end if;
when S3 =>
if X='1' then
Sreg0 <= S4;
elsif X='0' then
Sreg0 <= S1;
end if;
when S4 =>
if X='0' then
Sreg0 <= S3;
elsif X='1' then
Sreg0 <= S2;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
-- signal assignment statements for combinatorial outputs
Z_assignment:
Z <= '0' when (Sreg0 = S1 and X='0') else
'0' when (Sreg0 = S1 and X='1') else
'0' when (Sreg0 = S2 and X='1') else
'0' when (Sreg0 = S2 and X='0') else
'0' when (Sreg0 = S3 and X='1') else
'0' when (Sreg0 = S3 and X='0') else
'0' when (Sreg0 = S4 and X='0') else
'1' when (Sreg0 = S4 and X='1') else
'1';
end myvhdl_arch;

You might also like