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Prerequisite: EC207 Logic Circuit Design

The document describes a Computer Organization course with the code EC206. The course is a 3 credit hour course introduced in 2016. The objectives are to impart knowledge about processor design, architecture, programming concepts, and I/O and memory structures. The syllabus covers topics like functional units, arithmetic circuits, processor architecture, instructions, memory concepts, and I/O accessing techniques across 6 modules. The course aims for students to understand computer structure, memory types, and various computer design techniques.

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113 views2 pages

Prerequisite: EC207 Logic Circuit Design

The document describes a Computer Organization course with the code EC206. The course is a 3 credit hour course introduced in 2016. The objectives are to impart knowledge about processor design, architecture, programming concepts, and I/O and memory structures. The syllabus covers topics like functional units, arithmetic circuits, processor architecture, instructions, memory concepts, and I/O accessing techniques across 6 modules. The course aims for students to understand computer structure, memory types, and various computer design techniques.

Uploaded by

plbonifus
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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COURSE COURSE NAME L-T-P-C YEAR OF

CODE INTRODUCTION
EC206 Computer Organisation 3-0-0-3 2016
Prerequisite: EC207 Logic circuit design

Course objectives:
To impart knowledge in different aspects of processor design.
To develop understanding about processor architecture.
To impart knowledge in programming concepts.
To develop understanding on I/O accessing techniques and memory structures.

Syllabus:
Functional units of a computer, Arithmetic Circuits, Processor architecture, Instructions and
addressing modes, Execution of program, micro architecture design process, design or data
path and control units, I/O accessing techniques, Memory concepts, memory interface, cash and
virtual memory concepts
Expected outcome:
The student should be able to:
Illustrate the structure of a computer
Categorize different types of memories
Explain various techniques in computer design.
Text Books:
1. David Money Harris, Sarah L Harris, Digital Design and Computer Architecture, Morgan
Kaufmann Elsevier, 2009

References:
1. William Stallings: Computer Organisation and Architecture, Pearson Education.
2. John P Hayes: Computer Architecture and Organisation, Mc Graw Hill.
3. Andrew S Tanenbaum: Structured Computer Organisation, Pearson Education.
4. Craig Zacker: PC Hardware : The Complete Reference, TMH.
5. Carl Hamacher : Computer Organization , Fifth Edition, Mc Graw Hill.
6. David A. Patterson and John L. Hennessey, Computer Organisation and Design, Fourth
Edition, Morgan Kaufmann.
Course Plan
Module Course content (42 hrs) Hours Sem. Exam
Marks
I Functional units of a computer: Arithmetic Circuits 4 15
Adder- Carry propagate adder, Ripple carry adder, Basics
of carry look ahead and prefix adder, Subtractor,
Comparator, ALU
Shifters and rotators, Multiplication, Division 3
Number System- Fixed Point & Floating Point 1
II Architecture Assembly Language, Instructions, Operands 2 15
Registers, Register set, Memory, Constants
Machine Language R-Type, I-Type, J-Type Instructions, 3
Interpreting Machine Language code
FIRST INTERNAL EXAM
III Addressing Modes register only, immediate, base, PC- 3 15
relative, Pseudo direct
Steps for Executing a Program Compilation, Assembling, 3
Linking, Loading
Pseudoinstuctions, Exceptions, Signed and Unsigned 3
Instructions, Floating Point Instructions
IV Microarchitecture- design process 2 15
Single cycle processor, Single cycle data path, single cycle 2
control
multi cycle processor, multi cycle data path, multi cycle 3
control
SECOND INTERNAL EXAM
V Memory & I/O systems I/O accessing techniques: 3 20
programmed, interrupt driven and DMA, DMA bus
arbitration
Memory Arrays Bit Cells, Organization, Memory Ports 3
Memory types- DRAM, SRAM, Register Files, ROM

VI Memory - Hierarchy, Performance analysis 1 20


Cache Memory direct mapped, multi way set associate 3
cache, Fully associate cache
Virtual Memory Address Translation, Page Table, 3
Translation Look aside Buffer, Memory Protection,
replacement polices
END SEMESTER EXAM

Question Paper Pattern

The question paper consists of three parts. Part A covers modules I and II, Part B covers modules
III and IV and Part C covers modules V and VI. Each part has three questions. Each question can
have a maximum of four subparts. Among the three questions one will be a compulsory question
covering both the modules and the remaining two questions will be as one question from each
module, of which one is to be answered. Mark pattern is according to the syllabus with
maximum 50 % for theory and 50% for logical/numerical problems, derivation and proof.

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