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Random Counter LFSR

The document describes an entity for a linear feedback shift register (LFSR) with an 8-bit output counter. The LFSR entity has ports for an enable signal, clock, reset, and 8-bit output. The architecture contains a signal for the linear feedback and a process that shifts the count on each clock edge when enabled, resetting the count on a high reset.

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0% found this document useful (0 votes)
55 views1 page

Random Counter LFSR

The document describes an entity for a linear feedback shift register (LFSR) with an 8-bit output counter. The LFSR entity has ports for an enable signal, clock, reset, and 8-bit output. The architecture contains a signal for the linear feedback and a process that shifts the count on each clock edge when enabled, resetting the count on a high reset.

Uploaded by

manish 123
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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library ieee;

use ieee.std_logic_1164.all;
entity lfsr is
port (
cout :out std_logic_vector (7 downto 0);-- Output of the counter
enable :in std_logic; -- Enable counting
clk :in std_logic; -- Input rlock
reset :in std_logic -- Input reset
);
end entity;
architecture rtl of lfsr is
signal count :std_logic_vector (7 downto 0);
signal linear_feedback :std_logic;
begin
linear_feedback <= not(count(7) xor count(3));

process (clk, reset) begin


if (reset = '1') then
count <= (others=>'0');
elsif (rising_edge(clk)) then
if (enable = '1') then
count <= (count(6) & count(5) & count(4) & count(3)
& count(2) & count(1) & count(0) &
linear_feedback);
end if;
end if;
end process;
cout <= count;
end architecture;

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