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System Task and Function: Verilog HDL Asic Design

This document discusses various system tasks and functions in Verilog used for input/output during simulation like $display, $strobe, $monitor, $time, $scope, $random, $dumpfile, $fopen. These tasks allow displaying values, setting scopes, generating random numbers, dumping variables to files during simulation.

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Arus Reddy
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25 views2 pages

System Task and Function: Verilog HDL Asic Design

This document discusses various system tasks and functions in Verilog used for input/output during simulation like $display, $strobe, $monitor, $time, $scope, $random, $dumpfile, $fopen. These tasks allow displaying values, setting scopes, generating random numbers, dumping variables to files during simulation.

Uploaded by

Arus Reddy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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System Task and Function http://www.asic-world.com/verilog/sys_task_func1.html#Intr...

System Task and Function


Feb-9-2014

Introduction
There are tasks and functions that are used to generate input and output during simulation. Their
names begin with a dollar sign ($). The synthesis tools parse and ignore system functions, and hence
can be included even in synthesizable models.

$display, $strobe, $monitor


These commands have the same syntax, and display text on the screen during simulation. They are
much less convenient than waveform display tools like GTKWave. or Undertow or Debussy. $display
and $strobe display once every time they are executed, whereas $monitor displays every time one of
its parameters changes. The difference between $display and $strobe is that $strobe displays the
parameters at the very end of the current simulation time unit rather than exactly when it is executed.
The format string is like that in C/C++, and may contain format characters. Format characters include
%d (decimal), %h (hexadecimal), %b (binary), %c (character), %s (string) and %t (time), %m
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(hierarchy level). %5d, %5b etc. would give exactly 5 spaces for the number instead of the space
Verilog HDL needed. Append b, h, o to the task name to change default format to binary, octal or hexadecimal.

Asic Design Syntax


Trade
Unlimited $display ("format_string", par_1, par_2, ... );
In F&O - $strobe ("format_string", par_1, par_2, ... );
Pay Zero $monitor ("format_string", par_1, par_2, ... );
$displayb (as above but defaults to binary..);
$strobeh (as above but defaults to hex..);
$monitoro (as above but defaults to octal..);

$time, $stime, $realtime


These return the current simulation time as a 64-bit integer, a 32-bit integer, and a real number,
respectively.

$reset, $stop, $finish


$reset resets the simulation back to time 0; $stop halts the simulator and puts it in interactive mode
where the user can enter commands; $finish exits the simulator back to the operating system.

$scope, $showscope
$scope(hierarchy_name) sets the current hierarchical scope to hierarchy_name. $showscopes(n) lists
all modules, tasks and block names in (and below, if n is set to 1) the current scope.

$random
$random generates a random integer every time it is called. If the sequence is to be repeatable, the
first time one invokes random giving it a numerical argument (a seed). Otherwise the seed is derived
from the computer clock.

$dumpfile, $dumpvar, $dumpon, $dumpoff, $dumpall


These can dump variable changes to a simulation viewer like Debussy. The dump files are capable of
dumping all the variables in a simulation. This is convenient for debugging, but can be very slow.

Syntax

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System Task and Function http://www.asic-world.com/verilog/sys_task_func1.html#Intr...

$dumpfile("filename.vcd")
$dumpvar dumps all variables in the design.
$dumpvar(1, top) dumps all the variables in module top and below, but not modules instantiated
in top.
$dumpvar(2, top) dumps all the variables in module top and 1 level below.
$dumpvar(n, top) dumps all the variables in module top and n-1 levels below.
$dumpvar(0, top) dumps all the variables in module top and all level below.
$dumpon initiates the dump.
$dumpoff stop dumping.

$fopen, $fdisplay, $fstrobe $fmonitor and $fwrite


These commands write more selectively to files.

$fopen opens an output file and gives the open file a handle for use by the other commands.
$fclose closes the file and lets other programs access it.
$fdisplay and $fwrite write formatted data to a file whenever they are executed. They are the
same except $fdisplay inserts a new line after every execution and $write does not.
$strobe also writes to a file when executed, but it waits until all other operations in the time step
are complete before writing. Thus initial #1 a=1; b=0; $fstrobe(hand1, a,b); b=1; will write write 1
1 for a and b.
$monitor writes to a file whenever any of its arguments changes.

Syntax

handle1=$fopen("filenam1.suffix")
handle2=$fopen("filenam2.suffix")
$fstrobe(handle1, format, variable list) //strobe data into filenam1.suffix
$fdisplay(handle2, format, variable list) //write data into filenam2.suffix
$fwrite(handle2, format, variable list) //write data into filenam2.suffix all on one line. Put in the
format string where a new line is desired.

Copyright 1998-2014
Deepak Kumar Tala - All rights reserved
Do you have any Comment? mail me at:[email protected]

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