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Single Port Ram Synchronous Read Write

This document describes a RAM module with synchronous read and write capabilities. It defines the module's ports including clock, address, data, chip select, write enable and output enable. It then defines the module's architecture using internal variables like a memory signal of type RAM and a data output signal. The architecture contains code for reading and writing to the RAM on the rising edge of the clock when the appropriate conditions are met like chip select active and write enable for writes or chip select and output enable for reads.

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manish 123
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181 views2 pages

Single Port Ram Synchronous Read Write

This document describes a RAM module with synchronous read and write capabilities. It defines the module's ports including clock, address, data, chip select, write enable and output enable. It then defines the module's architecture using internal variables like a memory signal of type RAM and a data output signal. The architecture contains code for reading and writing to the RAM on the rising edge of the clock when the appropriate conditions are met like chip select active and write enable for writes or chip select and output enable for reads.

Uploaded by

manish 123
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram_sp_ar_sw is
generic (
DATA_WIDTH :integer := 8;
ADDR_WIDTH :integer := 8
);
port (
clk :in std_logic; -- Clock Input
address :in std_logic_vector (ADDR_WIDTH-1 downto 0); -- address Inp
ut
data :inout std_logic_vector (DATA_WIDTH-1 downto 0); -- data bi-dir
ectional
cs :in std_logic; -- Chip Select
we :in std_logic; -- Write Enabl
e/Read Enable
oe :in std_logic -- Output Enab
le
);
end entity;
architecture rtl of ram_sp_ar_sw is
----------------Internal variables----------------
constant RAM_DEPTH :integer := 2**ADDR_WIDTH;
signal data_out :std_logic_vector (DATA_WIDTH-1 downto 0);
type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto
0);
signal mem : RAM (0 to RAM_DEPTH-1);
begin
----------------Code Starts Here------------------
-- Tri-State Buffer control
-- output : When we = 0, oe = 1, cs = 1
data <= data_out when (cs = '1' and oe = '1' and we = '0') else (others=>'Z'
);
-- Memory Write Block
-- Write Operation : When we = 1, cs = 1
MEM_WRITE:
process (clk) begin
if (rising_edge(clk)) then
if (cs = '1' and we = '1') then
mem(conv_integer(address)) <= data;
end if;
end if;
end process;
-- Memory Read Block
-- Read Operation : When we = 0, oe = 1, cs = 1
MEM_READ:
process (clk) begin
if (rising_edge(clk)) then
if (cs = '1' and we = '0' and oe = '1') then
data_out <= mem(conv_integer(address));
end if;
end if;
end process;
end architecture;

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