Book 4 Oscillators and Advanced Electronics Topics

Series ISSN: 1932-3166
SCHUBERT, JR. • KIM

Fundamentals of
Series Editor: Mitchell A. Thornton, Southern Methodist University
Fundamentals of Electronics: Book 4
Electronics: Book 4
Oscillators and Advanced Electronics Topics
FUNDAMENTALS OF ELECTRONICS: BOOK 4

Thomas F. Schubert, Jr., University of San Diego
Ernest M. Kim, University of San Diego
Oscillators and Advanced Electronics Topics is the final book of a larger, four-book set, Fundamentals
of Electronics. It consists of five chapters that further develop practical electronic applications Oscillators and Advanced
based on the fundamental principles developed in the first three books. This book begins by
extending the principles of electronic feedback circuits to linear oscillator circuits. The second
chapter explores non-linear oscillation, waveform generation, and waveshaping. The third
chapter focuses on providing clean, reliable power for electronic applications where voltage
Electronics Topics
regulation and transient suppression are the focus. Fundamentals of communication circuitry
form the basis for the fourth chapter with voltage-controlled oscillators, mixers, and phase-lock
loops being the primary focus. The final chapter expands upon early discussions of logic gate
operation (introduced in Book 1) to explore gate speed and advanced gate topologies.
Fundamentals of Electronics has been designed primarily for use in an upper division
course in electronics for electrical engineering students and for working professionals. Typically
such a course spans a full academic year consisting of two semesters or three quarters. As
such, Oscillators and Advanced Electronic Topics, and the first three books in the series, Electronic
Devices and Circuit Applications (ISBN 9781627055628), Amplifiers: Analysis and Design (ISBN
Thomas F. Schubert, Jr.
9781627055642), and Active Filters and Amplifier Frequency Response (ISBN 9781627055666)
Ernest M. Kim

form an appropriate body of material for such a course.
MORGAN & CLAYPOOL

About SYNTHESIS
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store.morganclaypool.com
Fundamentals of Electronics
Book 4
Oscillators and
Advanced Electronics Topics
Synthesis Lectures on Digital
Circuits and Systems
Editor
Mitchell A. ornton, Southern Methodist University
e Synthesis Lectures on Digital Circuits and Systems series is comprised of 50- to 100-page books
targeted for audience members with a wide-ranging background. e Lectures include topics that
are of interest to students, professionals, and researchers in the area of design and analysis of digital
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required to understand the subject matter and practical case studies that illustrate applications. e
format of a Lecture is structured such that each will be devoted to a specific topic in digital circuits
and systems rather than a larger overview of several topics such as that found in a comprehensive
handbook. e Lectures cover both well-established areas as well as newly developed or emerging
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Fundamentals of Electronics: Book 4 Oscillators and Advanced Electronics Topics

omas F. Schubert, Jr. and Ernest M. Kim
2016
Fundamentals of Electronics: Book 3 Active Filters and Amplifier Frequency

omas F. Schubert and Ernest M. Kim
2016
Bad to the Bone: Crafting Electronic Systems with BeagleBone and BeagleBone Black,
Second Edition
Steven F. Barrett and Jason Kridner
2015
Fundamentals of Electronics: Book 2 Amplifiers: Analysis and Design

2015
Fundamentals of Electronics: Book 1 Electronic Devices and Circuit Applications

2015
Applications of Zero-Suppressed Decision Diagrams

Tsutomu Sasao and Jon T. Butler
2014
iv
Modeling Digital Switching Circuits with Linear Algebra
Mitchell A. ornton
2014
Arduino Microcontroller Processing for Everyone! ird Edition

Steven F. Barrett
2013
Boolean Differential Equations

Bernd Steinbach and Christian Posthoff
2013
Bad to the Bone: Crafting Electronic Systems with BeagleBone and BeagleBone Black
Steven F. Barrett and Jason Kridner
2013
Introduction to Noise-Resilient Computing

S.N. Yanushkevich, S. Kasai, G. Tangim, A.H. Tran, T. Mohamed, and V.P. Shmerko
2013
Atmel AVR Microcontroller Primer: Programming and Interfacing, Second Edition

Steven F. Barrett and Daniel J. Pack
2012
Representation of Multiple-Valued Logic Functions

Radomir S. Stankovic, Jaakko T. Astola, and Claudio Moraga
2012
Arduino Microcontroller: Processing for Everyone! Second Edition

Steven F. Barrett
2012
Advanced Circuit Simulation Using Multisim Workbench

David Báez-López, Félix E. Guerrero-Castro, and Ofelia Delfina Cervantes-Villagómez
2012
Circuit Analysis with Multisim

David Báez-López and Félix E. Guerrero-Castro
2011
Microcontroller Programming and Interfacing Texas Instruments MSP430, Part I

2011
Microcontroller Programming and Interfacing Texas Instruments MSP430, Part II

2011
v
Pragmatic Electrical Engineering: Systems and Instruments
William Eccles
2011
Pragmatic Electrical Engineering: Fundamentals

William Eccles
2011
Introduction to Embedded Systems: Using ANSI C and the Arduino Development

Environment
David J. Russell
2010
Arduino Microcontroller: Processing for Everyone! Part II

Steven F. Barrett
2010
Arduino Microcontroller Processing for Everyone! Part I

Steven F. Barrett
2010
Digital System Verification: A Combined Formal Methods and Simulation Framework

Lun Li and Mitchell A. ornton
2010
Progress in Applications of Boolean Functions

Tsutomu Sasao and Jon T. Butler
2009
Embedded Systems Design with the Atmel AVR Microcontroller: Part II

Steven F. Barrett
2009
Embedded Systems Design with the Atmel AVR Microcontroller: Part I

Steven F. Barrett
2009
Embedded Systems Interfacing for Engineers using the Freescale HCS08 Microcontroller
II: Digital and Analog Hardware Interfacing
Douglas H. Summerville
2009
Designing Asynchronous Circuits using NULL Convention Logic (NCL)

Scott C. Smith and JiaDi
2009
vi
Embedded Systems Interfacing for Engineers using the Freescale HCS08 Microcontroller
I: Assembly Language Programming
Douglas H.Summerville
2009
Developing Embedded Software using DaVinci & OMAP Technology

B.I. (Raj) Pawate
2009
Mismatch and Noise in Modern IC Processes

Andrew Marshall
2009
Asynchronous Sequential Machine Design and Analysis: A Comprehensive Development

of the Design and Analysis of Clock-Independent State Machines and Systems
Richard F. Tinder
2009
An Introduction to Logic Circuit Testing

Parag K. Lala
2008
Pragmatic Power
William J. Eccles
2008
Multiple Valued Logic: Concepts and Representations

D. Michael Miller and Mitchell A. ornton
2007
Finite State Machine Datapath Design, Optimization, and Implementation

Justin Davis and Robert Reese
2007
Atmel AVR Microcontroller Primer: Programming and Interfacing

2007
Pragmatic Logic
William J. Eccles
2007
PSpice for Filters and Transmission Lines

Paul Tobin
2007
vii
PSpice for Digital Signal Processing
Paul Tobin
2007
PSpice for Analog Communications Engineering

Paul Tobin
2007
PSpice for Digital Communications Engineering

Paul Tobin
2007
PSpice for Circuit eory and Electronic Devices

Paul Tobin
2007
Pragmatic Circuits: DC and Time Domain

William J. Eccles
2006
Pragmatic Circuits: Frequency Domain

William J. Eccles
2006
Pragmatic Circuits: Signals and Filters

William J. Eccles
2006
High-Speed Digital System Design

Justin Davis
2006
Introduction to Logic Synthesis using Verilog HDL

Robert B.Reese and Mitchell A.ornton
2006
Microcontrollers Fundamentals for Engineers and Scientists

2006
Copyright © 2016 by Morgan & Claypool
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any form or by any means—electronic, mechanical, photocopy, recording, or any other except for brief quotations
in printed reviews, without the prior permission of the publisher.
Fundamentals of Electronics: Book 4 Oscillators and Advanced Electronics Topics

www.morganclaypool.com
ISBN: 9781627055680 paperback

ISBN: 9781627055697 ebook
DOI 10.2200/S00715ED1V04Y201604DCS050
A Publication in the Morgan & Claypool Publishers series

SYNTHESIS LECTURES ON DIGITAL CIRCUITS AND SYSTEMS
Lecture #50
Series Editor: Mitchell A. ornton, Southern Methodist University
Series ISSN
Print 1932-3166 Electronic 1932-3174
Fundamentals of Electronics
Book 3
Oscillators and
Advanced Electronics Topics

University of San Diego
SYNTHESIS LECTURES ON DIGITAL CIRCUITS AND SYSTEMS #50
M
&C Morgan & cLaypool publishers
ABSTRACT
is book, Oscillators and Advanced Electronics Topics, is the final book of a larger, four-book set,
Fundamentals of Electronics. It consists of five chapters that further develop practical electronic
applications based on the fundamental principles developed in the first three books.
is book begins by extending the principles of electronic feedback circuits to linear oscilla-
tor circuits. e second chapter explores non-linear oscillation, waveform generation, and wave-
shaping. e third chapter focuses on providing clean, reliable power for electronic applications
where voltage regulation and transient suppression are the focus. Fundamentals of communica-
tion circuitry form the basis for the fourth chapter with voltage-controlled oscillators, mixers,
and phase-lock loops being the primary focus. e final chapter expands upon early discussions
of logic gate operation (introduced in Book 1) to explore gate speed and advanced gate topologies.
Fundamentals of Electronics has been designed primarily for use in upper division courses
in electronics for electrical engineering students and for working professionals. Typically such
courses span a full academic year plus an additional semester or quarter. As such, Oscillators and
Advanced Electronics Topics and the three companion book of Fundamentals of Electronics form an
appropriate body of material for such courses.
KEYWORDS
oscillators, phase-shift oscillator, Wien-Bridge oscillator, Colpitts oscillator, Hart-
ley oscillator, multivibrator, waveform shaping, 555 timer, silicon controlled rectifier
(SCR), Triac, voltage regulator, transient suppression, overvoltage protection, analog
to digital conversion, voltage controlled oscillator (VCO), phase-locked look (PLL),
filter, modulator, demodulator, TTL, ECL
xi
Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv
12 Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925

12.1 Linear Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925
12.1.1 Design of Practical Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
12.1.2 Frequency Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928
12.2 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930
12.2.1 Phase-Shift Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930
12.2.2 Wien-Bridge Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
12.3 LC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
12.3.1 Colpitts Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
12.3.2 Hartley Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
12.4 Crystal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
12.5 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
12.6 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
13 Waveform Generation and Waveshaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969

13.1 Multivibrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970
13.1.1 Bistable Multivibrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970
13.1.2 Astable Multivibrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
13.1.3 Monostable Multivibrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
13.2 Generation of Square and Triangular Waveforms Using Astable
Multivibrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
13.2.1 Precision Square Wave Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
13.2.2 Simultaneous Square and Triangle Wave Generation . . . . . . . . . . . . . . 982
13.2.3 Voltage-Controlled Frequency of Oscillation . . . . . . . . . . . . . . . . . . . . . 984
13.3 Non-Linear Waveform Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
13.4 Integrated Circuit Multivibrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
13.4.1 A 555 Timer Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . 993
13.4.2 A 555 Timer Astable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
xii
13.5 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997
13.6 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
13.7 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008
14 Power Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011

14.1 yristors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
14.1.1 e Silicon Controlled Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
14.1.2 e Triac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
14.2 Voltage Regulator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
14.2.1 e Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
14.2.2 e Error Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
14.2.3 Linear Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
14.2.4 Switching Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025
14.3 Voltage Regulator Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
14.3.1 Extending the Capabilities of a Simple Voltage Regulator . . . . . . . . . 1032
14.4 Transient Suppression and Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . 1035
14.5 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
14.6 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
15 Communication Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051

15.1 Analog-To-Digital Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
15.1.1 Quantizing and Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
15.1.2 Quantizing Error and Sampling Frequency . . . . . . . . . . . . . . . . . . . . . 1053
15.1.3 Flash Analog-to-Digital Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054
15.2 Voltage-Controlled Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
15.3 Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
15.3.1 BJT Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
15.3.2 Dual Gate FET Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
15.4 Phase-Lock Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
15.5 Active and Passive Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
15.5.1 Passive LC Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
15.5.2 Tuned Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
15.6 Modulator/Demodulator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
15.7 Receiver Design Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093
xiii
15.9 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103
16 Digital Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105

16.1 e Switching Speed of Bipolar Junction Transistors . . . . . . . . . . . . . . . . . . . 1106
16.2 Bipolar Digital Gate Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112
16.2.1 TTL and DTL Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113
16.2.2 ECL Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1123
16.2.3 I2 L Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
16.3 Dynamic Properties of Metal Oxide Semiconductor Transistors . . . . . . . . . . 1128
16.4 MOS Digital Gate Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134
16.5 Bistable Logic Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145
16.6 Semiconductor Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1151
16.7 Gallium Arsenide Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154
16.9 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1161
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172
Authors’ Biographies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173

xv
Preface
is final book of this work focuses on four significant branches of electronic circuitry that are not
necessarily in the direct path taken by the three previous books. Each is particularly significant in
its own right. Discussion here provides an introduction to these specialized topics:
• Oscillator discussions focus on both linear and non-linear oscillators.
• Power circuit discussions focus on DC power.
• Communication circuit discussions focus on high-frequency operation and the frequency

translation of signals.
• Digital circuit discussions focus on the non-linear operation of digital gates and the speed
at which they operate.
e discussion of linear oscillators is based on a foundation derived from feedback am-

plifier principles. Linear oscillators are shown to be amplifiers driven into a region of oscillatory
instability characterized by the Barkhausen criterion. Colpitts, Hartley and Wein-Bridge topolo-
gies form the basis for primary oscillator discussion. Stabilization of the frequency of oscillation
through the use of a crystal is explored. Non-linear oscillators (or waveform generators) are ex-
plored through discussions of multivibrator circuits. Other non-linear circuits, such as pulse gen-
erators and Schmitt triggers, are derived from multivibrator characteristics. An introduction to
arbitrary waveform generation concludes these two chapters.
Electronic power circuitry is vital in the operation of all electrical apparatus. e focus
of discussion on power electronics presented here is directed at providing clean, reliable power to
electronic circuitry. Central to the discussion is the design, operation, and use of voltage regulators.
Another topic of particular interest to the electronics designer, transient suppression along with
overvoltage protection, is presented. e thyristor family of electronic devices is introduced.
Communication circuits typically translate baseband signals to a higher frequency range
for transmission. In order to accomplish this task and reverse it at the receiver, a variety of fun-
damental building blocks are necessary. An introduction to these building blocks is presented
here. Voltage-controlled oscillators and mixers form the primary building blocks discussed for
transmission modulators, while mixers and phase-lock loops are presented as common in receiver
demodulators. A discussion of the trade-offs between active and passive filters complements pre-
vious discussion in Chapter 9 (Book 3). Analog-to-digital conversion is introduced.
While an introduction to the basic operation of a few logic gates was presented in Chap-
ters 3 and 4 (Book 1), discussion there focused on transistor operation rather than gate operation.
xvi PREFACE
Here a closer look at bipolar and FET gate operation, including gate speed is taken. Fundamen-
tal problems encountered when transistors transition between regions of operation are analyzed.
Several design alternatives to reduce these problems are discussed. Comparisons between gate
families are made, but not emphasized. A short introduction to gallium arsenide logic is pre-
sented.

April 2016
925
CHAPTER 12
Oscillator Circuits
An electronic oscillator is a circuit that produces a periodic output without an input signal. A
harmonic (often called linear) oscillator, which is the topic of this chapter, is a subset of electronic
oscillators that produce an output signal that is approximately sinusoidal. e oscillation is based
on a resonant circuit often designed using inductors and capacitors. Crystals may be used to closely
control the oscillation frequency.
Modern applications of oscillators include audio and electronic communication systems.
ese systems often contain several oscillators including crystal-controlled reference oscillators,
voltage-controlled oscillators (VCOs), and voltage-controlled crystal oscillators. Although many
integrated circuits exist for generating periodic signals, discrete oscillator designs have significant
advantages over many integrated solutions. In many instances, integrated circuit oscillators can-
not meet the high-frequency and low noise requirements of communication systems. Discrete
oscillators are also used in high-quality audio systems which require high stability and low noise.
e basic feedback amplifier topologies, presented in previous chapters, are used to analyze
and design oscillators. ese circuits can be used to generate essentially sinusoidal waveforms
by carefully designing the amplifier to operate at the critical point where the loop gain, Af , is
1. When the loop gain is at the critical point, the circuit is oscillatory and delivers a sinusoidal
waveform without an externally applied input signal.
Harmonic oscillator designs that incorporate feedback amplifier topology with the loop
gain at the critical point are used in a variety of electronic systems. ese circuits are commonly
called linear oscillators since they generate the waveforms through resonance phenomenon: that
is, a frequency selective feedback circuit is used to amplify the frequency of interest. An alternate
approach using non-linear signal waveshaping electronic circuits is often employed in oscillator
circuit design. ese nonlinear circuits, called multivibrators, are discussed in Chapter 13.
12.1 LINEAR ANALYSIS
e basic topology of a harmonic oscillator, shown in Figure 12.1, is identical to the feedback
amplifier topology introduced in Chapter 8 (Book 2). e open-loop amplifier gain, A.s/, and
feedback return ratio, f .s/, are frequency selective. An input signal, Xi .s/, is shown in Figure 12.1
for the sake of analysis: oscillators do not require an input signal to generate a sinusoidal output
waveform. In oscillator circuits, Xo .s/ is non-zero for Xi .s/ D 0.
926 12. OSCILLATOR CIRCUITS
+
Xi (s) ∑ A(s) Xo (s)
_
f (s)
Figure 12.1: Basic topology of a harmonic oscillator with injected input signal.
e closed-loop gain of the circuit shown in Figure 12.1 is,

A .s/
Af .s/ D ; (12.1)
1 C A .s/ f .s/
where
Xo .s/
Af .s/ D :
Xi .s/
e output signal is therefore,
A .s/
Xo .s/ D Xi .s/ : (12.2)
1 C A .s/ f .s/
In electronic oscillators, the circuit is not excited by an external time varying source: that is, the
input signal Xi .j!/ D 0. erefore, for a non-zero output Xo .s/, Equation (12.2) must yield
a loop gain A.j!o /f .j!o / D 1, at the frequency of oscillation, !o . From the discussion in
Chapter 11 (Book 3), this loop gain condition causes instability resulting in amplifier oscillation.
e condition of unity loop gain with a 180ı phase shift is called the Barkhausen criterion.
In order to achieve the requisite phase shift, reactive elements must be used in the feedback loop.
Since the feedback element is reactive, the signal phase shift is invariably a function of frequency.
is implies that there is only one frequency where the Barkhausen criterion is satisfied. e
circuit oscillates at the frequency where the Barkhausen criterion is satisfied.
When the oscillator is designed for A.j!o /f .j!o / D 1, there is a chance that oscillation
will cease due to variations in the characteristics of the active elements of the amplifier caused by
slight temperature variations, power supply noise, etc., that may force jA.j!/f .j!/j < 1. If the
magnitude of the loop gain becomes smaller than unity, the oscillation will decay and then cease.
erefore, an oscillator with the loop gain, A.j!o /f .j!o / exactly equal to 1 is not realizable
in practice. If jA.j!/f .j!/j > 1, the signal that is fed back into the mixing point (the summing
node) from the feedback network will be smaller than at the input to f .s/. erefore, the output
will appear larger than that of the pervious trip around the loop. is larger voltage at the output
will then reappear as a still larger voltage on the next trip around the loop. It therefore appears that
12.1. LINEAR ANALYSIS 927
for jA.j!/f .j!/j > 1, the amplitude of the oscillation increases without limit. In fact, the output
signal amplitude is limited by the power supply rails and the onset of nonlinear operation of the
active devices of the amplifier. As the oscillations increase in amplitude, the nonlinearity of the
circuit becomes more apparent. e onset of nonlinearity limits the amplitude of the oscillation.
In practical oscillators, it is necessary to design jA.j!/f .j!/j to be slightly greater than
unity: To ensure that the magnitude of the loop gain will not fall below unity with electronic
noise or variations in transistor and circuit parameters, the loop gain, jA.j!/f .j!/j 1:05. As
stated before, the amplitude of oscillation in practical harmonic oscillators is limited by the onset
of nonlinearity. In many cases, the excursion into nonlinear regions of operation by oscillators is
small, thereby allowing linear theory to be used to design the circuits. Additionally, the reactive
feedback network is frequency selective and serves a dual purpose in feedback oscillator design.
First, it ensures that the Barkhausen criterion is satisfied and that the conditions of oscillation
are met only at the desired frequency which is significantly lower than the high cutoff frequency
of the amplifier. Second, the reactive feedback network removes the harmonics of the distorted
signal caused by the onset of nonlinearity so that a relatively pure sinusoid at the fundamental
oscillation frequency appears at both the output (sampling point) and the mixing point.
12.1.1 DESIGN OF PRACTICAL OSCILLATORS

e design of oscillators is more an art than an exact science since the steady-state operating
conditions cannot be accurately predicted by simple mathematical techniques. At the onset of
nonlinearity, the linear models used for the analysis of amplifiers are not representative of all as-
pects of circuit behavior. However, linear analysis is useful in predicting many aspects of oscillator
operation.
In oscillators, the output of the circuit must be fed back into the input with a gain slightly
greater than unity and with a phase shift of 0ı (or some multiple of 360ı ): this condition of os-
cillation only occurs at the frequency of the sinusoidal oscillation. If the phase shift through the
reactive feedback network is assumed to be independent of the amplifier operating conditions,
the steady-state frequency of oscillation will be identical to the initial oscillation frequency in the
transient state at the beginning of oscillation. For independent amplifier operation, accurate pre-
dictions of the initial oscillation frequency can be made using linear small-signal analysis. Linear
small-signal analysis yields the minimum required amplifier gain and operating frequency of an
oscillator. In most oscillator designs, the reactive network has an effect on amplifier operation.
To counteract the loading effect, the magnitude of the loop gain at the oscillation frequency is
1:3 > jA.j!/f .j!/j > 1:05 to insure generation of a sinusoid with minimum harmonic distor-
tion. Higher values of jA.j!/f .j!/j results in an oscillatory waveform with higher harmonic
content. e transient time prior to steady-state oscillation is shorter for higher loop gains at the
oscillation frequency.
Another factor that complicates oscillator design is the frequency dependence of the reac-
tive components used in the feedback network. In particular, for radio frequency (RF) applica-
tions, a capacitor larger than a few hundred picofarads tends to appear inductive above 10 MHz.
An inductor may appear capacitive at higher frequencies due to stray capacitance between the
windings of the inductor. ese so-called “parasitic” effects are difficult to model using conven-
tional circuit theory. In fact, the parasitic effects of the reactive components may cause the circuit
to oscillate at a frequency other than that predicted by small-signal analysis: that is, an oscil-
lator circuit that appears to meet required specifications may oscillate not only at the designed
frequency of oscillation, but at a lower frequency (a phenomenon called “motor-boating”) and
at one or more frequencies higher than the designed oscillating frequency. In most cases, these
effects can be mitigated by employing high quality inductors and by connecting small (100 to
300 pF) capacitors in parallel with all bypass and coupling capacitors. ese smaller capacitors
provide an effective short circuit at frequencies where the larger capacitors become inductive.
e design process of an oscillator begins with the determination of the circuit topology and
the value of its elements. e circuit element values determine the desired oscillating frequency.
However, such an analysis does not predict circuit power output, efficiency, waveform purity,
frequency stability, or temperature and power supply variation sensitivities. ese effects are most
often resolved in the design by computer simulation and hardware prototyping to adjust circuit
component values until the desired overall performance is achieved. In practice, many designers
use a few “pet” oscillator circuits that are adapted to fulfill the required performance specifications.
12.1.2 FREQUENCY STABILITY

Frequency stability is expressed in terms of the amount of frequency change with respect to a
change in a particular circuit parameter, such as the small-signal transistor current gain hfe . As-
sume that is one of these circuit parameters, so that a change in about its equilibrium point
causes a change in the loop gain of a circuit. at is,
@ .Af /
.Af / D : (12.3)
@
Stable frequency operation requires that the loop gain remain invariant. From Equation (12.1),
the condition for stable oscillator operation implies that
@ .Af /
! 0:
@
For variations in , the loop gain of an oscillator is expressed as,
Af D 1 C .Af / : (12.4)
is corresponds to a new oscillating frequency and amplitude of oscillation:
! D !o C !; (12.5a)
and
v D vo C v; (12.5b)
12.1. LINEAR ANALYSIS 929
where !o and vo are the initial equilibrium oscillating frequency and amplitude, respectively.
e difference between the new and old equilibrium points are,
@ .Af / @ .Af / @ .Af /
.Af / D C v C ! D 0: (12.6)
@ @v G!
Solving Equation (12.6) for ! ,
@ .Af / @ .Af /
C v
! D @ @v : (12.7)
@ .Af /
@!
ree methods for stabilizing oscillators, using Equation (12.7) are:
1. e numerator of Equation (12.7) is set equal to zero. at is,
@ .Af /
v D @ : (12.8)
@ .Af /
@v
Equation (12.8) states that a rate of change in the circuit parameter must be counterbal-
anced by a change in another circuit parameter.
2. e denominator of Equation (12.7) must approach infinity. In order for ! to approach
zero, @.Af /=@! must approach infinity. An alternate expression that will allow for the so-
lution to this condition is,
@ .Af / @A @f
Df CA : (12.9)
@! @! @!
To simplify the analysis, assume that A is independent of ! . en Equation (12.9) simply
becomes,
@ .Af / @f
DA : (12.10)
@! @!
Since the feedback factor f describes a reactive feedback network, it is complex. erefore,
the amplitude and phase relationship must obey the relationship,
@f
A ! 1: (12.11)
@!
@
erefore, the magnitude and phase of f are: A @jf
@!
j
! 1 and A @!f ! 1.
Assuming that A is independent of ! ,
@ .Af / @f
DA :
@! @!
Since the slope @jf j=@! is directly proportional to the quality factor .Q/ of the oscillator
circuit, the fulfillment of the requirement of Equation (12.11) requires that a high quality
factor .Q/ circuit is required for stability.
3. e open loop gain of the oscillator circuit can be used to stabilize the circuit. In this case,
A must be made very large. erefore, f must be small to meet the oscillation criterion
of Af D 1. However, the derivative of f with respect to ! must be large to fulfill the
requirement of Equation (12.11).
12.2 RC OSCILLATORS
Simple RC oscillators are commonly used in audio frequency applications that span the frequency
range from several hertz to several tens of kilohertz. e two most commonly used oscillator
circuits are the RC phase-shift and Wien-bridge oscillators.
12.2.1 PHASE-SHIFT OSCILLATOR

e phase-shift oscillator is one of the simplest oscillators to design and construct in the audio
frequency range. e oscillator exemplifies the simple principles and conditions of oscillation
discussed in Section 12.1. A simple OpAmp-based phase-shift oscillator is shown in Figure 12.2.
Rf
vo
Reactive Phase-Shift Network
+Vcc f
ii
◦• ◦• _ C C C
+
i1 R i2 R i3 R
if –Vcc
Figure 12.2: OpAmp-based phase-shift oscillator.
In this circuit, an inverting OpAmp amplifier is followed by an RC “ladder” network con-

sisting of three cascaded arrangements of a resistor R and capacitor C . e three resistors and
three capacitors in the feedback network have identical values. e output of the reactive phase-
shift ladder network is returned to the input of the inverting OpAmp amplifier. is feedback
configuration is the shunt-shunt topology. erefore, the analysis used for shunt-shunt feedback
topologies is used. e amplifier gain is,
A D RM D Rf : (12.12)
12.2. RC OSCILLATORS 931
e feedback ratio is,
if i3
f D D : (12.13)
vo vo
Using the Barkhausen criterion,

i3 Rf i3
Af D 1D Rf D : (12.14)
vo vo
If the loading of the reactive phase-shift network on the inverting amplifier can be neglected, the
output of the inverting amplifier shifts the input signal by 180ı . At a particular frequency, the
RC network shifts the phase by an additional 180ı , resulting in a total phase shift of 0ı from the
output of the OpAmp amplifier to the input. e circuit oscillates at this frequency, provided that
the amplifier gain is sufficiently large.
In order to solve for the loop gain, mesh equations for Mesh 1, Mesh 2, and Mesh 3 are
formulated:
i1
Mesh 1: vo .i1 i2 / R D 0
j!C
i2
Mesh 2: .i1 i2 / R .i2 i3 / R D 0 (12.15)
j!C
i3
Mesh 3: .i2 i3 / R C i3 R D 0:
j!C
Solve for the current i3 using Cramer’s Rule,

vo
i3 D : (12.16)
5 1 1
R 1 C 6
! 2 R2 C 2 j!RC ! R2 C 2
2
erefore, the loop gain at the frequency of oscillation is,
i3 Rf
fA D Rf D D 1: (12.17)
vo 5 1 1
R 1 C 6
! 2 R2 C 2 j!RC ! R2 C 2
2
For equality to occur, the denominator must be real and the imaginary part zero
1
6 D 0: (12.18)
! 2 R2 C 2
e frequency of oscillation is found by solving for ! ,
p 1
!RC D 6 ) !D p : (12.19)
RC 6
At that frequency of oscillation, the feedback factor f D 1=29R. For proper oscillation, the
magnitude of the loop gain must be slightly greater than unity
ˇ ˇ
ˇ 1 ˇˇ Rf
ˇ
fA D ˇ Rf >1 ) > 29: (12.20)
29R ˇ R
is condition states that an inverting amplifier must have a voltage gain. jAj > 29: the resistors,
Rf and R, are related by the required gain of the amplifier.
Example 12.1 Design of an OpAmp phase-shift oscillator

Design an OpAmp phase-shift oscillator to produce a 1 kHz ˙ 10% sinusoidal wave. Use a A741
OpAmp and power supply voltages, ˙15 V. Verify the design using SPICE.
Solution:
e circuit topology of the oscillator is identical to Figure 12.2. Resistance values in the
order of 10 k are most practical in OpAmp circuits. e components for the feedback network
can be determined using Equation (12.20):
1
! D 2 .1k/ D p :
RC 6
Since there are more standard resistor value choices available to the designer than capacitor values,
choose a reasonable and common capacitor value to initiate the design. For this design, a capacitor
value of 0.01 F is selected:
C D 0:01 F:
Using the chosen capacitor value, solve for the resistor in the RC ladder network:
1
RD 6
p D 6:497 k 6:49 k:
2 .1 k/ 0:01 10 6
e magnitude of the gain of the inverting OpAmp amplifier at midband must be greater than
29 by at least 5%. Choose a gain of 1:2.29/ D 34:8. e feedback resistor Rf of the inverting
amplifier is then:
Rf D .Avo R/ D Œ 34:8 .6:49 k/ D 225:9 k 226 k:
e complete circuit design of the phase-shift oscillator is shown below.

e output of the oscillator is as shown. Note the transient time prior to steady-state oscillation.
e transient time is approximately 35 ms. A larger loop gain will shorten the transient time but
will also increase harmonic distortion of the steady-state sinusoid.
15
10
5
Output Voltage (V)
-5
-10
-15
0 10m 20m 30m 40m 50m
In the accompanying figure, the oscillation frequency is shown to be 935 Hz which meets the
design requirement.
15
10
5
Output Voltage (V)
-5
-10
-15
46m 47m 48m 49m 50m
Time (s)
Bipolar Junction Transistor Realization of the Phase-Shift Oscillator

Discrete phase-shift oscillators can be designed using a single BJT or FET amplifier. Figure 12.3
shows a BJT-based phase-shift oscillator. e design procedure for the BJT-based phase-shift
oscillator is identical to that of the OpAmp oscillator where the frequency of oscillation is deter-
mined by the R and C values of the reactive ladder network according to Equation (12.20). One
difference lies in the value of the resistor R0 in the RC ladder network that connects the reactive
feedback network to the base of the BJT.
e value of R0 is adjusted so that,
R D R0 C .RB ==hie / ; (12.21)
where
RB D RB1 ==RB2 :
It is evident that the RC phase-shift network is not independent of the BJT amplifier.
erefore, a complete analysis of the circuit is required. Assuming operation in the midband
frequency range, the small-signal behavior of the BJT-based phase-shift oscillator in Figure 12.3
can be analyzed using the small-signal equivalent model in Figure 12.4. Assume that hoe1 is very
large and can be ignored.
+VCC
vo
RC
RB1 C C C
● Q1
R R
RB2 RE CE R'
Figure 12.3: BJT-based phase-shift oscillator.
R'
vo C C C
ib
hfeib
RB hie RC R R
Figure 12.4: Small-signal equivalent circuit of a BJT-based phase-shift oscillator.
e small-signal equivalent circuit of the BJT-based phase-shift oscillator shown in Fig-

ure 12.4 is modified in Figure 12.5 to allow calculation of the loop gain of the circuit. e equiv-
alent resistance Ri is,
Ri D RB ==hie : (12.22)
e loop gain for the circuit in Figure 12.5 is most conveniently represented in terms of
currents,
i3
Af D : (12.23)
ib
e loop gain is found by using the method of analysis shown in the phase-shift oscillator cir-
cuit. When the oscillator is designed so that RB hie (that is, Ri D RB == hie hie ), Equa-
vo
ib C C C
+
ic
i1 i2 i3 R'
hfeib
vb RB hie RC R R
Ri
–
◦•
Figure 12.5: Equivalent circuit used to calculate loop gain.
tion (12.23) yields,

hfe
A .j!/ f .j!/ D ; (12.24)
R 4 6 1 5 1
3C j j 2 2
Cj 2
RC RX RC X RC X 2 RRC X R RC X 3
where X D !1C .
e Barkhausen criterion for oscillation requires that A.j!/f .j!/ D 1†180ı D 1. erefore,
oscillation occurs when the imaginary part of the denominator in Equation (12.24) is zero,

4 6 1
0Dj C 2
RX RC X R RC X 3
(12.25)
1 4 6 1
Dj C 3 2 :
! RC RC C ! R RC C 3
Equation (12.26) simplifies to,
1 6R
D4C : (12.26)
! 2 RR C C2 RC
Solving for the oscillation frequency, ! , in Equation (12.26) results in the expression:
1
!D r : (12.27)
4RC
RC C6
R
e real part of the loop gain A.j!/f .j!/ D 1. Under this condition, the imaginary component
of the denominator of Equation (12.24) is zero. erefore, at the oscillation condition,
hfe
1D : (12.28)
R 1 1 5
3C 2
C
RC !2 RC C2 RRC C 2
e required current gain, hfe , for the fulfillment of the Barkhausen criterion is found by substi-
tuting Equation (12.26) into (12.28) and solving for hfe ,
29 RC
hfe D 23 C C4 : (12.29)
RC R
R
To find the resistor ratio RC =R for the minimum hfe required to fulfill the Barkhausen criterion,
the derivative of hfe with respect to RC =R is found and set to zero,
0 1
d hfe d B 29 RC C
0D D @23 C C4 A: (12.30)
RC RC RC R
d d
R R R
Equation (12.30) yields the resistor ratio RC =R,

r
RC 29
D D 2:7: (12.31)
R 4
erefore, to fulfill the oscillation condition, the BJT current gain must be,
29
hfe 23 C C 4 .2:7/ D 44:5: (12.32)
2:7
e result of Equation (12.32) is that the circuit meets the Barkhausen criterion and will oscillate
if hfe 44:5. Most small-signal BJTs used in oscillator design have current gains well in excess of
44.5. To insure oscillation, the loop gain is adjusted to be slightly greater than unity by adjusting
the collector resistor RC .
MOSFET Realization of the Phase-Shift Oscillator

A depletion NMOSFET-based phase-shift oscillator, shown in Figure 12.6, is simpler to analyze
than BJT-based oscillators since the gate (input) resistance is very high. erefore, the analysis
of the FET phase-shift oscillator is similar to the OpAmp oscillator.
When the FET-based phase-shift oscillator is design so that R RD ==rd , then the load-
ing of the reactive feedback network on the amplifier can be neglected. Similarly, Rg must have
much larger value than R to prevent loading of the reactive feedback network. e equation for
the loop gain is found using the methods described for the BJT-based and OpAmp-based phase-
shift oscillators. e loop gain of the NMOSFET-based phase-shift oscillator in Figure 12.6
is,
j gm .RD ==rd / ! 3 R3 C 3
A .j!/ f .j!/ D ; (12.33)
.1 6! 2 R2 C 2 / C j!RC .5 ! 2 R2 C 2 /
where gm is the mutual conductance of the FET.
+VDD
vo
RD C C C
R R R
RG
RS CS
Figure 12.6: Depletion NMOSFET-based phase-shift oscillator; bias resistor RG R.
At the oscillation condition,
1 1
!o D p ) fo D p : (12.34)
RC 6 2RC 6
Substituting Equation (12.34) into (12.33) yields the expression for the loop gain at the oscillation
frequency,
gm .RD ==rd /
A .j!/ f .j!/ D : (12.35)
29
From Equation (12.35), the gain of the FET amplifier must be gm RL D 29. is condition
implies that the magnitude of the gain of the FET amplifier must be at least 29. is conclusion
is identical to that of the OpAmp phase-shift oscillator.
12.2.2 WIEN-BRIDGE OSCILLATOR

e Wien-bridge oscillator circuit uses a balanced bridge as its reactive feedback network. e
OpAmp implementation of the Wien-bridge oscillator is shown in Figure 12.7 where the bridge
network is clearly depicted. When using an OpAmp as its gain element, the oscillator is assumed
to operate at a frequency significantly lower than the unity gain frequency of the OpAmp.
e feedback configuration of the Wien-bridge oscillator is the series-shunt topology. To simplify
the analysis of the circuit, Figures 12.8a and b are used. To find the loop gain of the oscillator
circuit, the feedback path at the output of the OpAmp is broken and an external voltage vL is
applied as shown in Figure 12.8b. Auxiliary voltages vi ; v1 , and v2 are indicated to simplify the
analysis.
+VCC
−
AV vo
+
C
–VCC
R Rf
R C RS
Figure 12.7: OpAmp Wien-bridge oscillator circuit.
Rs Rf
Rs Rf
◦•
◦• _
v1 +
+
+VCC vL
+VCC –
− _
−
vo v1 vo
AV ◦• AV
+
+ +
–VCC –VCC
Z1
C R C
R
+ Z2 ◦•
◦•
R C v2 R C +
vL –
_
(a) (b)
Figure 12.8: (a) OpAmp Wien-bridge oscillator (re-drawn); (b) Circuit used to calculate loop gain.
e open-loop gain of the OpAmp, AV (very large positive gain) and the output voltage is
vo D AV vi . e loop gain is therefore,
vo vi
Af D D AV : (12.36)
vL vL
Noting that vi D v2 v1 and A D AV , the feedback factor is,

vi v2 v1 Z2 RS
f D D D : (12.37)
vL vL Z1 C Z2 RS C Rf
erefore, the loop gain for the circuit is,

vo Z2 RS
Af D D AV
vL Z1 C Z2 RS C Rf
2 3
R
6 .1 C j!RC/ RS 7
D AV 6 7
4 R 1 RS C Rf 5
CR j (12.38)
.1 C j!RC/ !C
2 3
j!
6 RS 7
6 !o 7
D AV 6 2 7;
4 j! j! R S C Rf 5
C 1C
!o !o
1
where !o D RC .
Using the condition for oscillation, Af D 1, Equation (12.38) yields,
2 " #
! ! AV RS C Rf
0D1 Cj 3 : (12.39)
!o !o RS .1 C AV / C Rf
Equating the real and imaginary parts to zero, Equation (12.39) yields,
1
! D !o D ; (12.40)
RC
for the oscillation frequency, and
Rf 2AV C 3
D 2; (12.41)
RS AV 3
for the ratios of the gain resistors Rf and RS .

12.3. LC OSCILLATORS 941
12.3 LC OSCILLATORS
LC oscillators are commonly used in radio frequency applications that span the frequency range
from several hundred kilohertz to several hundred megahertz. e two most commonly used
oscillator circuits are the Colpitts and Hartley oscillators. ese oscillators are configured in the
general form shown in Figure 12.9. e amplifier may be an OpAmp, BJT, or FET amplifier.
e amplifier gain is Av , the input resistance to the amplifier is Ri , output resistance is Ro , and
complex impedances Z1 ; Z2 , and Z3 . e feedback topology of the circuit in Figure 12.9 is a
series-shunt feedback.
Ri
+VCC
Ro
−
AV vo
+
Z3
–VCC
Z2
Z1
Figure 12.9: General form of many oscillator circuits.
e load impedance of the circuit is,
ZL D Œ.Z1 ==Ri / C Z3 ==Z2 : (12.42)
e open loop gain is,
Av ZL
AD : (12.43)
ZL C Ro
e feedback factor is,
Z1 ==Ri
f D : (12.44)
.Z1 ==Ri / C Z3
e loop gain is found by multiplying Equations (12.43) and (12.44),
Av .Z1 ==Ri / Z2
Af D : (12.45)
Ro Œ.Z1 ==Ri / C Z2 C Z3 C Z2 Œ.Z1 ==Ri / C Z3
If the impedances are purely reactive (inductive or capacitive), then Z1 D jX1 ; Z2 D jX2 ; Z3 D
jX3 , where X D !L for inductors and X D 1=!C for capacitors, the loop gain is,
2
X1 Ri C j X1 Ri2
Av X2
Ri2 C X12
Af D : (12.46)
X1 Ri2 X12 Ri
j Ro C X2 C X3 X2 C X3
Ri2 C X12 Ri2 C X12
For the loop gain to be real with no phase shift and Ri X1 , the imaginary component of
Equation (12.46) is set equal to zero,
0 D X1 C X2 C X3 ; (12.47)
therefore,
Av X1 X2 Av X1
Af D D : (12.48)
X2 .X1 C X3 / .X1 C X3 /
From Equation (12.47), it can be seen that the circuit oscillates at a resonant frequency corre-
sponding to the series combination of X1 ; X2 , and X3 .
Equation (12.48) is simplified by using the relationship in Equation (12.47),
Av X1
Af D : (12.49)
X2
For oscillation, the loop gain, jAf j, must have a magnitude of at least unity, and X1 must have
the same sign as X2 ; that is, they must be the same type of reactance, either both capacitive or
inductive. is implies that X3 must be inductive if X1 and X2 are capacitive, or vice versa.
A Colpitts oscillator is a circuit where Z1 and Z2 are capacitors, and Z3 is an inductor. A
Hartley oscillator is a circuit where Z1 and Z2 are inductors, and Z3 is a capacitor. In the latter
case, mutual inductance between Z1 and Z2 will alter the relationships derived above.
LC oscillators are commonly used in Radio Frequency (RF) applications in the frequency
range between 100 kHz and several hundred MHz. In this range of frequencies, the simple audio
frequency small signal models of active devices (BJTs and FETs) cannot be used. High frequency
transistor models must be used in the design and analysis. LC oscillators are found extensively in
communication electronics. For example, in AM and FM receivers, station tuning is accomplished
by varying a capacitance or inductance.
12.3.1 COLPITTS OSCILLATOR

As stated above, the Colpitts oscillator is a special case of the LC oscillator described in the
previous section. A BJT-based Colpitts oscillator circuit is shown in Figure 12.10. In this circuit,
the capacitors CB and CE are very large coupling and bypass capacitors, respectively.
e small-signal ac model at the output of the BJT-based Colpitts oscillator is shown in
Figure 12.11. e equivalent device output capacitance Co is not included in the equivalent circuit
since the high frequency response of BJT amplifiers is limited by its input capacitance, Ci D
C C f1 C gm .Ri ==RC /gC . e input resistance of the BJT amplifier, Ri , is given by: Ri D
.rb C r /==RB , and the output resistance of the BJT, ro , is assumed to be very large compared to
RC and Ri .
+VCC
◦•
RC
RB1
vo L
CB ◦•
C2 C'1
RB2
RE CE
Figure 12.10: BJT-based Colpitts oscillator.
vo L
+
gmv̟ RC C2 C'1 Ci Ri v̟
–
C1
Figure 12.11: Output equivalent circuit for the Colpitts oscillator.
e Colpitts oscillator reactances are identified as:

1 1
X1 D ; X2 D and X3 D !L; (12.50)
!C1 !C2
where
C1 D C10 C Ci : (12.51)
From Equation (12.47), it can be seen that this circuit oscillates at:
1 1
X1 C X2 C X3 D 0 ) C !o L D 0:
!o C1 !o C2
Equivalently
s
C1 C C2
!o D : (12.52)
LC1 C2
e requirements for proper oscillation come from the Barkhausen criterion applied to Equa-
tion (12.49):
ˇ ˇ ˇ ˇ
ˇ X1 ˇ ˇ C2 ˇ
jAf j D ˇˇAv ˇ D ˇAv ˇ > 1: (12.53)
X2 ˇ ˇ C1 ˇ
Where Av is the midband voltage gain (obtained from Figure 12.11 with capacitors replaced by
open circuits and inductors replaced by short circuits).
vo ˇF R C
Av D D gm .RC ==Ri / gm .RC ==r / D : (12.54)
v RC C r
Substitution of Equation (12.54) into (12.53) yields the Colpitts Barkhausen criterion:
ˇF R C C1
> : (12.55)
RC C r C2
Example 12.2 BJT-based Colpitts Oscillator

Complete the design of the circuit shown for an oscillation frequency of 10.7 MHz. Assume that
the transistor parameters are:
ˇF D 200;
VA D 150 V;
rb D 30 ;
C D 3 pF;
fT D 250 MHz:
+15 V
RC
2.2 kΩ
vo L
RB1
120 kΩ ◦•
CB
68 µF
C2 C'1
0.01 µF
RB2
RE CE
120 kΩ
6.49 kΩ
68 µF
Solution:
First determine the bias condition of the oscillator.
Applying KVL to the base-emitter loop,
VCC RB2 IC ˇF C 1
0D .RB1 ==RB2 / V IC RE :
RB1 C RB2 ˇF ˇF
Substituting in the appropriate values yields the collector current,
IC D 1 mA:
Checking the collector-emitter loop results in VCE D 6:3 V.
e hybrid- parameters of interest are:
jIC j 0:001 ˇF 200
gm D D D 38:5 mS r D D D 5:2 k:
Vt 0:026 gm 0:0385
e output resistance of the BJT, ro , is significantly large enough to ignore in this design. Also,
RB r .
e capacitance C is,
gm 0:0385 12
C D C D 3 10 D 21:5 pF:
!T 2 250 106
e Miller’s equivalent input capacitance of the BJT is,
Ci D C C C .1 C gm R/ D C C C f1 C gm ŒRB1 ==RB2 ==RC == .rb C r /g

D 21:5 C 3 1 C 0:0385 120 103 ==120 103 ==2:2 103 == 30 C 5:2 103 10 12
D 199 pF:
en
C1 D C10 C Ci D 0:01 F C 199 pF D 10:2 nF:
Applying the Colpitts Barkhausen criterion using a factor of 1.25, one can determine the value
of C2
ˇF RC C1
D 1:25
.RC C r / C2
9

1:25 .RC C r / C1 1:25 Œ2200 C 5200 10:2 10
C2 D D D 214 pF:
ˇF R C 200 .2200/
Select C2 D 220 pF.

e desired frequency of oscillation is 10.7 MHz as expressed as
s
1 C1 C C2
fo D :
2 LC1 C2
Solving for L

C1 C C2 10:2 10 9 C 220 10 12
LD D 2
.2fo /2 C1 C2 2 10:7 106 10:2 10 9 220 10 12
D 1:03 H 1:0 H:
SPICE Results:
e resulting output at the collector of the BJT is shown below. Note the finite transient time to
steady-state oscillation.
1.5
1.0
Output Voltage (V)

500.0m
0.0
-500.0m
0.0 600.0n 1.2µ 1.8µ 2.4µ 3.0µ
Time (s)
e steady-state output of the oscillator is shown below. e period of oscillation is 98.3 ns which
correspond to 10.2 MHz. e oscillation frequency of the simulated circuit is within 5% of the
desired oscillating frequency of 10.7 MHz.
1.5
1.0
Output Voltage (V)
500.0m
0.0
-500.0m
2.00µ 2.08µ 2.16µ 2.24µ 2.32µ 2.40µ
Time (s)
A FET-based Colpitts oscillator, shown in Figure 12.12, is somewhat simpler to design and
analyze since the input (gate) resistance is very large. e capacitors CG and CS are very large
coupling and bypass capacitors, respectively.
If the circuit is designed with a large value of RG , the small-signal model at the output of
the FET-based Colpitts oscillator is shown in Figure 12.11.
e equivalent device output capacitance Co is not included in Figure 12.13 since the high
frequency response of FET amplifiers is limited by Ci D Cgs C Œ1 C gm .RD ==rd / Cgd . Once
again C1 D C10 C Ci .
VDD
RD
vo L
CG ◦•
C2 C'1
RG
RS CS
Figure 12.12: JFET-based Colpitts oscillator.
vo L
+
gmvgs rd RD C2 C'1 Ci vgs
–
R C1
Figure 12.13: Output equivalent circuit for the Colpitts oscillator in Figure 12.12.
As was the case for the BJT Colpitts oscillator, the circuit will oscillate at
s
C1 C C2
!o D ; (12.56)
LC1 C2
and the requirements for proper oscillation come from the Barkhausen criterion applied to Equa-
tion (12.49): ˇ ˇ ˇ ˇ
ˇ X1 ˇ ˇ C2 ˇ
ˇ
jAf j D ˇAv ˇ D Av ˇ > 1:
ˇ (12.57)
X2 ˇ ˇ C1 ˇ
Where Av is the midband voltage gain (obtained from Figure 12.11 with capacitors replaced by
open circuits and inductors replaced by short circuits).
vo
Av D D gm .RD ==rd / : (12.58)
v
Substitution of Equation (12.54) into (12.53) yields the Colpitts Barkhausen criterion:
C1
gm .RD ==rd / > : (12.59)
C2
An OpAmp-based Colpitts oscillator is shown in Figure 12.14. e small output resistance

of the OpAmp is included in the analysis.
Rf
◦• vo
RS
− L
+ C C
Ro
Figure 12.14: OpAmp-based Colpitts oscillator.
e oscillation condition occurs at

r
2
!o D : (12.60)
LC
e oscillator circuit should be designed so that,
Rf
> 1: (12.61)
RS
e advantage of using Colpitts oscillators comes from the fact that tuning a single inductor
allows for variation in the oscillation frequency. is is especially advantageous since inductors
can easily be tuned by introducing ferrite material in through the cross-section of the inductor
coil.
12.3.2 HARTLEY OSCILLATOR

e Hartley oscillator circuit is similar to the Colpitts oscillator with one major difference: the
capacitors and inductors have been “swapped.” A Colpitts oscillator can be mapped into a Hartley
oscillator by exchanging jXL and jXC . A FET-based Hartley oscillator circuit is shown in
Figure 12.15, where CD is a large coupling capacitor required to isolate the DC and AC models.
e inductors in the circuit are identical and, for simplicity, there it is assumed that there is no
mutual inductance coupling between the inductors.
+VDD
RD
CD vo C
L2 L1
•
•
RG RS CS
Figure 12.15: FET-based Hartley oscillator.
e Harley oscillator reactances are identified as:
1
X1 D !L1 ; X2 D !L2 and X3 D : (12.62)
!C
e midband voltage gain is given by:
vo
Av D D gm .RD ==rd / : (12.63)
v
Oscillation occurs at
1
X1 C X2 C X3 D 0 ) !o L1 C !o L2 D 0: (12.64)
!o C
Equivalently
1
!o D p : (12.65)
.L1 C L2 / C
e condition for oscillation indicates that the circuit will oscillate if
ˇ ˇ
ˇ ˇ
ˇgm .RD ==rd / !o L1 ˇ ) jgm .RD ==rd /j > L2 : (12.66)
ˇ !o L2 ˇ L1
e advantage of using Hartley oscillators comes from the fact that tuning a single capacitor
allows for variation in the oscillation frequency. is is especially advantageous since a single
voltage variable capacitor called a varactor diode can be used to easily tune the circuit.
12.4. CRYSTAL OSCILLATORS 951
12.4 CRYSTAL OSCILLATORS
Crystals are three-dimensional, mechanical oscillating components that oscillate in many differ-
ent modes. e crystal oscillations are governed by the crystal piezoelectric properties, and the
arrangement and shape of the electrodes attached to the crystal. Crystals are fabricated so that
several oscillating and harmonic modes can be used in the design of a circuit. Crystals are available
in a wide range of discrete frequencies.
For stable frequency operation, the oscillator should be designed so that a crystal is the
controlling element for the oscillation. e crystal oscillator is often a critical component in
communications systems and in digital signal processing applications. e circuit symbol for the
piezoelectric crystal is shown in Figure 12.16a. e electrical equivalent circuit representing the
resonant nature of the piezoelectric crystal is shown in Figure 12.16b. e equivalent circuit is
similar to the familiar RLC passive resonant circuit.
◦•
RS
L Co
XTAL
C1
◦•
(a) (b)
Figure 12.16: (a) Circuit symbol for a crystal; (b) Equivalent circuit for a crystal.
e capacitance Cp is in the order of 10 pF and includes the capacitance associated with the
mechanical package and Cs is in the order of 0.05 pF. e crystal equivalent inductance, L, is very
large for quartz crystals, on the order of several tens of Henrys. e internal losses of the crystal
are represented by Rs which is typically small. e resistive loss, Rs , is related to the quality factor
Q of the crystal, since the energy lost during any periodic signal is associated with the dissipative
resistance. Q is defined as the ratio of maximum energy stored to the amount lost per periodic
cycle. It also determines the bandwidth of resonant circuits. e bandwidth is calculated from Q
and the resonant frequency by,
fo
BW D : (12.67)
Q
e quality factor is related to the dissipative resistance and inductance through the relationship,
!o L
QD : (12.68)
Rs
Crystals are inherently high Q devices. When used in oscillator circuits, a crystal increases the
oscillation stability. is was shown in Section 12.1 where,
@ .Af / @f
DA :
@! @!
Since the slope @jf j=@! is directly proportional to the quality factor .Q/ of the oscillator circuit,
the high Q characteristic of crystals allows the fulfillment of the requirement of Equation (12.10)
that A.@jf j=@!/ ! 1. erefore, crystal oscillators are inherently very stable.
Figure 12.16b provides a simplified equivalent circuit of a crystal at one oscillating fre-
quency. In reality, the crystal has many oscillatory modes (and frequencies). erefore, a more
accurate model of a crystal depicting its many oscillatory frequencies and harmonics is shown in
Figure 12.17.
RS1 RS2 RS3 RSn
Co L1 L2 L3 ••• Ln
C11 C12 C13 C1n
Figure 12.17: Electric circuit equivalent of a crystal showing many oscillatory states.
e circuit in Figure 12.17 contains several series resonant circuits whose frequencies are nearly
the odd harmonics of the fundamental oscillatory frequency. e higher resonant frequencies are
called overtones of the fundamental. Typical circuit parameters for fundamental, third, and fifth
overtone crystals are given in Table 12.1.
If Rs D 0, crystal input impedance in a narrow frequency range around fo is,
h i
.j!Co / 1 j!L C .j!C1 / 1
Z .j!/ D : (12.69)
j!L C .j!C1 / 1 C .j!Co / 1
12.4. CRYSTAL OSCILLATORS 953
Table 12.1: Typical crystal data
f, MHz Oscillation Mode Rs, Ω Co, pF C1, fF Q

1.0 Fundamental 250 4.0 9.0 65,000
2.0 Fundamental 70 3.5 10.0 110,000
5.0 Fundamental 15 6.0 24.0 86,000
10.0 Fundamental 12 6.0 24.0 50,000
20.0 Fundamental 12 6.0 24.0 25,000
45.0 3rd Overtone 25 5.0 1.5 90,000
100.0 5th Overtone 40 5.0 0.3 130,000
e impedance Z.j!/ will be zero when L and C1 are in resonance: that is,
1
fs D p : (12.70)
2 LC1
where fs is the series resonant frequency of the crystal. Conversely, the crystal will have infinite
input impedance at the frequency,
1
fa D s ; (12.71)
Co C1
2 L
Co C C1
where fa is the antiresonant frequency of the crystal. An ideal crystal (one with Rs D 0) behaves
as both a series resonant and a parallel resonant circuit with infinite Q. Realistically, all crystals
have some series resistance, Rs . For non-zero Rs , the input impedance of a crystal is,
h i
.j!Co / 1 j!L C Rs C .j!C1 / 1
Z .j!/ D : (12.72)
j!L C Rs C .j!C1 / 1 C .j!Co / 1
In practice, the input impedance of a crystal at resonance with non-zero Rs is the same as one
with Rs D 0. e effect of Rs is primarily in the reduction of Q.
Crystal oscillators can be implemented in a variety of topologies. For example, a Pierce
oscillator, shown in Figure 12.18, is a simply a Colpitts oscillator where the crystal has replaced
the inductor in the feedback path. e Pierce oscillator depends on the inductive component of
the crystal to provide a feedback of the proper phase. e crystal will oscillate at a frequency
between fa and fS .
e circuit in Figure 12.18 is designed and analyzed in the same manner as the LC Colpitts
oscillator. Feedback is provided through the crystal which is operating near the series-resonant
+VDD
RD
LN
CG vo
•
C2 C'1
RG
RS CS
Figure 12.18: Pierce crystal oscillator.
mode frequency. For oscillators operating above 20 MHz, an inductor, LN , is placed in parallel
with the crystal. e purpose of LN is to neutralize the package capacitance, Co , where:
1
LN : (12.73)
.2 fo /2 Co
e Pierce oscillator is most commonly used with fundamental mode crystals.

A Pierce oscillator can be designed from CMOS inverter used as an amplifier is shown in
Figure 12.19. e reactive components of the feedback network consist of C1 ; C2 , and XTAL (the
crystal).
e CMOS amplifier has high-gain inverting amplifier. e reactive feedback network
reverses the phase again so that there is positive feedback. is CMOS oscillator is often used as
a simple timing circuit.
e effect of adding series or parallel elements to the crystal is quite complex. e resonant
frequency is altered, and the dissipative resistance is scaled. Losses due to the added components
will also alter the composite Q of the oscillator. To complicate things further, all of the effects
mentioned vary as the circuit is tuned or adjusted.
Figure 12.20 shows an improved crystal Colpitts oscillator circuit. e schematic shows a
series crystal in the feedback path of the oscillator.
Here the crystal appears as a series resistance Rs (crystal resistance) at the series resonant fre-
quency. Since Rs is small, it can usually be ignored in designing the circuit. e design procedure
is identical to an LC Colpitts oscillator with an addition of a crystal in the feedback path.
12.5. CONCLUDING REMARKS 955
◦ +VDD
RG
• vo
R1
C2 XTAL C1
Figure 12.19: CMOS Pierce oscillator.
+VCC
RC
RB1
vo L
XTAL C2 C'1
RB2
RE CE
Figure 12.20: Improved crystal Colpitts oscillator.
12.5 CONCLUDING REMARKS

Electronic harmonic oscillator circuits were discussed in this chapter. Although several different
configurations were presented, all of the harmonic oscillators shared the Barkhausen criterion for
oscillation which simply states that the loop gain of the circuit has unity magnitude gain and a
phase of 180ı .
Oscillators were designed from BJTs, FETs, and OpAmps. e advantage of using FETs
and OpAmps lies in the large input resistance of the devices. Because of their large input resis-
tances, the device does not affect the impedance of the reactive feedback network. However, at
higher frequencies, OpAmps cannot be used since the high-frequency response is limited by the
relatively low gain-bandwidth product. erefore, for high frequency RF applications, BJT and
FET oscillators are used.
At high frequencies, LC reactive networks are commonly used. is is due to the inductive
nature of resistors at high frequencies, which prohibits the use of RC phase-shift oscillators at
these frequencies.
For good frequency stability, crystals are used in the oscillator circuit. Because crystals are
inherently reactive, they can be used in place of inductors in oscillator circuits. At higher fre-
quencies, however, a small inductor should be place in parallel with the crystal to counteract the
package capacitance.
Summary Design Example: Color Reference Oscillator for Color Television

e color seen on a typical television is emitted from special phosphors. e color cathode ray
tube (CRT) has three separate phosphors placed on the screen. When struck by electrons one
phosphor emits red, on green, and one blue. e three phosphors are arranged very close to each
other in alternating vertical stripes or as tiny points in a matrix pattern. e color that is projected
to the user is a combination of the three phosphor emissions.
e electronic signal required to produce color on an otherwise black and white picture
signal is called chrominance or chroma. e frequency of the chroma signal is 3.5795 MHz. e
chroma signal is a vector with the phase angle indicating the hue (tint, or type of color) and
magnitude indicating the saturation level or color intensity. A red fire engine is a saturated red
object.
ere are several oscillator designs that can be considered for the 3.5795 MHz oscillator.
ey are:
• Phase-shift oscillator
• Wien-bridge oscillator
• Colpitts oscillator
• Hartley oscillator
• Pierce oscillator
Each of the oscillator configurations listed can be design with OpAmps, BJTs, and FETs. OpAmp
implementations are not practical in this case since the frequency is higher than most low cost
OpAmp gain-bandwidth products. For low cost, it is also common to use inexpensive BJTs for
discrete electronic circuits. A common device is the 2N3904 npn BJT. e BJT specifications are:
ˇF D 200, Cibo D 8 pF at VEB D 0:5 V VA D 150 V,
rb D 30 , Cobo D 4 pF at VCB D 5 V, fT D 300 MHz at ICT D 10 mA.
e oscillator chosen is the BJT Colpitts oscillator. e transistor is to be biased at a modest
collector current. Choose IC D 1 mA with a large évenin base resistance to simplify analysis.
e circuit configuration chosen is shown below.
+15 V
RC
1 kΩ
vo L
CB RB1
68 µF 120 kΩ C2 C'1
RB2
120 kΩ RE
CE
6.49 kΩ
68 µF
In order to solve for the reactive feedback elements, the effective input and output capacitance of
the BJT must be found. e parameters of interest are C and C for analytical design.
e hybrid- parameters of interest are:
jIC j 0:001 ˇF 200

gm D D D 38:5 mS r D D D 5:2 k:
Vt 0:026 gm 0:0385
e output resistance of the BJT, ro , is significantly high enough to ignore in the design.
Also, RB r 1=1000.
e capacitance, C D Cobo D 4 pF and the capacitance C is,
gm 0:0385 12
C D C D 4 10 D 16:4 pF:
!T 2 300 106
e Miller’s equivalent input capacitance of the BJT is,
Ci D C C C .1 C gm R/ D C C C f 1 C gm ŒRB1 ==RB2 ==RC == .rb C r /g

D 16:4 C 4 1 C 0:0385 120 103 ==120 103 ==103 == 30 C 5:2 103 10 12
D 147:8 pF:
ere is considerable freedom in the choice of component values Let C10 D 0:051 F. en,
C1 D C10 C Ci D 0:051 F C 147:8 pF D 51:15 nF:

If the magnitude of the closed loop gain is designed for 1.25, then
ˇF RC C1
D
1:25.RC C r / C2
9

1:25 .RC C r / 1:25 Œ 1000 C 5200 51:15 10
C2 D D D 1:982 nF:
ˇF RC 200 .1000/
Select C2 D 2000 pF. e frequency of oscillation is 3.5795 MHz as expressed as,
s
1 C1 C C2
fo D :
2 LC1 C2
Solving for L,
C1 C C2 .51:15 10 9 C 200 10 9 /
LD D
.2fo /2 C1 C2 Œ2.3:5795 106 /2 .51:15 10 9 /.200 10 9/
D 1:027 H 1 H:
Simulation using these values results in an oscillation frequency, fo D 3:52 MHz. A simple
method for insuring stable and accurate oscillation frequency is to use a 3.5795 MHz crystal. A
crystal Colpitts oscillator can be designed by simply replacing the inductor in the reactive feedback
network using the calculated capacitor values.
12.6 PROBLEMS
12.1. For the network shown, show that:
(a) When used with an OpAmp to form an oscillator, the resonant frequency is
f D 2RC and that the gain must exceed 3.
(b) Use SPICE to verify the result of a).
R C
+ +
Vo C R Vi
– –
12.2. Design an OpAmp-based phase shift oscillator circuit at 8 kHz. Assume an ideal
OpAmp. Simulate your design to verify proper operation.
12.3. Show that a four section RC network reduces the required network voltage gain for a
phase-shift oscillator.
12.6. PROBLEMS 959
(a) Determine the minimum required voltage gain of the amplifier.
(b) Determine the resonant frequency of a four section RC phase-shift oscillator.
12.4. Determine the resonant frequency of a phase-shift oscillator with a three RC sections
with capacitors to ground as shown.
Rf
vo
+VCC
− R R R
+ C C
C
–VCC
12.5. For a four section RC phase-shift network, similar to Problem 12.4 with capacitors to
ground, for a phase-shift oscillator:
(a) Determine the minimum required voltage gain of the amplifier.
(b) Determine the resonant frequency of the phase-shift oscillator.
12.6. Given FET parameters:
VPO D 1:5 V; IDSS D 12 mA;
VA D 200 V:
(a) Complete and modify the design shown for an oscillation frequency of 5 kHz. Make
any necessary assumptions.
(b) Simulate the circuit using SPICE and confirm the oscillation frequency.
+24 V
vo
RD C C C
0.012 µF 0.012 µF 0.012 µF
RG ◦•
510 kΩ R R R
RS CS
1 kΩ 1 kΩ 1 kΩ
12.7. Given the following BJT parameters of interest: ˇF D 200, and VA D 200 V:
(a) Complete the design of the BJT-based phase-shift oscillator shown. What is the
frequency of oscillation? Make any necessary assumptions.
(b) Simulate the circuit using SPICE and confirm the oscillation frequency.
+24 V
vo
RB1 RC
C C C
22 kΩ ◦•
0.01 µF 0.01 µF 0.01 µF
•
RB2 R R
12 kΩ RE 3.9 kΩ 3.9 kΩ
4.53 kΩ CE R'
12.8. Complete the design an OpAmp-based Wien-bridge oscillator for 19.2 kHz. Use C D
1 F and Rf D 5:1 k.
Simulate the circuit using SPICE and confirm the oscillation frequency.
+12 V
−
AV vo
+ C
1 µF
–12 V
R Rf
5.1 kΩ
R C RS
1 µF
12.9. Using an ideal OpAmp, design a Colpitts oscillator at 1 kHz using an inductor value of
L D 10 H. Simulate the completed design and verify the oscillation frequency.
12.6. PROBLEMS 961
12.10. Design a BJT-based common-emitter configured Colpitts oscillator at 1 MHz. A C15 V
power supply is available. e BJT parameters of interest are:
ˇF D 200; VA D 150 V; rb D 30 ; Cibo D 8 pF at VEB D 0:5 V;
Cobo D 4 pF at VCB D 5 V; and fT D 300 MHz at IC D 10 mA:
12.11. Given the following BJT parameters:
(a) Design a BJT-based common-emitter configured Colpitts oscillator at 10 MHz.
Bias the transistor at IC D 1 mA and VCE D 8 V. A power supply voltage of C24 V
is available.
(b) Re-design the oscillator using the parameters found in Table 12.1 for a 10 MHz
fundamental crystal.
(c) Simulate both circuits with SPICE and comment on the results.
12.12. Design an NJFET-based common-source configured Colpitts oscillator at 2 MHz. e
FET parameters of interest are:
IDSS D 6 mA; VPO D 4:7 V; VA D 100 V;
Ciss D 4:5 pF at VGS D 0 V; and Crss D 1:5 pF at VGS D 0 V:
Assume a C15 V power supply. Bias the transistor at ID D 1 mAI VDS D 5 V.
12.13. Determine the relationship for the frequency of oscillation for the common-base config-
ured Colpitts oscillator in terms of C1 ; C2 , and L using small-signal hybrid- analysis
and appropriate assumptions. Assume that ro 1 C1 C20 .rb C r /, and CC and CB are
large-valued capacitors.
L
vo
C1 C2
CC
RC
+VCC
RB1
RE
CB
RB2
12.14. Determine the relationship for the frequency of oscillation for the common-gate con-
figured Colpitts oscillator in terms of C1 ; L using small-signal analysis and appropriate
assumptions. CD and CG are large-valued capacitors.
L
vo
C1 C2
CD
RD
+VCC
RS
CG
RG
12.15. Design a BJT-based common-base configured Colpitts oscillator at 1 MHz. e BJT

parameters of interest are:

Assume a C15 V power supply. Bias the transistor at IC D 1 mAI VCE D 5 V.

12.16. Design an NMOSFET-based common-gate configured Colpitts oscillator at 2 MHz.
e FET parameters of interest are:


12.17. Design an NJFET-based common-source configured Hartley oscillator at 1 MHz. e
FET parameters of interest are:

Ciss D 6 pF at VGS D 0 V; and Crss D 2 pF at VGS D 0 V:

12.6. PROBLEMS 963
12.18. Determine the relationship for the frequency of oscillation for the transformer coupled
common-base configured Hartley oscillator shown in terms of C; L, and the transformer
turns ratio using small-signal hybrid- analysis and appropriate assumptions. Assume
that CC and CB are large-valued capacitors.
n1 : n2 vo
● ●
C
L CC
RC
+VCC
RB1
RE
CB
RB2
12.19. In many instances it is preferable to use auto-transformers, which are easily fabricated,
instead of regular transformers for coupling signals in feedback configurations. e auto-
transformer and its equivalent circuit are shown in the figure:
IDEAL
n2 : n1
L
n2 L
}n1
vo
L
C
n1{ n2 CC
RC
+VCC
RB1
RE
CB
RB2
Determine the relationship for the frequency of oscillation for the auto-transformer cou-
pled common-base configured Hartley oscillator shown in terms of C; L, and the auto-
transformer turns ratio using small-signal hybrid- analysis and appropriate assump-
tions. Assume that CC and CB are large-valued capacitors.
12.20. What is the relationship for the frequency of oscillation for the auto-transformer cou-
pled common-base configured Hartley oscillator shown in Problem 12.16 when RE is
eliminated .RE ! 1/?
12.21. Design a BJT-based auto-transformer coupled common-base configured Hartley oscil-

lator at 1 MHz. e BJT parameters of interest are:

Assume a C15 V power supply. Bias the transistor at IC D 1 mAI VCE D 5 V. Simulate
the circuit using SPICE and confirm the oscillation frequency.
12.22. Determine the relationship for the frequency of oscillation for the transformer coupled
common-source configured Hartley oscillator shown in terms of C; L, and the auto-
transformer turns ratio using small-signal analysis and appropriate assumptions. Assume
that CC and CG are large-valued capacitors.
n1 : n2
● ●
vo
C
L CC
RC
+VCC
RS
CG
RG
12.23. Determine the relationship for the frequency of oscillation for the auto-transformer cou-
pled common-source configured Hartley oscillator shown in terms of C; L, and the auto-
transformer turns ratio using small-signal analysis and appropriate assumptions. Assume
that CC and CG are large-valued capacitors.
12.6. PROBLEMS 965
vo
L
C
n1{ n2
CC
RD
+VDD
RS
CG
RG
12.24. What is the relationship for the frequency of oscillation for the auto-transformer cou-
pled common-gate configured Hartley oscillator shown in Problem 12.19 when RS is
eliminated .RS ! 1/?
12.25. Determine the relationship for the frequency of oscillation for the auto-transformer cou-
pled common-collector configured Hartley oscillator shown in terms of C; L, and the
auto-transformer turns ratio using small-signal hybrid- analysis and appropriate as-
sumptions.
Assume that CC and CB are large-valued capacitors.
+VCC
RB1 RC
CC
L
C
n1{ n2
RB2
12.26. Design an NMOSFET-based auto-transformer coupled common-gate configured Hart-

ley oscillator at 2 MHz. e FET parameters of interest are:
IDSS D 6 mA; VT D 2:0 V; VA D 150 V;

12.27. If the temperature stability of the crystal is 5.0 ppm/ı C, determine the percent change
in oscillator frequency after a rise in temperature of 50ı C for a Pierce oscillator. Assume
that the temperature variation only affect the series equivalent capacitance of the crystal.
12.28. A small inductance is added in parallel with a crystal operating in the series mode in a
crystal oscillator. Will the frequency of the oscillation increase or decrease? Explain. Use
simulations where appropriate.
12.29. A small “trimmer” capacitance is added in parallel with a crystal operating in the an-
tiresonant mode in a crystal oscillator. Will the frequency of the oscillation increase or
decrease? Explain. Use simulations where appropriate.
12.30. Design a test circuit to confirm the resonance frequency of a 2 MHz crystal with the
parameters given in Table 12.1. Confirm its operation by simulating the circuit using
SPICE.
12.31. Design a 1 MHz CMOS Pierce oscillator using the crystal data in Table 12.1. e MOS
parameters are:
Kn D 100 A=V2 ; Kn D 100 A=V2 ;

VTn D jVTn j D 1 V; Ciss D 50 pF at VGS D 0 V; and Crss D 5 pF at VGS D 0 V:
12.32. Find the condition under which the circuit shown will oscillate.
Assume VA D 180 V.
12.6. REFERENCES 967
+VDD
RB RC
470 kΩ 2.2 kΩ
Crystal
(resonance at
vo 100 kHz)
◦• • •
C1 C2’
•
500 pF 0.022 µF
•
RE CE
1 kΩ 47 µF
•
REFERENCES
[1] Ghausi, M. S., Electronic Devices and Circuits: Discrete and Integrated, Holt, Rinehart and
Winston, New York, 1985.
[2] Millman, J. and Halkias, C. C., Integrated Electronics: Analog and Digital Circuits and Sys-
tems, McGraw-Hill Book Company, New York, 1972.
[3] Sedra, A. S. and Smith, K. C., Microelectronic Circuits, 3rd ed., Holt, Rinehart, and Win-
ston, Philadelphia, 1991.
[4] Schilling, D. L. and Belove, C., Electronic Circuits, 3rd ed., McGraw-Hill Book Company,
New York, 1989.
[5] Young, P. H., Electronic Communication Techniques, 3rd ed., Merrill Publishing Company,
New York, 1994.
969
CHAPTER 13
Waveform Generation and

Waveshaping
In addition to sinusoidal waveforms, electronic systems often have need for signals with other
wave shapes. Common waveforms include single pulses of fixed duration as well as periodic square
waves and triangular waves. Fixed-duration pulses are used primarily for timing of events in com-
munication and control systems. Periodic square waves are formed by a regular series of pulses:
one typical use is as a clock for digital systems. If pulse timing, duration, or amplitude can be
externally controlled, these altered square waves become the foundation of many digital com-
munication systems. Triangular waves are particularly significant in scanning an electron beam
across a cathode-ray tube screen (as in television or oscilloscope applications), in precise time
measurements, and in time modulation.
Electronic circuits that generate non-sinusoidal waveforms, such as pulse, square, and tri-
angular waveforms, are typically based upon electronic multivibrators. ese multivibrators are
characterized by a very rapid transition between two distinct output states and can be grouped
into three basic categories based on the time stability of these output states. A bistable multivi-
brator will rest indefinitely in either output state until triggered to change state. A monostable
multivibrator has one stable state: the other state is of fixed, finite duration (a quasi-stable state)
that can only be activated with a triggering signal. A constant, periodic switching between quasi-
stable states characterizes an astable multivibrator. Astable, periodic switching is also known as
non-linear oscillation.
In this chapter, multivibrator circuits intended for precision analog applications are pre-
sented. ese circuit designs are based on a slight variation of the operational amplifier, typically
known as the comparator. Circuits that generate single pulses of varying time duration or square
and triangular waveforms of variable time symmetry using multivibrators are described. Similar
circuits utilizing an integrated-circuit multivibrator, in the form of an IC timer, are also described.
A voltage-controlled square-wave oscillator (VCO) is presented as a special case of non-linear os-
cillation.
Arbitrary, periodic waveforms are often derived from triangular waveforms. Two techniques
to generate sinusoids from triangular waveforms are described as examples of waveform alteration.
e primary technique is based on piece-wise linear amplification using the forms of the basic
diode clipping circuits described in Chapter 2 (Book 1).
970 13. WAVEFORM GENERATION AND WAVESHAPING
Multivibrator applications based on OpAmps and comparators are best suited for elec-
tronic applications from a fraction of a Hertz up to a few Megahertz. High-frequency, analog
multivibrator applications are beyond the scope of this discussion. High-frequency multivibrators
intended for, digital applications are presented in Chapter 16.
13.1 MULTIVIBRATORS
Multivibrator circuits are fundamental to many waveshaping and wave generation circuits. In the
most common form they have two output states, each of which may be either stable or quasi-
stable. As such, multivibrator circuits can be grouped into three classifications based on the sta-
bility of the output states:
• Bistable Multivibrator —two stable output states. Bistable circuits require a triggering signal
to transition between output states. Once in a particular output state, the circuit remains in
that stable state indefinitely until triggered for a transition to the other stable output state.
• Astable Multivibrator —two quasi-stable output states. Without any external triggering, the
astable multivibrator transitions periodically between two quasi-stable output states.
• Monostable Multivibrator —one stable and one quasi-stable output state. In monostable cir-
cuits, a triggering signal is required to induce an output transition from the stable state to
the quasi-stable state. After the circuit remains in the quasi-stable state for a fixed time,
typically long in comparison with the time of transition between states, it returns to the
stable state without external triggering.
13.1.1 BISTABLE MULTIVIBRATORS

One of the most simple forms of a bistable circuit is the comparator. A comparator shares many
characteristics with a high voltage gain OpAmp: it has two inputs and a single output determined
by the difference of two input signals. As seen in Figure 13.1, the circuit symbol for a comparator
is identical with that of an OpAmp and the terminals are identified in the same manner. If the
non-inverting input is at a higher potential than the inverting input, the output of the comparator
is the HIGH voltage output state: reversing the sense of the inputs yields the LOW voltage output
state. e HIGH and LOW output voltage states are often determined by the power supply rails,
but may be internally controlled to be other voltage levels (5 V and 0 V are a common pair when
interfacing to digital circuitry). While OpAmps can be used as comparators, a comparator is not
typically used with a wide range of negative feedback. erefore, the comparator can be optimized
for rapid transition between states at the expense of linearity and feedback stability. As such, a
comparator will typically transition between states much more quickly than an OpAmp of similar
design. Comparators suffer from the same non-ideal characteristics as OpAmps. Slew rate and
frequency response are, arguably, the most problematic of these non-ideal properties.¹
¹Non-ideal characteristics of OpAmps are discussed in Section 1.5 (Book 1). e discussion is also valid for comparators.
13.1. MULTIVIBRATORS 971
non-inverting input ◦ +
output
inverting input ◦ −
Figure 13.1: Comparator circuit symbol.
While comparators perform well in a noiseless environment, the noise content of a typical
signal can create false triggering or multiple triggering of the output of a comparator. In a typical
application, a comparator is used to determine when the non-inverting input voltage exceeds
the voltage level at the inverting input. As shown in Figure 13.2, the addition of noise to an
increasing input signal at the non-inverting input can cause several transitions of the comparator
output when the input voltage nears the voltage reference level present at the inverting input.
Usually a single transition of the output is desired in such a comparison.
reference level
noisy input
signal
comparator output
Figure 13.2: e output of a comparator due to a noisy input.
Multiple triggering of the output of a comparator can be eliminated with the application of
positive feedback. Positive feedback retains the rapid output transition of comparator, but alters
the trigger level so that two separate trigger levels exist: one for positive slope signals and an-
other for negative slope signals. e resultant transfer relationship exhibits hysteresis as shown in
Figure 13.3. Any input signal below the negative slope transition voltage, VT , results in a LOW
output, VL . If the output state is LOW, it will not transition to the HIGH state unless the input
is greater than the positive slope transition voltage, VTC . Similarly, any input above VTC results
in a HIGH output, VH , that will not transition to the LOW state unless the input falls below
VT . us, signals, after crossing a threshold, do not respond to input signal changes unless the
variation is large enough to cross the deadband.
VH
deadband
Output
VL
– + Input
VT VT
Figure 13.3: Schmitt trigger transfer characteristic hysteresis.
An example of a comparator with positive feedback is shown in Figure 13.4. is form of
circuit is called a Schmitt trigger. Aside from being especially useful in converting slowly varying
or a noisy signal into a clean, pulsed form with sharp transitions, the Schmitt trigger is particularly
useful in converting sine-wave input into a pulse-train output. Variation of the pulse-train duty
cycle in this application is accomplished by varying the triggering voltage levels, VTC and VT .
Rf
Rin
vin
+
vo
vr ◦ −
Figure 13.4: A simple Schmitt trigger circuit.
e Schmitt trigger can be realized in many configurations. When comparators are used
as the basic active element,² inverting and non-inverting forms are typically realized as is shown
in Figure 13.5. e additional resistors shown provide stable reference voltage, vr . If a more
precise reference voltage is necessary, precision voltage reference circuitry may be utilized instead
of simple resistor networks.³
²Bipolar and CMOS realizations of Schmitt trigger circuits for digital applications are presented in Section 16.5.
³Precision voltage references are discussed in Section 14.2.1.
±VCC
vin − vin
+
vo vo
• + −
±VCC
(a) (b)
Figure 13.5: Typical Schmitt trigger circuits. (a) Inverting Schmitt trigger; (b) Non-inverting Schmitt
trigger.
Example 13.1 Design Example

e simple Schmitt trigger circuit of Figure 13.4 is configured so that the two stable output
voltages are ˙10 V. e reference voltage, vr , is a ground potential. Complete the design by
choosing Rin and Rf so that the output transition to C10 V occurs at the threshold voltage,
vin D VTC D 0:5 V. At what input voltage level does the transition to 10 V (that is, VT ) occur?
Solution:
e output will transition to C10 V when the non-inverting input reaches the reference
voltage, vr D 0 V. e non-inverting input voltage can be obtained from the input voltage, vin D
0:5 V and the LOW output voltage, vo D 10 V, using the voltage division technique:
Rf
vr D 10 C Œ0:5 . 10/ D 0:0;
Rf C Rin
or
Rf 10
D ) Rf D 20 Rin :
Rf C Rin 10:5
Many resistor pairs will fulfill this simple requirement. As with OpAmps, it is important to choose
resistors that are small compared to the input resistance of the comparator and large compared to
the output resistance. e following choice is one pair of values that will meet the design goals
using standard resistance values:
Rf D 20 k and Rin D 1 k:
e transition to 10 V is an exact mirror image of the transition to C10 V : it occurs at
vin D 0:5 V:
us, the HIGH output state .C10 V/ is triggered when the input exceeds 0.5 V and remains
until the input falls below 0.5 V.
13.1.2 ASTABLE MULTIVIBRATORS

Astable multivibrators continuously transition between quasi-stable output states without the aid
of an external triggering input. e output of an astable therefore becomes a square wave with the
waveform duty cycle as a possible variable. One such astable circuit is shown in Figure 13.6. Here
the two inputs to a comparator are coupled to the comparator output through two different type
networks. e non-inverting input is connected through a resistive voltage divider: as the output
toggles between quasi-static states, this input similarly toggles between states. e inverting input
is connected to the comparator output by an RC charging network: this input exponentially
transitions toward the output voltage. When the inverting input voltage matches the voltage at
the non-inverting input, the output voltage toggles to the other quasi-stable state. is output
toggling causes successive exponential change and toggling.
Rf
Rg
+
vo
−
C
R
Figure 13.6: An astable multivibrator.
e two quasi-stable output voltage states of the astable multivibrator are at fixed voltages, VH
and VL . When the output is in one of these states, the voltage state at the non-inverting (“C”)
comparator node is given by:
C Rg C Rg
vH D VH or vL D VL : (13.1)
Rg C Rf Rg C Rf
Just prior to a HIGH to LOW transition, for example, the output voltage is VH , the non-inverting
C
input is at vH , and the inverting input is in exponential transition from its initial value, vLC , toward
VH . is exponential transition will continue until the voltage at the non-inverting input matches
C
that at the inverting input, vH , at which time the output will toggle to VL . at is,
t
v .t / D VH VH vLC e RC : (13.2)
e total exponential transition time is the solution to the expression
C
v .t / D vH ; (13.3)
or
Rg t Rg
VH VH VL e RC D VH : (13.4)
Rg C Rf Rg C Rf
e transition time is given by:
( )
Rg C Rf VH Rg VL Rg .VH VL /
tHL D RC ln D RC ln 1 C : (13.5)
Rf VH Rf VH
A LOW to HIGH transition time is determined in the same manner: the expression is
the same as Equation (13.5) with VH and VL interchanged. As such, the duty cycle of the output
square wave can be altered somewhat. e period of this repeated output toggling becomes the
sum of the two transition times:

Rg .VH VL / Rg .VL VH /
D RC ln 1 C C ln 1 C : (13.6)
Rf VH Rf VL
e complexity of these expressions for transition time can be simplified greatly by assuming
a particular comparator operational configuration. Typically, an astable multivibrator is operated
with symmetric voltage limits, VL D VH . is operation practice results in identical transition
times and a 50% duty cycle:

Rg
tHL D tLH D RC ln 1 C 2 : (13.7)
Rf
In this case, the period of the repeated output toggling is twice the transition time:

Rg
D 2 tHL D 2RC ln 1 C 2 : (13.8)
Rf
In practice, the slew rate limitations of the circuit comparator will lengthen each of the transition
times lowering the frequency of operation somewhat. e waveforms associated with a symmetric
astable multivibrator are shown in Figure 13.7.
13.1.3 MONOSTABLE MULTIVIBRATORS

A monostable multivibrator produces a single output pulse, typically of precise amplitude and
duration, each time a trigger signal is applied to the input. As such, monostable multivibrators
are useful in transforming a train of pulses with variable amplitude and/or duration into a train of
pulses with standard amplitude and duration. e output during the single pulse is quasi-stable:
between pulses the output is stable.
VH vo(t)
+ v+(t)
vH
v–(t)
v+L
VL
Figure 13.7: Astable multivibrator waveforms.
An astable multivibrator can be transformed into a monostable multivibrator by stabilizing

one of the quasi-stable output states. e circuit of Figure 13.8 has its negative output, VL , sta-
bilized by the introduction of the stabilizing diode, DS . is diode prevents the inverting input,
v .t/, from becoming sufficiently negative to fall below the lower non-inverting state:
C Rg
v .t/ > vL D VL : (13.9)
Rg C Rf
C1 D1 Rf
v1
vin
R1
Rg
+
vo
−
R
•
DS C
Figure 13.8: A monostable multivibrator.

erefore, the comparator will not spontaneously toggle to the positive output state, VH . In order
for an external signal to trigger a pulse, the capacitive input circuit formed by C1 ; R1 , and D1 is
added. is input circuit allows a fast rise time pulse to momentarily lift the non-inverting input
above the inverting input which triggers a HIGH output.
As with the astable circuit, the monostable multivibrator output states are given by VH
(quasi-stable) and VL (stable). When the circuit is in the stable state, the two inputs to the com-
parator are:
C Rg
vL D VL and vL D V 0:7 V: (13.10)
Rg C Rf
A positive pulse applied to the input, vin , will raise the non-inverting input above the inverting
input and force the comparator output to the HIGH state, VH . e non-inverting input toggles
and the inverting input begins an exponential transition to VH :
C Rg
vH D VH ;
Rg C Rf
and (13.11)
t
v .t/ D VH VH vL e RC :
e exponential transition will continue until the voltage at the non-inverting input matches that
C
at the inverting input, vH , at which time the output will toggle to VL . e duration of the positive
pulse is given by the time of this exponential transition:
( )
Rg C Rf VH vL
tpulse D RC ln : (13.12)
Rf VH
After the output toggles LOW, the non-inverting input returns to its stable state, vLC , and the
inverting input begins an exponential transition toward VL :
C
t
v .t / D VL VL vH e RC : (13.13)
is exponential transition is halted by the diode, DS , before the inverting input is sufficiently
negative to toggle the comparator HIGH. Consequently, the LOW output state is stable. e
time to return to the stable state is given by:
( )
C
VL vH
trecovery D RC ln : (13.14)
VL vL
Once the monostable multivibrator returns to its stable state, it can be retriggered to output an-
other single pulse. e characteristic of a single output pulse for each triggering leads to the
common alternate identification of a monostable multivibrator as a one-shot. Typical monostable
vo(t)
VH
+
vH
–
vo(t)
v–L
trecovery
tpulse
v+L
VL
Figure 13.9: Monostable multivibrator waveforms.
multivibrator waveforms are shown in Figure 13.9. In order to ensure clean, single pulses, design
guidelines suggest that the input circuit time constant be small compared to the pulse duration.
One-shot circuits find greatest use in analog or asynchronous digital circuitry. Use in synchronous
digital circuitry is discouraged due to a variety of problems.

e monostable multivibrator circuit of Figure 13.8 is configured so that the two stable output
voltages are ˙10 V. Complete the design so that the circuit responds to a pulse input with an
output pulse of duration 10 ms. What is the recovery time for the design?
Solution:
e pulse duration is given by Equation (13.12):
( ) ( )
Rg C Rf VH vL Rg C Rf .10:7/
tpulse D RC ln D RC ln :
Rf VH Rf 10
In order to reduce the effects of stray noise, it is good practice to keep within the first two time
constants of the exponential decay. While many sets of component values will satisfy the con-
straints, the following set is chosen.
Choose RC D tpulse (one time constant) D 10 ms.
13.2. GENERATION OF SQUARE AND TRIANGULAR WAVEFORMS 979
One pair of standard components meeting this choice are:
R D 10 k and C D 1 F;
a further consequence of this choice is:
( )
Rg C Rf .10:7/
1 D ln :
Rf 10
One pair of standard value resistors that will meet this requirement are:
Rg D 15:4 k and Rf D 10 k:
e recovery time is determined by Equation (13.14). With the above choices for component
values it is:
10 5
trecovery D 10 k .1 / ln D 4:78 ms:
10 . 0:7/
13.2 GENERATION OF SQUARE AND TRIANGULAR

WAVEFORMS USING ASTABLE MULTIVIBRATORS
In electronic applications, the three most useful waveforms are:
• sinusoidal waveforms,
• square waveforms, and
• triangular waveforms.
Precision generation of these waveforms is vital to the proper operation of a wide variety of elec-
tronic devices and electronic test equipment. Square wave can be generated using by either passing
a sinusoid through a bistable circuit, such as a Schmitt trigger, or directly with an astable multi-
vibrator. Triangular waveforms can be obtained by integrating a square waveform. Simultaneous
generation of all three waveform types presents a challenge. Fortunately one form of astable mul-
tivibrator is capable of simultaneous generation of square and triangular waveforms: sinusoids can
be derived from the triangular waveform using non-linear waveshaping techniques.⁴
13.2.1 PRECISION SQUARE WAVE GENERATION

e astable multivibrator discussed in Section 13.1.2 is a near-ideal generator of square waves.
With symmetric output voltage levels, a uniform square wave is generated with period,

Rg
D 2RC ln 1 C 2 : (13.15)
Rf
⁴ese non-linear techniques are discussed in Section 13.3.
A precision square-wave generator based on this astable multivibrator is shown in Figure 13.10.
In this circuit the symmetric output voltage levels are ensured through the use of a back-to-back,
matched pair of Zener diodes.
Rf
+
vo
−
Rg R
Figure 13.10: An astable multivibrator square wave generator.
Alteration of the time symmetry of the waveform so that the HIGH output time is not
equal to the LOW output time is often desired in such a circuit. Two possible techniques used to
alter the symmetry are significant in any discussion of multivibrators:
• A monostable multivibrator (one-shot) is connected in series with the output of the circuit of
Figure 13.10. e monostable multivibrator is adjusted to output a pulse of varying duration
without varying the period of the waveform.
• e astable multivibrator circuit is modified so that the HIGH and LOW output times are
unequal.
Due to the significant increase in the complexity of the circuit, including the addition of another
comparator, the addition of a one-shot is usually not the best choice: minor modification of the
astable multivibrator is simple and effective.
While it has been shown that non-symmetric HIGH and LOW voltage states will lead to
non-symmetric waveforms, it is more common to vary the square-wave time symmetry through
control of the exponential RC time constant. e circuit shown in Figure 13.11 is one possible
multivibrator realization that provides different charging and discharging time constants. During
the HIGH output state, diode, D , conducts and diode, D 0 , is OFF. e circuit reduces to that
of Figure 13.10: the time constant is given by the product of RC . e addition of a diode in the
negative-feedback path reduces the voltage apparent to the charging network by V . Since the
charging time is not dependent on this voltage, the HIGHstate duration time is, as previously
derived:
Rg
tH D RC ln 1 C 2 : (13.16)
Rf
Rf
+
vo
−
Rg R' D'
C R D
Figure 13.11: An astable, non-symmetric square-wave generator.
When the output is in the LOW state, the operational modes of the two diodes, D and D 0 , are
interchanged and the alternate negative-feedback resistor, R0 , acts in the exponential decay. e
resultant LOW output state duration time is similarly given by:

0 Rg
tL D R C ln 1 C 2 : (13.17)
Rf
If the two negative-feedback resistors are not equal in value, R ¤ R0 , the HIGH and LOW
duration times are unequal and the square wave is asymmetric. e period of the asymmetric
square wave is given by the sum of the two duration times:

Rg
D tH C tL D R C R0 C ln 1 C 2 : (13.18)
Rf
Duty cycle is typically defined as the ratio of the HIGH state duration, tH , to the period, :
tH R
duty cycle D D : (13.19)
R C R0

Design a circuit using an astable multivibrator to produce a 10 kHz square-wave with a 35%
HIGH state duty cycle.
Solution:
When basing timing on RC decay, it is best to stay approximately within the first two time
constants. Choosing Rf D Rg will satisfy this guideline. It is also important to choose resis-
tors that will meet standard comparator resistance guidelines. erefore, within these guidelines,
arbitrarily choose:
Rg D Rf D 10 k:
en
1
D D 100 s D R C R0 C .1:0986/
f
.R C R0 /C D 91:024 s:
Arbitrarily choose a convenient value of C that will keep the resistor values, R and R0 , within
comparator resistance constraints. Here choose
C D 0:01 F ) R C R0 D 9:1024 k:
A 35% duty cycle implies

R
D 0:35 ) R D 0:53846 R0 :
R C R0
ese two constraints result in the final two standard-value resistors:
R0 D 5:916 k 5:90 k and R D 3:1858 k 3:20 k:
13.2.2 SIMULTANEOUS SQUARE AND TRIANGLE WAVE GENERATION

Astable multivibrators, as described previously (and shown in Figure 13.10), provide a square
wave output and a pseudo-triangular waveform as an internal signal. Unfortunately, this internal
waveform has voltage transitions that are exponential rather than linear. Transition linearity can
be achieved by replacing RC capacitive charging. Two distinct possibilities for linearization of
the signal are dominant in typical realizations:
• Current-source fed capacitive charging, or
• Integration of the square wave.
In the first possibility, the negative-feedback resistor, R, is replaced by a constant current device.
is current source typically has as its primary element, a FET operating in the saturation region.
e second possibility uses an OpAmp integrator to create a linearly varying signal. Since OpAmp
integrators invert the signal, the output of the integrator is fed back to the non-inverting terminal
of the comparator, as shown in Figure 13.12. In this form, the comparator takes the form of a
simple Schmitt trigger.
is astable circuit also has two quasistatic states. ey exist for the square wave output, vsq ,
at fixed voltages, VH and VH (once again, the symmetry is ensured by back-to-back, matched
Schmitt trigger integrator
Rin
Rf Vs +
vtr
+
−
− R
C
vsa
Figure 13.12: Triangular/square wave generator.
Zener diodes). e Schmitt trigger toggles between output states when the voltage at its non-
inverting input is at ground potential. is toggle requirement reflects back on the integrator
output, vtr , as:
Rin Rin
vtr.toggle/ D vsq D VH : (13.20)
Rf Rf
As previously stated, the time-dependent output, vtr .t/, is an inverted integral of the difference
between vsq .t/ and the symmetry-control voltage, Vs (a constant):
Z
1 ˚
vtr .t/ D vsq .t/ Vs dt: (13.21)
RC
When vsq is in the HIGH state vtr is linearly decreasing between its toggle values:
Z
1 Vs VH
vtr .t/ D fVH Vs g dt D t C (a HIGH constant): (13.22)
RC RC
e “HIGH constant” of integration need not be evaluated for this discussion. e time for the
decreasing voltage transition is given by the difference in toggle values divided by the slope of the
linear transition:

Rin VH Vs 2Rin RC VH
2 VH D t ) t D : (13.23)
Rf RC Rf fVH Vs g
When vsq is in the LOW state vtr is linearly increasing between its toggle values with a different
slope
Z
1 VH C Vs
vtr .t/ D fVH C Vs g dt D t C (a LOW constant): (13.24)
RC RC
While the difference in toggle values remains the same, the change in slope results in a different
transition time for the positive transition:

Rin VH C Vs 2Rin RC VH
2 VH D tC ) tC D : (13.25)
Rf RC Rf fVH C Vs g
e signal will continuously repeat the transitions. e period for the total waveform is the sum
of the transition times:
4Rin RC VH2
D t C tC D : (13.26)
Rf VH2 Vs2
e positive-slope duty cycle is given by the ratio of the positive transition time to the period:

tC 1 Vs
duty cycle D D 1 : (13.27)
2 VH
Symmetric waveforms (those with a 50% duty cycle) are obtained when Vs is at ground poten-
tial. Positive Vs results the positive-slope waveform segment having shorter duration than the
negative-slope segment (positive-slope duty cycle < 50%): negative Vs reverses the relationship.
In this circuit, the frequency of oscillation is also dependent on Vs : it is maximized when Vs D 0
and decreases in a non-linear fashion as the magnitude of Vs increases. e generator waveforms,
vtr and vsq , are shown in Figure 13.13 for positive Vs .
vsq
VH
Rin
V
Rf H
vtr
−Rin
V
Rf H
−VH
t− t+ τ
Figure 13.13: Triangle/square wave generator signals.
13.2.3 VOLTAGE-CONTROLLED FREQUENCY OF OSCILLATION

Control of the frequency of oscillation of a waveform generator is often important. e frequency
of oscillation for the waveform generator of Section 13.2.2 can be controlled by:
• variation of component values (typically R or C ), or
• variation of the symmetry signal, Vs .
A manually-controlled variable resistor or capacitor can be an adequate frequency control device
in many applications. Other design constraints may require that the frequency be controlled by
electrical, rather than mechanical, inputs. In particular, the need for a voltage-controlled oscillator
(VCO) is significant in many demodulation circuits for communication purposes.
While the circuit of Section 13.2.2 meets the voltage-control requirement, there are two
significant drawbacks to using this circuit as a VCO:
• a change in the frequency produces a change in the duty cycle
• the frequency depends on the control voltage in a non-linear fashion: the frequency is de-
pendent on 1 .VS2 VH2 ).
Square and triangle waves, with voltage controlled frequency, can be generated simulta-
neously with a circuit of the basic topology shown in Figure 13.14. is circuit is an astable
multivibrator where the rate of linearly charging a capacitor is decoupled from the amplitude of
the output of the square wave. is decoupling is accomplished by the insertion of a FET single-
pole, double-throw (SPDT) switch between the Schmitt trigger and the integrator. e SPDT
switch is controlled by the output of the Schmitt trigger: it alternately couples the input of the
integrator to either the frequency-control voltage, vm , or its negative, vm (usually obtained from
an OpAmp unity-gain amplifier). It is required that vm be positive and of sufficient magnitude
so that the switch operates properly.
Schmitt trigger +v
◦ m
C
Q1 − R
− vsq −
+ vtr
+ +
Q2
Rf ◦ −vm
Rg
FET switch & buffer Integrator
Figure 13.14: A voltage-controlled oscillator.

e output of the integrator, vtr , depends on vm and vsq :
Z
1 vm
vtr .t/ D ˙vm dt D t C a constant of integration: (13.28)
RC RC
When vsq is HIGH,the output of the FET switch is connected to vm : when vsq is LOW
the output of the switch is connected to Cvm . As in the previously discussed waveform generator,
the triangle wave transitions are linear with time. e duration of each transition is determined
from the toggle voltages and the slope of the transition. e toggle values for the Schmitt trigger
are obtained from a voltage division of its two output states: VH and VH :
Rg Rg
vtr.toggle/ D vsq D ˙ VH : (13.29)
Rf C Rg Rf C Rg
e time for the voltage transition is given by the difference in toggle values divided by the slope
of the linear transition:
2 Rg vm 2 Rg RC VH
VH D t ) tD : (13.30)
Rf C Rg RC Rf C Rg vm
Circuit symmetry implies that positive and negative transitions are of equal duration: the period
of oscillation is double that of a single transition:
4 Rg RC VH
D 2t D : (13.31)
Rf C Rg vm
e frequency of oscillation is the inverse of the period:

1 Rf C Rg vm
f D D : (13.32)
4 Rg RC VH
e results of Equation (13.32) indicate the desired linear dependence of frequency with input
voltage, vm . Typically, the linearity extends over three or more decades. If greater frequency vari-
ation is necessary, it must be accomplished through resistor switching (typically resistor, R, is
switched).

Design a voltage controlled oscillator that will output a 15 V peak-to-peak square wave of variable
frequency from 100 Hz to 2 kHz for an input voltage range of 0.1 V to 2 V.
Solution:
e output of the circuit shown in Figure 13.14 will satisfy all design requirements with
proper choice of components and component values. A square wave can be obtained at the vsq
terminal of the circuit. e 15 Vp p output voltage requirement is obtained by careful choice of
13.3. NON-LINEAR WAVEFORM SHAPING 987
the Zener diode matched pair. e pair is chosen so that 2 .Vz C V / D 15 V. is requirement
will result in diodes with a Zener voltage:
Vz 6:8 V:
e frequency variation is obtained from Equation (13.32). Using the lower range of frequency
and voltage, the resultant component constraint is:
Rf C Rg 0:1 Rf C Rg
100 D ) D 30; 000:
4 Rg RC 7:5 Rg RC
Many sets of component values will satisfy this constraint and keep within the standard compara-
tor resistance guidelines. One set is:
Rf D Rg D 10 k ) RC D 66:67 10 6
C D 4700 pF ) R D 14:2 k.
All these values are standard component values.
13.3 NON-LINEAR WAVEFORM SHAPING

Arbitrarily shaped, periodic signals can be derived from triangular waveforms through a two-port
network with an appropriate, non-linear transfer function. e non-linear property of the network
is usually derived using a piece-wise linear approximation through the introduction of a series of
breakpoints. Typically, the breakpoints are realized with diode⁵ or transistor switching networks.
While selectively filtering the harmonic content of the output of a multivibrator may seem to be
an effective, alternate means of waveshaping, this technique is usually not a practical solution.
e steep transition regions required to filter the various harmonics imply a very complex, high-
order filter design. In most situations the design goals can be more easily met by piece-wise linear
approximation. Digitally generated waveforms are another alternative that is particularly popular
in arbitrary waveform generators: the design of digital waveform generators is beyond the scope
of this discussion.
A general waveshaping network using diodes is shown in Figure 13.15. A triangle wave,
vtr , enters the network, is shaped by the piece-wise linear two-port network, and then buffered by
the unity gain amplifier: the shaped output is vo . e network is composed of an array of elements
consisting of a series-connected diode, resistor, and voltage sources. If the voltages fViC g consist of
a progressively increasing set of positive voltages, this portion of the array will progressively flatten
the waveform as it increases. Similarly, an increasing magnitude set of negative voltages fVi g will
progressively flatten the negative portion of the waveform. Reversing a diode in either the upper
or lower portion of the array will have the opposite effect on the waveform at the breakpoint.
⁵Diode switching networks to shape waveforms are initially introduced in Section 2.6 (Book 1).
e primary difficulty encountered in this form of array is provision for many independent
voltage sources. Surprisingly, design solutions are simplified by the switching nature of the ar-
ray. One possibility is the use of forward-biased diodes to specify the break-point voltages. In
order to demonstrate the utility of such an array, a simple triangle-to-sinusoid converter will be
demonstrated.
V1+ V+
2 ● ● ● V+
n
D1+ D+2 ● ● ● D+n
−
R1+ R+2 ● ● ● R+n vo
Rs
vtr ● ● ● +
R1− R−2 ● ● ● R−n
D1− D−2 ● ● ● D−n

V1− V2− ● ● ●
−
Vn
Piece-wise linear two-port Buffer
Figure 13.15: A piece-wise linear waveshaping circuit.
Example 13.5 Design Example: A Triangle-to-Sinusoid Converter

In order to produce a sinusoid of magnitude, Vs , from a triangle wave of magnitude, Vtr.max/ ; the
transfer function for the triangle-to-sinusoid converter must be given by the expression:

vtr
vo D Vs sin :
2 Vtr.max/
vtr ● ● vo
Rs
● ●
R1 ● ●
R2
● ●
It has been decided to approximate this transfer function with the seven-segment diode array
shown. Here the voltage sources are provided by forward-biased diodes. is array clips all in-
puts so that the maximum possible output is ˙3 V ˙1:8 V. ere are four other breakpoints
(progressively introduced by diode conduction) at ˙0:6 V and ˙1:2 V. e slopes of the transfer
function in the various regions are given by:⁶
m1 D 1 0:6 V < vo < 0:6 V
R1
m2 D 0:6 V < jvo j < 1:2 V
R1 C Rs
R1 R2
m3 D 1:2 V < jvo j < 1:8 V.
R1 R2 C R1 Rs C R2 Rs
e analytic expression for the slope of the transfer function is given by:

d vo Vs vtr
D cos ;
d vtr 2 Vtr.max/ 2 Vtr.max/
slope at the various breakpoints yields:
Vs 2
m1 jvtr D0 D 1 ) D :
Vtr.max/
For a 1:8 V magnitude sinusoid this expression implies that Vtr.max/ D 2:825 V.
At the first breakpoint vo D vtr D ˙0:6 V
m2 D 0:945 ) R1 D 17:17Rs :
At the second breakpoint vo D 1:2 V; vtr D 1:27 V
m3 D 0:7613 ) R2 D 2:690Rs :
Reasonable choices for the resistors, using standard values are:
Rs D 1 k R1 D 17:2 k and R2 D 2:7 k:
A PSpice analysis of the circuit was performed: e input and output waveforms are shown. Total
harmonic distortion of the near-sinusoidal output of this circuit was calculated to be about 1.0%:
a reasonable value for such a simple circuit. Typical converters usually have at least 6 breakpoints
on each side of ground.
⁶ese equations assume the forward dynamic resistance of the diodes is zero-valued. If the dynamic resistance can be reasonably
approximated, the resistor values, R1 and R2 , should be reduced by that approximation.
Triangle-tosinusoid converter
VS 1 0 PWL(0 -2.825 1M 2.825 2M -2.825)
RS 1 2 1K
D1P 2 10 D1N4148
D1N 10 2 D1N4148 4
R1 10 0 17.2K
D2P1 2 21 D1N4148
D2N1 22 2 D1N4148 2
D2P2 21 20 D1N4148
D2N2 20 22 D1N4148
Voltage (V)
R2 20 0 2.7K
0
D3P1 2 31 D1N4148
D3N1 33 2 D1N4148
D3P2 31 32 D1N4148
D3N2 34 33 D1N4148 -2
D3P3 32 0 D1N4148
D3N3 0 34 D1N4148
.TRAN .01M 2M 0 0.01M -4
.LIB NOM.LIB 0.0 500.0μ 1.0m 1.5m 2.0m
.PROBE Time (s)
.FOUR 500 V(2)
.END
Another similar form of piece-wise linear two-port network uses BJTs as the switching
device rather than diodes. A seven-segment array demonstrating this technique applied to triangle
to sinusoid conversion is shown in Figure 13.16.⁷ is design was based on the breakpoints and
slopes derived in Design Example 13.5. e BJT-based circuit has several advantages over the
diode-based circuit. Primary among the advantages is the flexibility concerning the amplitude of
vtr . As long as
VCC Vtr.max/ and 1:8 < Vtr.max/ < 15 V;
this circuits performs well with less than 1.5% total harmonic distortion. One particular drawback
is the rather strong dependence on the forward-biased dynamic resistance of the base-emitter
junctions of the various transistors. Performance is greatly dependent on these values (in the
design shown, the 2:7 k resistor was reduced to 2 k and the 17.2 k resistor was reduced to
14.3 k due to dynamic resistance considerations).
Another technique useful in the conversion of triangular waves to sinusoids is non-linear
amplification. A particularly useful circuit that employs this technique is shown in Figure 13.17.
e design utilizes logarithmic amplification obtained with an overdriven differential gain stage:
input triangle waves alternately force one the two BJTs to the verge of saturation.
In this amplifier the triangle wave is amplified linearly near the zero crossing: in the regions near
the peaks of triangle the amplification is logarithmic. For a well-controlled triangle voltage input,
⁷More complete discussion can be found in Grebene, 1984, pp 592–595.
● ● ● ◦ VCC
412 Ω
240 Ω
2 kΩ
● ●
●
240 Ω
14.3 kΩ
● ●
240 Ω
R R R
1 kΩ
vtr ◦ ● ◦ vo ● ● ● ● ● ● ●
R R R
240 Ω
14.3 kΩ
● ●
240 Ω
●
2 kΩ
● ●
240 Ω
●
412 Ω
R = 27 kΩ
● ● ● ◦ –VCC
Figure 13.16: A seven-segment triangle to sinusoid converter.
the resultant transfer function is near-ideal and produces a low-distortion sinusoid output, vo .
Optimal performance occurs with
52 mV < I1 R < 86 mV;
and
Vtr.max/ 95 mV:
VCC
RL RL
– vo +
vtr
R
I1 I1
VEE
Figure 13.17: Differential pair triangle-sinusoid non-linear amplifier.
A logarithmic triangle-sinusoid converter is particularly useful at high frequencies where the

higher-voltage input requirement of piece-wise linear converters may be difficult to produce with
sufficient accuracy.
13.4 INTEGRATED CIRCUIT MULTIVIBRATORS

An alternative to the realization of multivibrators with discrete elements exists in the form of
an integrated circuit package. ese IC packages, commonly identified as IC timers, contain the
primary components needed to implement monostable and astable multivibrators: a minimum
number of external components is necessary to complete the multivibrator design. Among the IC
timers currently available, the 555 timer has gained widest acceptance due to its versatility and
low cost.
e basic functional block diagram of a 555 timer is shown in Figure 13.18. It consists of
two comparators, a resistive network that sets the trigger levels of the comparators, a transistor
that acts as a switch, and a set-reset (SR) flip-flop. e three internal resistors, labeled R, divide
the input voltage, VCC , so that the voltage trigger levels of the two comparators, CP1 and CP2 , are
at 2=3 VCC and 1=3 VCC , respectively. ese trigger levels can be altered by applying an external
voltage at the Control input terminal. e outputs of the comparators control the state of the
SR flip-flop. An SR flip-flop is a form of bistable circuit:⁸ it is a level retention circuit with
complementary outputs Q and QN . e output, Q, transitions to match the S input when only
one input is HIGH. When both inputs are LOW the flip-flop retains its last value of Q and holds
it until at least one input transitions to HIGH. e terms set and reset refer to the action of the
output, Q. Q sets (transitions to HIGH) when the set input, S , is HIGH: Q resets (transitions
⁸More information on the characteristics of flip-flops can be found in Section 16.5.
13.4. INTEGRATED CIRCUIT MULTIVIBRATORS 993
to LOW) when the reset input, R, is HIGH. e transistor switch shorts the Discharge input to
ground when QN is HIGH.
◦ VCC ◦ Reset
◦
Discharge
R
Threshold CL
◦ +
CP1 R Q ◦vo
Control −
◦ •
R flip-flop
• +
–
CP2 S Q
Trigger −
◦
◦ Ground
Figure 13.18: Simplified functional diagram of 555 IC timer.
e 555 timer is available in both bipolar and CMOS technologies. In various forms it is capable
of producing timing signals with a duration that ranges from microseconds to hours. Astable
oscillation up to a few Megahertz is possible. While many functional operations can be performed
with this circuit, discussion will be limited to a monostable multivibrator (one-shot) and an astable
multivibrator (non-linear oscillator).
13.4.1 A 555 TIMER MONOSTABLE MULTIVIBRATOR

Timing operations, using a 555 timer, are typically based on the charging and discharging of
external networks. Most fundamental of these timing operations is that of a monostable multi-
vibrator. e 555 timer implementation of a monostable multivibrator is shown in Figure 13.19.
Here the timed interval is controlled by a single external RC network. e basic connections are
as follows:
• A capacitor, C , is connected from the threshold input to ground.
• A resistor, RA , is connected from the threshold input to the positive power, VCC .
• e discharge and threshold inputs are shorted together.
• e reset input is held HIGH.
• e control input is left open (or connected through a small capacitor to ground).
e stable state of this circuit exists when the output, Q, of the flip-flop is LOW. In order to
achieve that state the input, vin , must be greater than the trigger level of CP2 . In this state, the
complementary output of the flip-flop, QN is HIGH. is causes the transistor switch to activate,
forcing a rapid discharge of the capacitor voltage to essentially zero. e output of CP1 is LOW.
e output of each comparator is therefore LOW: the LOW inputs to the flip-flop retain the
LOW output until an input change occurs.
RA
◦• ◦• Rst ◦V
VCC CC
◦•
Dis
R
Thd CL
◦• +
CP1 R Q ◦vo
C ◦ ◦• −
Ctl
R flip-flop
◦• +
–
CP2 S Q
vin◦ −
Trg
R
◦• 555 Timer
◦• Gnd
Figure 13.19: A 555 timer monostable multivibrator.
e quasi-stable state occurs when the input voltage, vin , momentarily drops below the
trigger level of CP2 :
vin < VCC =3: (13.33)
is change in input level forces the output of CP2 to a HIGH state, setting the flip-flop (Q,
HIGH and QN LOW). e QN output of the flip-flop deactivates the transistor switch and allows
13.4. INTEGRATED CIRCUIT MULTIVIBRATORS 995
the capacitor to begin charging toward the positive power voltage, VCC :
t

vc .t/ D VCC 1 e RA C : (13.34)
e charging will continue until vc .t / exceeds the trigger voltage of CP1 . e duration of the
charging is given by the solution to:
2VCC t

D VCC 1 e RA C
) t D RA C ln .3/ : (13.35)
3
When vc .t/ reaches the trigger level the output of CP1 goes HIGH. If the input signal vi .t / has
returned HIGH, the flip-flop changes state and returns to Q D LOW: a single HIGH pulse of
duration RA C ln.3/ is formed. If vi .t/ is still LOW, the HIGH pulse continues until vi .t/ goes
HIGH at which time the pulse terminates.
13.4.2 A 555 TIMER ASTABLE MULTIVIBRATOR

An astable multivibrator where the frequency of oscillation and the duty cycle can be indepen-
dently controlled with two external resistors and a single external capacitor is shown in Fig-
ure 13.20. In this configuration, the HIGH duty cycle is limited to the range of 50% to 100%.
e basic connections are as follows:
• A capacitor, C , is connected from the trigger input to ground.
• A resistor, RA , is connected from the discharge input to the positive power, VCC .
• A resistor, RB , is connected from the threshold input to the discharge input.
• e trigger and threshold inputs are shorted together.
• e reset input is held HIGH.
• e control input is left open (or connected through a small capacitor to ground).
In this astable configuration, the capacitor voltage, vc .t /, transitions exponentially between the
trigger levels of the two comparators (established by the resistors labeled R):
VCC 2 VCC
vc .t/ : (13.36)
3 3
Both the direction and rate of capacitor voltage transition are controlled by the switching tran-
sistor. When vc .t/ is between the trigger levels, both comparators will have a LOW output: this
output state signals the flip-flop to retain its last output state. When vc .t / reaches the upper trig-
ger level, the output of CP1 momentarily changes to a HIGH: this action activates the reset state
of the flip-flop (Q, LOW and, QN HIGH). e output of the flip-flop activates the transistor
RA
◦• V ◦• Rst ◦V
CC CC
◦•
Dis
RB R
Thd CL
◦• +
◦• CP1 R Q ◦vo
◦ • −
Ctl
R flip-flop
• +
–
CP2 S Q
Trg
◦• −
C R
• 555 Timer
◦• ◦• Gnd
Figure 13.20: A 555 timer astable multivibrator.
switch which forces the capacitor to begin an exponential discharge through the resistor, RB , to
ground:
2 VCC t
vc .t / D e RB C : (13.37)
3
As soon as the voltage drops below the upper trigger level, the output of CP1 returns LOW,
however, the flip-flop retains its output state and the discharge continues. It continues until vc .t/
reaches the lower trigger level. e duration of this discharging transition, td , occurs at the solu-
tion to:
VCC 2 VCC td
D e RB C ) td D RB C ln .2/ : (13.38)
3 3
When vc .t/ reaches the lower trigger level, the output of CP2 momentarily changes to a HIGH:
this action activates the set state of the flip-flop (Q, HIGH and QN LOW). e output of the
flip-flop deactivates the transistor switch which forces the capacitor to begin exponential charging
through the resistors, RA and RB , toward VCC :
2 VCC t
ŒRA CRB C
vc .t / D VCC e : (13.39)
3
As soon as the voltage rises above the lower trigger level, the output of CP2 returns LOW, how-
ever, the flip-flop retains its output state and the charging continues. It continues until vc .t/
reaches the upper trigger level. e duration of this charging transition, tc , occurs at the solution
to:
2 VCC 2 VCC tc
ŒRA CRB C
D VCC e ; (13.40)
3 3
or
tc D ŒRA C RB C ln .2/ : (13.41)
e transitions continue indefinitely producing a non-linear oscillation. A HIGH output occurs

during the charging transition and a LOW output occurs during the discharging transition. e
period of oscillation is given by the sum of the transition times:
D tc C td D ŒRA C RB C ln.2/ C RB C ln.2/ D ŒRA C 2RB C ln.2/; (13.42)
or
0:693ŒRA C 2RB C: (13.43)
e HIGH duty cycle is given by the ratio of tc to :

tc RA C RB
duty cycle D D : (13.44)
RA C 2 RB
Since it is not possible to set RA D 0 and still have a functioning astable multivibrator, the HIGH
duty cycle will always be greater than 0.5 (50%). e output voltage and capacitor voltage wave-
forms for a 60% duty cycle 555 timer astable multivibrator are shown in Figure 13.21.

A variety of circuits that generate non-sinusoidal waveforms has been presented in this chapter.
ese circuits are based on electronic multivibrators. Multivibrators are classified into three basic
types based on the stability of the output states:
• Bistable Multivibrator—two stable output states.
• Astable Multivibrator—two quasi-stable output states.
• Monostable Multivibrator—one stable and one quasi-stable output state.
Bistable multivibrators provide two distinct output states when appropriately triggered: one of the
most useful of these circuits is the Schmitt trigger. A Schmitt trigger performs the particularly
useful task of noise elimination through hysteresis in its transfer function. Astable multivibrators
VCC vo(t)
2/ V
3 CC
vc(t)
1/
3 VCC
0
tc td
τ
Figure 13.21: Waveforms for 555 timer astable multivibrator (60% duty cycle).
are non-linear oscillators that provide periodic square and/or triangular waveforms. Monostable
multivibrators provide a single output pulse of fixed duration when triggered. Monostable and
astable multivibrators can be realized through the use of an IC timer. Most dominant among IC
timers is the 555 timer family.
Arbitrary, periodic waveforms can be derived from triangular waveforms. A technique to
generate arbitrary waveforms using diode clipping circuitry is commonly used. Low harmonic
content sinusoids can be generated using this technique or by non-linear amplification.
Summary Design Example

e transmission of digital computer signals over standard telephone lines requires the use of a
modulator-demodulator unit known as a modem. Typically, modems transmit 2400 digital pulses
per second. In the construction of such a device, a local square-wave oscillator is often required at
that frequency. In order to interface with other digital circuits, the output of the oscillator must
be TTL compatible. ese design goals reduce to the following specifications:
f D 2400 Hz VH 5 V VL 0 V:
Design such a device so that the square-wave duty cycle lies between 40% and 60%.
Solution:
e obvious design alternatives are:
• a linear oscillator,
• a discrete-element astable multivibrator, or
• an IC timer astable multivibrator.
e two astable multivibrator types have a distinct advantage in complexity, size, and cost over a
linear oscillator at this low frequency. In addition the TTL compatible output voltage levels lead
to a 555 timer realization as an extremely advantageous choice. erefore, the 555 timer circuit
topology shown in Figure 13.20 is chosen as the basis for this design.
e specifications lead to specific parameter values needed in this design. If VCC D 5 V, the
output voltage levels will meet specification. e frequency of oscillation requirement leads to:
1
ŒRA C 2RB C ln.2/ D D 416:7 s:
2400
Arbitrarily choose the capacitor to be a convenient standard value:
C D 0:027 F ) RA C 2RB D 22:26 k:
A 555 timer can only have duty cycle greater than 50%. Arbitrarily choose the duty cycle to lie
easily within the design goals at 55%. is choice leads to a ratio of resistor values:
RA C RB D 0:55ŒRA C 2RB ) RB D 4:5RA :
Combining the two constraining equations for resistance values leads to standard-value resistors
of value:
RA D 2:23 k and RB D 10:0 k:
e design is complete. If exact-value components are used the computed frequency is 2403:7 Hz
(0.15% error) with a duty cycle of 55.02% (within specifications).
Design Verification Using SPICE

Most versions of SPICE are supplied with a macromodel of a CMOS version of the 555 timer.
e simple astable multivibrator oscillator in this design example can be modeled as:
A plot of the output and capacitor voltages is shown below. e simulation yields a square wave
of frequency 2378 Hz ( 0.92% error) with 54.5% duty cycle (within specifications).
6 (425.00u, 4.853)
4
Voltage (V)
(302.19u, 2.000)
(531.28u, 2.000) (722.66u, 2.000)
(625.00u, 495.0u)
-2
0 250µ 500µ 750µ 1m
Time (s)
13.6. PROBLEMS 1001
13.6 PROBLEMS
13.1. A simple Schmitt trigger has the following design requirements:
• stable output voltages at ˙5 V.

• reference voltage, vr D 0 V.
• threshold voltages, VTC D ˙1 V.
Design a circuit to meet these requirements to within ˙0:05 V.
13.2. A sinusoidal input voltage

v.t / D A sin.1000 t/;
is the input to the simple Schmitt trigger circuit created in Design Example 13.1. Quan-
titatively describe the output voltage if:
(a) e input sinusoidal amplitude is 1.0 V (i.e., A D 1:0).

(b) e input sinusoidal amplitude is 0.4 V (i.e., A D 0:4).
Assume the output voltage is zero-valued at t D 0.
13.3. A non-inverting Schmitt trigger has the following design requirements:
• stable output voltage at ˙10 V.

• positive slope threshold voltage, VTC D 2 V.
• negative slope threshold voltage, VT D 0 V.
13.4. An inverting Schmitt trigger has the following design requirements:
• stable output voltage at ˙10 V.

• positive slope threshold voltage, VTC D 1:5 V.
• negative slope threshold voltage, VT D 3 V.
13.5. Another form of OpAmp Schmitt trigger is shown.
(a) Determine the transfer characteristic as a function of the circuit parameters. Assume
Vref < VCC 2.
(b) If the circuit is constructed with the following circuit element values, what are the
threshold and output voltages?
Rg D 8:2 k R D 1 k
Vref D 4 V VCC D 15 V.
(c) Use SPICE to verify the results of part b).
◦ +Vref
R
Rin
vin◦
● R
+
Rg
● vo
−
R
Rf R
◦
–Vref
13.6. Design an astable multivibrator to produce a symmetric square wave of frequency 2 kHz.
Verify the design using SPICE.
13.7. Design an astable multivibrator to produce a symmetric square wave with amplitude,
6 Vp p and frequency, 1.2 kHz. Verify the design using SPICE.
13.8. e astable multivibrator circuit shown is constructed with the following component
properties:
Rf D 2 k D1 W V D 0:6 VI Vz D 6:4 V
Rg D 1 k D2 W V D 0:6 VI Vz D 3:4 V.
(a) What are VH and VL ?

(b) Determine the HIGH duty cycle (tHL = ).
(c) Complete the design by choosing component values R and C so that the circuit will
oscillate at 1 kHz.
(d) Verify the results using SPICE.
13.6. PROBLEMS 1003
Rf
Rg
●
+
● vo
−
R
● ●
D1
C D2
●
13.9. Design an astable multivibrator to produce a square wave of frequency 500 Hz with a
HIGH state duty cycle of 40%. It is required that VH D 5 V: VL may be varied. Verify
the design using SPICE.
13.10. Design an astable multivibrator to produce a square wave of frequency 500 Hz with a
HIGH state duty cycle of 40%. It is required that VH D VL D 5 V. Hint: In order
to have different time constants for the two transitions, diodes may be placed in the
discharge path. Verify the design using SPICE.
13.11. Design a one-shot circuit that responds to a pulse input with an output pulse of duration
3 ms. Verify the design using SPICE (any OpAmp macromodel will suffice in modeling
a comparator in this application).
13.12. Design a one-shot circuit that responds to a pulse input with an output pulse of duration
1.0 ms. Verify the design using SPICE (any OpAmp macromodel will suffice in modeling
a comparator in this application).
13.13. A stable 120 Hz pulse train of amplitude 5 V is required. Since commercial power is
extremely stable, it has been decided to use the 60 Hz, 110 V power-line voltage as a
triggering source for this pulse train. Design a system that will produce the required
pulse train using a simple one-shot based on the simple design topology shown. Verify
Input System Output
full-wave
one-shot
rectifier
60 Hz, 100 VAC 5 Vp-p, 120 Hz
13.14. A stable 60 Hz pulse train of amplitude 10 V is required. Using commercial power-line

input and a design topology similar to that in the previous problem, design a system to
produce the required pulse train. Verify the design using SPICE.
13.15. Design an astable multivibrator to produce a 340 Hz symmetric triangle wave with peak-
to-peak amplitude of 8 V. Verify the design using SPICE.
13.16. Design an astable multivibrator to produce a 500 Hz triangle wave with an amplitude of
10 V peak-to-peak and a 40% positive slope duty cycle. Verify the design using SPICE.
13.17. It is suggested that a device to sound the orchestral tuning note (A D 440 Hz) could be
inexpensively mass-produced using an astable multivibrator as the tone oscillator. e
presence of harmonics of the 440 Hz tone in the output is desirable.
(a) Design an astable multivibrator to produce that frequency.

(b) Trained musicians are easily capable of determining pitch (frequency) error of
˙3 cents. A cent is defined as 1% of a semitone, where a pitch transition of a semi-
tone produces a change in frequency by a factor of the twelfth root of two. us,
pitches (when compared to the ideal pitch frequency, fo ) that are considered “in
tune” must lie within the frequency range:
p 1003 p 100
3
3 3
12 12
2 fo < f < 2 fo ) 2 1200 fo < f < 2 1200 fo :
Comment on the practicality of using the design of part a) for this mass-produced device.
13.18. Design a voltage controlled oscillator that will output a 10 V peak-to-peak square wave
of variable frequency from 50 Hz to 1 kHz for an input voltage range of 0.2 V to 4 V.
13.19. Design a voltage controlled oscillator that will output a 10 V peak-to-peak triangle wave
of variable frequency from 50 Hz to 4 kHz for an input voltage range of 0.1 V to 8 V.
13.20. e diode network shown is a proposed triangle-to-sinusoid converter. It is said to be

capable of taking a 20 Vp-p triangle-wave input and produce a sinusoid with less than 3%
total harmonic distortion. Unfortunately the design does not include the proper value for
the reference voltages ˙Vref .
(a) Determine the break point voltages as a function of Vref (assume Vref > V ).
(b) Choose an appropriate value for Vref and determine the total harmonic distortion
of the output using SPICE.
(c) Try another value for Vref . Compare the resultant output total harmonic distortion
with that of part b).
13.6. PROBLEMS 1005
◦ +Vref
• •
6.34 kΩ 1.30 kΩ
•
6.81 kΩ 1.96 kΩ
• • •
vin 7.87 kΩ 4.02 kΩ 10.0 kΩ

◦ • • •
7.32 kΩ 15.0 kΩ
• •
−
v
• ◦ out
• • +
◦ –Vref
13.21. Design, using the basic topology shown in Figure 13.15 (some diodes must be reversed),
a seven-segment expanding wave-shaping network for use in the receiver of the digital
telephony system described above. e desired design characteristics are:
vo D vin , jvin j < 1

vo D 2 vin 1, 1 < vin < 2 vo D 2 vin C 1, 1 > vin > 2
vo D 4 vin 5, 2 < vin < 3 vo D 4 vin C 5; 2 > vin > 3
vo D 8 vin 17, 3 < vin < 4 vo D 8 vin C 17, 3 > vin > 4.
Hint: An amplifier is needed in addition to the passive diode network.
13.22. One common use of non-linear waveshaping occurs in digital telephony. Analog-to digi-
tal (A/D) conversion introduces the same quantization noise for small-amplitude signals
than for large-amplitude signals. us, small signals appear to have more relative noise
due to the A/D conversion than large signals. In order to equalize the signal-to-noise
ratio, the input message is amplified in a non-linear fashion prior to A/D conversion:
this process is called compressing. Upon receipt, the message is digital-to-analog (D/A)
converted and non-linearly amplified to restore linearity, this process is called expand-
ing. Together the two processes are called companding. Design, using the basic topology
shown in Figure 13.15, a seven-segment compressing wave-shaping network with the
following characteristics:
vo D vin , jvin j < 1
vo D 0:5 .vin C 1/, 1 < vin < 3
vo D 0:25 .vin C 5/, 3 < vin < 7
vo D 0:125 .vin C 17/, 7 < vin < 15
vo D 0:5 .vin 1/, 1 > vin > 3
vo D 0:25 .vin 5/, 3 > vin > 7
vo D 0:125 .vin 17/, 7 > vin > 15.
13.23. Design a monostable multivibrator using a 555 timer with a pulse output of duration
10 ms. e input is a 5 V signal that drops to 0 V for a duration of 1 ms to trigger the
multivibrator.
13.24. Series connection of IC timers can produce an output consisting of a delayed pulse of
fixed duration. e first timer fixes the delay, with its negative transition triggering the
second timer. e second timer sets the duration of the output pulse. e two timers are
capacitively coupled with a pull-up resistor on the input of the second timer: the RC
time constant of this coupling circuit must typically be less than 50 s (for a 555 timer).
Design such a two IC timer circuit that will produce an output pulse that is delayed from
an input triggering pulse. e design specifications are:
Input trigger — 5 V to 0 V for 10 s

Output delay — 2 ms ˙ 10 s
Output duration — 0.5 ms ˙ 10 s.
Use SPICE to verify the design.
13.25. Verify the waveforms shown in Figure 13.21 by designing a 555 timer astable multi-
vibrator to oscillate at 2 kHz with 60% HIGH duty cycle. Use SPICE to display the
waveforms.
13.26. e expression for the output-waveform duty cycle of an IC timer oscillator is given by
Equation (13.44). A 50% duty cycle implies that RA D 0 (the discharge and VCC terminals
are shorted together). Explain why the circuit will not oscillate with a 50% duty cycle.
Use SPICE simulation to verify that the circuit will not oscillate.
13.27. e circuit shown purports to use an IC timer to produce square-wave oscillation with a
50% duty cycle. e design parameters are:
1
f D and R2 > 10R1 :
1:386 R1 C1
(a) Use this circuit topology to design a 540 Hz oscillator.

13.6. PROBLEMS 1007
(b) Use SPICE and the macromodel of a 555 timer to check the design for frequency
and duty cycle compliance with specifications.
(c) If design parameters are not met, explain any mechanisms that cause the variation.
+10 V◦ R2 ◦vo
• •
Rst VCC Vo R1
Trg •
◦ Dis IC Timer
•
Thd
Ctl Gnd
C1
10 µF
•
13.28. e circuit shown is a voltage-to-frequency converter based upon linear charging of a ca-
pacitor by a constant current source. Use SPICE and the macromodels for a 741 OpAmp
and 555 timer to determine the linearity of the voltage-to-frequency conversion over the
range 0:5 V < vin < 5 V:
◦+5 V
• • •
Rst V•CC
• 10 kΩ
vin
◦ + Trg
•
Vo • ◦vo
− IC
• • Thd Timer
•
Ctl •
430 Ω Dis
Gnd
0.1 µF
0.47 µF
• •
13.29. One-shot circuits that use an IC timer have a very rapid recovery time. is rapid recovery
creates opportunities for unusual applications of the timer. One application is the use of
an IC timer monostable multivibrator (one-shot) to divide the frequency of a pulse train.
In order to divide the frequency by a factor, N , the pulse duration of the of the one-shot
is chosen to lie in the range:
.N DC / < t < N ;
where is the period of the original pulse train and DC is the HIGH state duty cycle
given as a fraction rather than a percentage. e trigger terminal serves as the input to the
frequency divider. Design, using a 555 timer, a circuit that will divide the frequency of
a 10 kHz square wave (DC D 0:5) by a factor of three (N D 3). Verify the design using
SPICE.
13.30. e circuit shown may be used to detect irregularities in a train of pulses. As long as the
pulse spacing is shorter than the timing interval of the timing circuit, the monostable
circuit is continuously triggered. Pulse spacing greater than the timing interval or the
termination of the pulse train allows completion of the timing interval and the generation
of an output pulse.
(a) Assume a pulse train input at 1 kHz with a LOW duty cycle of 20%. Complete the
design so that a missing LOW pulse will be detected (the pulse spacing is effectively
increased by the absence of a pulse).
(b) Test the design of part a using SPICE.
◦ +5 V
• • •
Rst V•CC R RL
vin◦ • Trg
Vo • ◦vo
IC
Dis •
Timer
Thd •
Ctl C
Gnd
0.1 µF
•
13.7 REFERENCES
Linear Circuits Data Book, Volume 3, Voltage Regulators/Supervisors, Comparators, Special Func-
tions, and Building Blocks, Texas Instruments Inc., Dallas, 1992.
Grebene, Alan B., Bipolar and MOS Analog Integrated Circuit Design, John Wiley & Sons,
New York, 1984.
Hambley, Allan R., Electronics, A Top-Down Approach to Computer-Aided Circuit Design,
Macmillan Publishing Company, New York, 1994.
Millman, Jacob, Microelectronics, Digital and Analog Circuits and Systems, McGraw-Hill
Book Company, New York, 1979.
Millman, Jacob and Taub, Herbert, Pulse, Digital, and Switching Waveforms, McGraw-Hill
Book Company, New York, 1965.
Savant, C.J., Roden, Martin S., and Carpenter, Gordon L., Electronic Circuit Design, An
Engineering Approach, e Benjamin/Cummings Publishing Co., Menlo Park, 1987.
Sedra, Adel S. and Smith, Kenneth C., Microelectronic Circuits, Saunders College Publish-
ing, Phil.
Wojslaw, Charles F. and Moustakas, Evangelos A., Operational Amplifiers, John Wiley &
Sons, New York, 1986.
1011
CHAPTER 14
Power Circuits
All the electronic circuits described in the first three sections of this book have as their main pur-
pose the modification of an input signal so as to perform useful work on the load. is signal
modification may take the form of signal amplification, frequency filtering, digital logical opera-
tions, or a variety of other possibilities. Inherent in all designs is an electrical power source. Most
often this source is a DC voltage source: in some instances, the DC is derived from AC source.
e proper operation of all electronic circuitry depends on the application of uniform electrical
power in the form of these sources. Power electronic circuits are responsible for converting the
available electric energy into a form with appropriate uniformity.
Regardless of the form of the input electrical energy (AC, DC, or a combination) the basic
form of an electrical power system remains consistent. A typical electrical power system is shown
in Figure 14.1. In such a system the input energy is filtered, converted to a new form, or shifted to
a new level by an electrical power circuit, and again filtered. Electronic (or possibly mechanical)
observation of the load conditions is an important factor in control of all operations.
Electrical
Input Power Output
Energy Load
Filter Circuit Filter
Source
Electrical
Feedback
Control
Circuit
Mechanical
Feedback
Power Electronic System
Figure 14.1: Typical electronic power system.
Previous chapters have described the principles of AC to DC conversion through the use
of diode half-wave or full-wave rectifiers followed with a simple passive low-pass filter (active
filtering is extremely inefficient in power applications). e benefits of feedback on stability have
also been discussed. is chapter focuses on combining previously explored devices and principles
into power circuits useful to the electronic designer. While many of these devices are commercially
available in IC packages, knowledge of the principles of operation is valuable to the prudent device
user or circuit designer.
1012 14. POWER CIRCUITS
Within many power circuits there exists the need for a high-power switch. BJTs and FETs
are extremely useful as switching elements and have previously been discussed. Both of these
transistor switches find common use in power circuits. yristors form another family of semi-
conductor devices that are extremely useful in switching applications. Most common among this
family are the Silicon controlled rectifier, typically used in DC applications, and the triac for AC
applications.
Voltage regulators are a common device available for providing a stable DC output voltage
for a wide range of input voltage and output current. As realized in a three-pin IC package, these
regulators are extremely effective, easy to implement, and inexpensive. e internal design of
both linear and switching regulators is discussed. While the design of DC power supplies is not
specifically addressed in this chapter, many of the design principles of simple voltage regulators
can be applied to their more powerful relative.
Protection against high-voltage transient or the accidental application of an overvoltage
is another major concern of the electronic designer. Several types of transient suppressors are
discussed. Similarly, several overvoltage protection circuits are described.
14.1 THYRISTORS
yristors are a form of solid state switch that is activated by a triggering signal. Prior to activation,
a thyristor acts as an extremely high-impedance path: once activated, a thyristor acts as a low-
impedance path and remains activated until the switched current falls below a minimum value,
the holding level, at which time it deactivates. Once a thyristor is activated, the triggering signal
is no longer necessary to continue activation unless low switched current deactivates the thyristor.
e most common members of the thyristor family include:
• Silicon controlled rectifiers (SCRs)
• Triacs
• Programmable unijunction transistors (PUTs)
• Silicon bilateral switches (SBSs)
• Sidacs
Silicon controlled rectifiers are most commonly used as power control elements, triacs are bi-
directional switches and are most useful in AC power applications under 40 Amperes, pro-
grammable unijunction transistors are most often used in timer circuits, Silicon bilateral switches
are most commonly used as gate trigger devices for the power control elements, and Sidacs are
a high voltage bilateral trigger device. e thyristor family also includes the gate turnoff (GTO)
thyristor: a device capable of being turned off, as well as on, with the application of different
polarity gate current. e GTO thyristor typically is used in power inverters (DC to AC power
converters).
14.1. THYRISTORS 1013
yristors have several distinct advantages over mechanical switches. Primary among these
advantages over mechanical switches are:
• High switching speed.
• Low energy switch triggering.
• Automatic debounce characteristics.
• Zero-current deactivation avoids contact arcing in inductive circuits.
While each type of thyristor has its particular uses, discussion in this chapter will be limited to
the two most commonly used thyristor types, the SCR and the Triac. Several SCR applications
will be presented in later sections of this chapter.
14.1.1 THE SILICON CONTROLLED RECTIFIER

e Silicon controlled rectifier (SCR) is the foundation element of the thyristor family. Its circuit
symbol is shown in Figure 14.2. e three SCR terminals take their names from diode terminol-
ogy and are identified as:
A – anode
K – cathode
G – gate
e SCR can conduct currents in excess of 50 Amps from the anode to the cathode and is capable
of blocking voltages up to 800 V. e gate terminal is the input for the triggering signal.
A K
Figure 14.2: e SCR circuit symbol.
SCRs have a four-layer structure of alternating p -type and n-type semiconductor material.
Conceptually, this structure takes the form of Figure 14.3a. e structure functionally acts as two
complementary BJTs connected as shown in Figure 14.3b.
Analysis of the SCR equivalent circuit leads to its modes of operation. e SCR has two funda-
mental operational states:
• An OFF state where only extremely small leakage currents pass from the anode to the
cathode. In this state transistor Q1 is cutoff and Q2 is in the forward-active region, albeit
with extremely low current flow.
• An ON state where current flows freely between anode and cathode. Here both transistors
are in saturation.
A
IA
Q2
p
n • Q1
p
IG
n
IK
G
K K
(a) (b)
Figure 14.3: SCR structure (a) Typical medium-power SCR semiconductor structure; (b) Equivalent
circuit.
In order to understand the transition between modes, it is necessary to examine the basic transistor
current relationships:
IC1 D ˛1 IE1 C ICO1 D ˛1 IK C ICO1 ; (14.1)
and
IC 2 D ˛2 IE 2 C ICO2 D ˛2 IA C ICO2 : (14.2)
Here the two quantities ICO1 and ICO2 are the collector leakage currents of each transistor¹ (with
an open emitter) and ˛1 and ˛2 are the collector-emitter current ratios. Note that in this for-
mulation, ˛i is transistor-region dependent and is only equal to ˛Fi in the forward-active region.
Kirchhoff ’s current law applied to the SCR equivalent circuit of Figure 14.3b yields expressions
for the currents into the anode and out of the cathode of the SCR:
IA D IC1 IC 2 ; (14.3)
and
IK D IA C IG D IC1 IC 2 C IG : (14.4)
e above four equations can be combined to determine the SCR anode current as a function of
the transistor parameters and the gate current:
IA D f˛1 .IA C IG / C ICO1 g f ˛2 IA C ICO2 g ; (14.5)
¹Since Q1 is an npn BJT, the collector leakage current, ICO1 , is a positive quantity. Q2 is a pnp BJT and has negative ICO2 .
which leads to
˛1 IG C ICO1 ICO2
IA D : (14.6)
1 .˛1 C ˛2 /
When the control transistor, Q1 , is OFF, ˛1 0 and ˛2 < 1: the SCR anode current is a
small multiple of the sum of the magnitude of the leakage currents. As current is applied to the
gate of the SCR and Q1 begins to turn on, ˛1 increases until the denominator of Equation (14.6)
becomes zero. is singularity in the expression for the anode current, IA , is physically realized
by a rapid increase in the anode current until it is limited by the external circuitry to which the
SCR is connected. At that current limiting point, IG may be removed and the two BJT leakage
currents will suffice to latch the SCR in the ON state. SCR deactivation will only occur when
the anode current drops to zero value due to external circuit circumstances. SCR reactivation will
occur when VAK is again positive and a current pulse enters the gate. SCR condution current for
the case of sinusoidal VAK and a pulse train at the SCR gate is shown in Figure 14.4.
VAK
Trigger
Pulse
Conduction Current
Figure 14.4: SCR conduction triggered by a pulse train.
While a conducting SCR presents very low dynamic resistance to the conduction current, there
is a voltage drop across the anode-cathode terminals. e voltage across the SCR in the ON state
is approximately given by the sum of a base-emitter drop, a collector-emitter drop and an ohmic
loss:
VAK VBE.sat/ C VCE.sat/ C RB IA :
Here RB is the bulk resistance associated with the SCR. e ON voltage drop has a minimum
value in the range of 1 V and may be as high as 2–3 V for high-current SCRs. e actual voltage
drop for any particular SCR is best determined from manufacturer’s specifications or experimental
evaluation.
In addition to the desired SCR activation with positive gate current, there are four false
SCR activation mechanisms which must be avoided:
• High rate of change of anode-cathode voltage, d VAK =dt .
• High anode-cathode voltage, VAK .
• High device junction temperature.
• Energy injection into device semiconductor junctions, principally in an optical fashion.
Reasonable design caution can avoid false SCR activation by the last three mechanisms: opaque
packaging avoids optical activation, a proper heat sink avoids high temperatures, and selection of
an SCR with a correct voltage-blocking rating avoids an avalanche breakdown. Fast variation of
the anode-cathode voltage, VAK , is the most likely significant false activation mechanism in most
applications.
A voltage applied across the anode-cathode terminals of an SCR induces a current through
the SCR proportional to the derivative of the applied voltage. is current is due to the junction
capacitances between the layers of semiconductor:²
d VAK
i DC
:
dt
If this capacitance-charging current exceeds the gate triggering current, the SCR is subject to false
triggering. Sensitivity to rate of change false activation can be reduced by a resistance shunting
the gate-cathode junction or, more commonly, controlled with a snubber circuit.
Snubber circuits limit the rate of change of the voltage across a SCR (or more generally any
thyristor). In their most simple form, a snubber circuit consists of a series connected resistor and
capacitor which shunt the SCR, as shown in Figure 14.5. e RC time constant of the snubber
circuit limits the rise time of the anode-cathode voltage and thereby reduces the possibility of
false activation. On occasion the resistor in the snubber circuit may be shunted or connected in
series with a diode. is diode is added to aid in suppression of transient voltages that may occur.
Input +
Source − Load
SCR Control
Figure 14.5: SCR application with snubber circuitry.
14.1.2 THE TRIAC

e triac is also a three-terminal semiconductor switch: its circuit symbol is shown in Figure 14.6.
e triac switch differs from the SCR in that it is capable of conduction currents in either direc-
²Junction capacitance is discussed in Section 10.4 (Book 3).
tion. e current-carrying terminals are simply identified at MT1 and MT2 (Main Terminals 1
and 2): the triggering terminal, G, remains identified as the gate. Positive conduction current is
identified as flowing from MT2 through the triac to MT1 : positive gate current flows into the
triac.
IT
MT2 MT1
Figure 14.6: Triac circuit symbol.
e triac is a five-layer semiconductor device as shown in Figure 14.7. In many ways it

can be thought of as two complementary SCRs (a pnpn device and an npnp device) connected
in parallel. ere are, however, properties of the triac that can not be described by such a simple
model. In particular, is the ability of the triac to be triggered into conduction in either direction by
either a positive or negative current into the gate. is bipolar triggering ability can be accounted
for by noting the region between the gate and MT1 is essentially two complementary diodes.
Either a positive or negative gate current will bring one of these diodes into conduction triggering
the same transistor action found in a SCR.
MT2
n
p
n
p
n n
G MT1
Figure 14.7: Typical triac semiconductor structure.
e four possible regions of triac operation are identified in Figure 14.8: the regions are
identified by the polarity of the main terminal voltage difference and the polarity of the gate
current. While it is possible to activate the triac in any region, the activation sensitivity to the
gate current varies with region.
Region I (positive gate current and positive main terminal voltage difference) is the most
sensitive of the four regions. Regions II and III are only slightly less sensitive to gate current turn
on. Region IV typically requires as much as four times the gate activation current as Region I: this
VMT2-MT1
+
II I
IG
− +
III IV
−
Figure 14.8: Triac regions of operation.
region of operation is avoided whenever possible. In many AC applications, the polarity of the
gate current is automatically reversed as the polarity of the input voltage reverses so that operation
is always in regions I and III.
e triac is subject to the same false activation mechanisms as the SCR. Many of the same
precautions must be taken to ensure that the only activation mechanism is through the gate cur-
rent. One additional precaution that must be taken involves the necessity of bidirectional snubber
circuitry. While simple RC snubber circuitry is effective for both conduction current polarities
(assuming proper choice of non-polarized capacitor), more complex SCR snubber circuitry may
not be bidirectional and therefore inappropriate for triac use.
14.2 VOLTAGE REGULATOR DESIGN

e performance of electronic circuitry often depends on the application of stable DC power
to the circuitry. Zener diode regulators, as discussed in Chapter 2 (Book 1), are one possible
method for providing relatively stable DC power. However, Zener diode regulators have sig-
nificant drawbacks: the most significant of which is the dependence the output voltage on load
current and temperature. A better alternative to the use of a zener diode in efficiently ensuring
stable power is the use of an integrated circuit voltage regulator. Such devices are highly effec-
tive, widely available, and relatively inexpensive. An integrated circuit voltage regulator provides
specific, stable DC power over a wide range of load current and input voltage conditions and has
relatively small variation in output with temperature.
An integrated circuit voltage regulator consists of three basic elements as shown in Fig-
ure 14.9:
• A voltage reference element that provides a known stable voltage level, VREF , that is essen-
tially independent of temperature and the input voltage.
• An error amplifier that compares the output voltage or some fraction of the output voltage
to the reference voltage, VREF .
14.2. VOLTAGE REGULATOR DESIGN 1019
• A power control element that converts, as indicated by the error amplifier, the input voltage
to the desired output voltage over varying load conditions.
Each of these elements can be realized with several circuit topologies. e following discussion
provides a sampling of the element topologies common in typical voltage regulators. While all
examples shown here assume that the voltage to be regulated is positive, regulation of both voltage
polarities is common and accomplished with the same general circuit topology. In addition, track-
ing regulators provide a symmetric pair of regulated voltages (i.e., ˙ 10 V) for applications that
need matched, regulated power. One such application is the dual power bus needed for OpAmps.
Input Control Regulated

◦ • • ◦
Voltage Element Voltage
Error
Amp
VREF
Voltage
Reference
Figure 14.9: Typical voltage regulator block diagram.
14.2.1 THE VOLTAGE REFERENCE

e design goal of the voltage reference element is to provide a known, stable reference voltage,
VREF . ere are three basic circuit topologies that provide a reference voltage within common
voltage regulators. Two of these circuits are based on the Zener diode reverse breakdown voltage,
Vz , and the third is based on the base-emitter junction voltage of a BJT. Simplest among the three
circuits is a basic Zener diode reference, as shown in Figure 14.10.
In this circuit the output voltage, VREF , is dependent on the diode zener breakdown voltage,
Vz , the diode zener resistance, rz , the input voltage, Vin , and the resistor value, R:

R rz
VREF D Vz C Vin : (14.7)
rz C R rz C R
e basic zener diode reference can be satisfactory in applications where the input voltage, Vin ,
is relatively stable. However, the susceptibility of this circuit to variation in input voltage and
load-current induced temperature variation, may make it a poor choice in many applications.³
³e zener voltage for integrated circuit zener diodes varies with temperature by approximately C2:2 mV=ı C.
◦
VCC
• ◦ VREF
Figure 14.10: Basic Zener diode voltage reference.
An improvement in the basic zener diode voltage reference can be obtained by making
the diode current independent of input voltage, Vin . One typical circuit topology that reduces
diode current variation by driving the zener diode with a constant current source is shown in
Figure 14.11.
V
◦ in
•
• Q2
• ◦ VREF
Q1 •
RSC
Figure 14.11: Constant-current Zener diode voltage reference.
Here the current in the zener diode is the sum of the base current in Q1 and the current through
resistor RSC :
Iz D IB1 C IRSC : (14.8)
In most applications the base current can be ignored:
VBE1
Iz IRSC D : (14.9)
RSC
is gives a stable reference voltage, VREF :

rz
VREF D Vz C Iz rz C VBE1 Vz C VBE1 1 C : (14.10)
RSC
Temperature variation of the reference voltage can be minimized by balancing the positive
temperature variation of the zener voltage, Vz , with the negative temperature variation of the
base-emitter voltage, VBE1 . e major disadvantage of the constant-current zener diode reference
voltage is the need for the input voltage, Vin , to be relatively large: it must remain, depending
on the exact circuit design, at least 1.5 volts more than the zener voltage.⁴ is restriction on the
input voltage limits the minimum voltage application of such a regulator.
A third common reference voltage circuit, the bandgap voltage reference, is shown in Fig-
ure 14.12. is design allows for a minimum input-output voltage difference as small as 0.6 volts:
the input and output vary only by the voltage across the input resistor, R.
V
◦ in
• • ◦ VREF
R1 I3 R3
• • Q3
Q1 • Q2
R2
Figure 14.12: Bandgap voltage reference.
e output of the bandgap voltage reference is based on the highly predictable base-emitter
voltage of a BJT in the forward-active region. Here the output reference voltage, VREF , is given
by:
VREF D VBE3 C I3 R3 : (14.11)
e current, I3 , is essentially the output of a Widlar current source⁵ formed by transistors Q1 and
Q2 and resistors, R1 and R2 . e current source has an output current, IC 2 , given by the solution
⁴Manufacturers specify the minimum voltage difference between input and output voltage: for this design topology, it typically
lies in the two to three volt range.
⁵Widlar current sources are discussed in Section 6.4.5 (Book 2).
to the transcendental equation

ˇF IC1
IC 2 R 2 D Vt ln : (14.12)
ˇF C 1 IC 2
If the base current of Q3 is assumed to be small compared to the collector current of Q2 , the
output voltage can be derived from Equations (14.11) and (14.12):

R3 IC1
VREF Vt ln C VBE3 : (14.13)
R2 IC 2
It can be seen from Equation (14.13) that the bandgap reference circuit has an output, VREF ,
that is independent of the input voltage, Vin . An additional benefit of this circuit topology is its
relative insensitivity to temperature variation. If the circuit is built in IC form, then all circuit
elements are essentially at the same temperature. e ratio of the collector currents IC1 and IC 2
remains basically constant over temperature change and the variation in the reference voltage with
temperature is given by:

VREF R3 IC1 Vt VBE3
ln C : (14.14)
T R2 IC 2 T T
In Chapter 2 (Book 1), the voltage equivalent temperature, V t , was defined as:
kT T
Vt D ; (14.15)
q 11600
V t consequently has a positive variation with temperature. In Chapter 3 (Book 1), it was shown
that the variation in VBE with temperature is negative. us, it is possible have essentially no
temperature variation in VREF if the two temperature dependent terms in Equation (14.14) cancel.
e necessary conditions for cancellation are:

R3 IC1 11600 VBE3
ln D : (14.16)
R2 IC 2 T
A judicious choice of the resistors R1 ; R2 and R3 allows the designer to produce a wide variety
of reference voltages that are relatively insensitive to temperature and input voltage variation. A
typical reference voltage value used in many regulators is 2.5 V.
All of the described voltage reference circuits find uses other than in voltage regulators:
they can be used whenever an independent voltage reference is necessary. A precision reference
voltage is usually achieved with either the bandgap or constant current zener reference circuits.
ese precision voltage reference circuits are used in wide variety of electronic applications. Most
common among these is as reference for precision analog to digital conversion. A few of the
common applications for voltage reference circuits are:
• Analog to digital conversion, A/D
• Digital to analog conversion, D/A
• Digital multimeter applications
• Voltage to frequency conversion, VCO
• Frequency to voltage conversion, FM detection
14.2.2 THE ERROR AMPLIFIER

e error amplifier in IC voltage regulators is basically a differential amplifier that compares the
output voltage (or a fraction of the output voltage) to the reference voltage. ey may take as
simple a form as an emitter-coupled or source-coupled pair, but are more often similar to an
OpAmp circuit.⁶ ese differential amplifiers must have a high common-mode rejection ratio
(CMRR), low offset currents and voltages, and a high power supply rejection ratio (PSRR) to be
effective in voltage regulation applications.
14.2.3 LINEAR VOLTAGE REGULATORS

e inputs to the power control element of a voltage regulator are the supply voltage and the
control signal from the error amplifier. e output of this element must be a constant, specific
voltage over a wide range of load currents and impedances. While the voltage reference and error
amplifier elements can be virtually identical for a wide range of voltage regulators, the power
control element varies widely depending on the type of desired regulation. e three basic types
of power control elements are:
• Series
• Shunt
• Switching
Voltage regulators are often classified by the type of control unit employed. A voltage regulator
with a series or shunt power control element is classified as a linear voltage regulator : a regulator
with a switching power control element is a switching regulator. Linear regulators have a distinct
noise advantage over switching regulators. Due to energy conversion efficiency considerations,
linear regulators are typically found in low power electronic applications: switching regulators
find greater use in high power applications where they act as regulated power supplies.
⁶Differential amplifiers are discussed in several sections of this book. See Chapters 2 (Book 1) and 6 (Book 2) for basic discus-
sions.
Series Regulators
e series regulator is best suited for medium load current applications where the input-output
voltage difference is not large. e commonly-used, three-terminal IC voltage regulator, found
in many electronic designs, is usually of this design. Safety features such as input overvoltage and
output short-circuit protection can also be provided in series regulators.
For a series regulator, the error amplifier regulates the output voltage, Vo , through an active
series element, usually a transistor, as shown in Figure 14.13. If the output voltage falls below
R2 C R1
Vo VREF ; (14.17)
R2
the error amplifier will supply a positive voltage signal to the BJT. e transistor base-emitter
junction becomes more forward biased and increases the current to the load. e output voltage is
thereby increased until an appropriate balance is achieved. Large input-output voltage differences
imply that the active control element must dissipate significant power. e internal losses lead to a
typical working efficiency for a series regulator of 40–50%: high input-output voltage differential
can reduce this figure further. e potentially large internal power loss is the greatest disadvantage
of a series regulator.
Vin◦ • • ◦V
o
R1
− •
Error
Amp
+
VREF
Voltage R2
Reference
Figure 14.13: Basic series regulator topology.
Shunt Regulators
While the shunt regulator is usually the most inefficient of all regulator topologies, it can be a
good choice in some applications. It is relatively insensitive to input voltage variation, protects
the source from load current transients, and is inherently rugged against an accidental load short-
circuit. It is the simplest of all regulators: for example, the zener diode regulator, as described in
Chapter 2 (Book 1), is a passive form of shunt regulator. e basic circuit topology of an active
shunt regulator is shown in Figure 14.14.
RS
Vin◦ • • • ◦V
o
VREF
Voltage –
Reference Error
Amp R1
+
•
R2
Figure 14.14: Basic shunt regulator topology.
Here, the active series pass element of the series regulator has been replaced by a resistor,
RS , and the changes in load current are neutralized by shunting excess current through an active
element (usually a transistor) to ground. When the output voltage falls below
R2 C R1
Vo VREF ; (14.18)
R2
the error amplifier reduces voltage to the base of the BJT thereby reducing the shunt current.
Since the current through the series pass element, RS , must remain constant, more current is
available for the load and Vo is increased until an appropriate balance is achieved.
14.2.4 SWITCHING VOLTAGE REGULATORS

e switching regulator is most often used in relatively high-power applications where power
conversion efficiency is of high concern. Switching regulators have a typical operating efficiency of
60–90%. In addition, they provide good regulation over a wide range of input voltage and maintain
high efficiency over a wide range of load current. It is also possible to provide regulated voltages
larger than the input voltage. A switching regulator has a significant size and weight advantage
over other regulators in high-power applications: typically a switching regulator is smaller by a
factor of between four and eight.
e basic topology of a switching regulator, as shown in Figure 14.15, is similar to a linear
regulator except the active element is modulated in an ON/OFF mode of operation by a switch
control unit. Typically, control unit uses the output of the error amplifier to pulse-width modulate
the output of a constant-frequency oscillator. e pulse-width modulated square wave varies the
ON/OFF duty cycle of the active element similarly varying the average value of the passed voltage.
e addition of a rectifying low-pass filter after the series active element smoothes the output
voltage to the desired value. Another realization of the switch control unit consists of a voltage-
controlled oscillator with non-varying ON time. A major drawback of this realization is the added
complexity of the rectifying filter due to variable frequency inputs. Consequently, the voltage-
controlled oscillator realization is not typically found in modern switching voltage regulators.
Rectifier
Vin◦ • • ◦V
& Filter o
R1
Switch Control
− •
Pulse Width Error
Modulator Amp
+
Oscillator
R2
Voltage
Reference VREF
Figure 14.15: Typical switching regulator topology.
e added complexity of a switching regulator in the form of complex switch control cir-
cuitry and the need for a high-frequency active switching element increase the cost of the reg-
ulator. As a result, switching regulators can only compete economically with other regulators in
high-power applications (greater than 20 W). Switching regulators typically have somewhat
higher output ripple and can be more susceptible to load current transients than linear regula-
tors. In addition, high rate (20–500 kHz), square-wave switching generates significant electro-
magnetic interference (EMI) and radio-frequency interference (RFI). It is possible successfully
diminish both EMI and RFI with proper filtering.
e rectifying filtering section of a switching voltage regulator can take several different
topologies. Most common among these topologies are:
• Buck
• Boost
• Buck-Boost
e basic topology of each rectifying filter section is shown in Figure 14.16. e majority of other
rectifying filter are direct derivatives of these three types.
e output voltage, Vo , of the buck filter configuration (Figure 14.16a) is always less than
the input voltage, Vin . Here, a switch is placed in series between the input voltage and the input to
⁷e active element switch is shown here as a BJT. In many switching regulator designs, is a much more complex element.
Many designs use a class A amplifier with a transformer output as the high-frequency switch.
Vin◦• • • ◦•Vo Vin◦ • • ◦-V

o
Switch Switch
Control Control •
•
(a) (b)
Vin◦ • • ◦V
o
Switch
Control
(c)
Figure 14.16: Switching regulator filtering configurations.⁷(a) Buck (step down); (b) Buck-boost fil-
tering (step up or down) (c) Boost filtering (step up).
an LC low-pass filter. When the switch is conducting, current flows through the inductor to the
load. When the switch opens, the magnetic field within the inductor maintains the current flow
to the load, pulling current through the diode from ground. In a buck circuit, the output voltage
is proportional to the product of the input voltage and the switch duty cycle:
Vo Vin (duty cycle): (14.19)
Peak switch current in the buck circuit is proportional to the load current.
e boost filter configuration (Figure 14.16c) has the unique property of providing an output
voltage that is always larger than the input voltage. In this circuit, the switch is placed within the
LC filter so that it can shunt current to ground. With the switch in its conducting state, the
inductor current increases. When the switch opens, the output voltage, Vo , is the sum of the
input voltage and the voltage across the inductor (a positive voltage due to decreasing inductor
current). Boost regulators deliver a fixed amount of power to the load:
1 2
PL D LI fo ; (14.20)
2
where I is the peak inductor current, and fo is the switch operating frequency. In order to deter-
mine the output voltage the load resistance, RL , must be known:
r
p LRL fo
Vo D Po RL D I : (14.21)
2
Of course, the peak inductor current, I , is proportional to the duty cycle of the switch operation.
Boost circuits are particularly useful in charging capacitive circuits (as in a capacitive-discharge
automotive ignition system) and make good battery chargers.
e buck-boost rectifying filter (Figure 14.16b) provides the possibility of output voltages
that are either higher or lower than the input voltage. e circuit operates in much the same
fashion as the boost circuit with the exception that the output voltage is simply the voltage across
the inductor. e buck-boost circuit also delivers constant power to the load, independent of the
load resistance: Hence, Equations (14.20) and (14.21) are valid. e buck-boost has the distinct
feature of providing a negative voltage output. is change of polarity is often an advantage,
sometimes a drawback. Isolation of the input from the output through transformer coupling
avoids any problems.
For all these configurations, transient changes in the load conditions may cause problems. If
the load suddenly becomes a very high impedance or suddenly becomes disconnected, the energy
stored in the inductor has no path for dissipation. In a worst case scenario, arcing across the load
may occur. Switching power regulators are currently in a constant state of change due to major
innovations in component design. It appears that major improvements in design are near.
14.3 VOLTAGE REGULATOR APPLICATIONS

e three-terminal, linear, IC voltage regulator is the most common voltage regulator in electronic
applications with power requirements less that 20 W and voltages less than 50 V. Its small
size, high quality, and cost effective properties make it an extremely useful device. In its most
simple form, the three-terminal regulator requires a minimum number of external components for
proper operation: typical connection of a positive, fixed-output regulator is shown in Figure 14.17.
e only external components necessary for this particular regulator are two small-value, high-
frequency capacitors to improve stability and transient response.
3 Terminal
Vin◦ • Linear • ◦V
o
Regulator
Figure 14.17: Typical fixed IC voltage regulator connection.
Whenever using an IC voltage regulator, the circuit designer is faced with several design
choices based on the properties and limitations of these regulators. Linear regulators are cate-
gorized by their regulated output voltage. e most basic categories are based on the following
properties:
• Output Voltage Polarity
14.3. VOLTAGE REGULATOR APPLICATIONS 1029
• Fixed or Variable Output Voltage
• Dual-tracking Output Voltages
e maximum output current is one additional constraint that must be considered. IC voltage
regulators typically come with maximum current ranging from 100 mA to 3 A. It is possible to
extend this maximum output current with the addition of external circuit pass elements (Sec-
tion 14.3.1).
e polarity of the input and output voltage usually determines the use of a positive or
negative regulator: positive regulators typically are used to regulate positive voltages—negative
regulators typically regulate negative voltages. is is particularly true in systems where the input
and output share a common ground. However, in systems where the ground reference can be
floating at either the input or the output, the positive and negative regulators may be interchanged
(Figure 14.18). In this special case a positive regulator can be used to regulate negative voltages
and a negative regulator can be used to regulate positive voltages.
Positive •◦ ◦
◦
Regulator
◦
+ +
+ Vo + Vo
Vin – Vin –
Negative –◦
◦• –◦ •◦
Regulator
(a) (b)
Figure 14.18: Voltage regulation alternatives. (a) Positive output using positive regulator; (b) Positive
output using negative regulator.
Fixed output voltage regulators are available in a variety of output voltage values and current
ratings. ey provide an inexpensive, simple means of regulating output voltage and have several
advantages:
• ease of use
• few external components
• reliable performance
• internal thermal and short-circuit protection
e main disadvantage of a fixed output voltage regulator lies in the inability to precisely adjust its
output. e variation in output voltage may be as large as ˙ 5% for any specified value. A similar
problem exists due to the limited selection of output voltage values that are available.
Adjustable output voltage regulators are best suited for applications requiring high-precision
voltage regulation and/or regulation at a non-standard voltage level. In addition, the regulated
voltage may be sensed at a location remote from the output of the regulator. is feature allows for
compensation due to losses in a distributed load or external pass components. Additional features
often found on adjustable regulators include: adjustable short-circuit current limiting, access to
the reference voltage, VREF , and overload protection. Adjustable regulators typically require a few
more external components than fixed regulators (Figure 14.19). e capacitors improve stability
and transient response.
3 Terminal
Vin◦ • Adjustable • • ◦V
o
Regulator
• •
• •
Figure 14.19: Typical adjustable voltage regulator connection.
It is possible to accomplish the performance of an adjustable voltage regulator using a fixed-

output regulator and an OpAmp. One circuit topology that has an adjustable output is shown in
Figure 14.20. In this circuit the variable output is limited to values larger than the specified,
3 Terminal
Vin◦ • Fixed • • ◦V
o
Regulator
−
• • •
+
• • •
Figure 14.20: Variable regulated output using a fixed output voltage regulator.
regulated output of the fixed regulator. While designs of this type are effective, the additional
components required often makes them economically impractical.
Many systems require balanced, dual-polarity power: an OpAmp that requires ˙VCC about
a common ground is such a system. An obvious solution to dual-polarity applications is two
independent regulators, one positive and one negative, paired together. Two problems arise with
such a solution: power-ON latch-up and undervoltage output imbalance. Latch-up is due to the
intolerance of each individual regulator to reverse voltages applied at its output. In dual-polarity
systems with a single load across both outputs, reverse voltages may appear during the power-
ON operation and cause latch-up of the output of one of the regulators. is condition can be
avoided by placing diodes, from input to output and output to ground of each regulator, to avoid
significant reverse voltage application. In many systems that require balanced power of opposite
polarity, the application of unbalanced power will offset the output. If, for a variety of reasons, the
imbalance is not constant, there will be a time-varying offset in the signal output: time-varying
outputs are usually interpreted as information signals.
Dual Tracking Regulators provide a solution to both problems. Latch-up is internally controlled
and no additional external components are necessary. In order to avoid an imbalance in output
voltages, the control system within a dual tracking regulator monitors both the positive and neg-
ative power outputs. If either output falls out of regulation, the tracking regulator will respond by
varying the other output to match: a decrease in the magnitude of the positive output will result
in an equal decrease in the magnitude of the negative output. A typical dual tracking connection
is shown in Figure 14.21. As is the case with most linear regulators, output capacitors improve
ripple and transient performance: input capacitors may be necessary if the source is particularly
noisy or if the regulator is placed too far from the unregulated power supply.
+Vin◦ • • ◦+V
o
Dual Tracking
• • ◦
Regulator
−Vin◦ • • ◦−V
o
Figure 14.21: Typical dual tracking regulator connection.
Limitations as to the input voltage range and output voltage and current ranges over which
regulation will occur apply to all voltage regulators. e safe operating area (SOA) defines the
limits of these ranges. Exceeding the limits can result in catastrophic failure, temporary device
shutdown, or failure to properly regulate the output. e SOA is defined by manufacturer’s spec-
ifications relating to the input voltage, the output current, maximum power dissipation, and, in
the case of variable voltage regulators, the output voltage. ese specifications are described as:
Vin.max/ e absolute maximum input voltage with respect to the
regulator ground terminal.
.Vin Vo /min e minimum input-output voltage difference at which regulation
can be maintained. Also called the dropout voltage.
.Vin Vo /max e maximum input-output voltage difference.
IL.max/ e maximum current deliverable to the load from the regulator.
PD.max/ e maximum power that can be dissipated by the regulator.
Vo.min/ For adjustable regulators, the minimum output voltage that can
be regulated.
Vo.max/ For adjustable regulators, the maximum output voltage that can
be regulated.
Of these specifications, Vin.max/ ; IL.max/ , and PD.max/ can result in catastrophic failure if proper
protection is not provided. Often this protection is within the regulator itself: in some cases it
must be provided with external circuitry. e other specifications are functional limits that, if
exceeded, imply a failure in the regulation ability of the device.
14.3.1 EXTENDING THE CAPABILITIES OF A SIMPLE VOLTAGE

REGULATOR
It is often desirable to extend the SOA of a regulator with external components so as to exceed
one of the specified limits. Extending the maximum values of output current, input voltage, and
output voltage is necessary in many voltage regulator applications. While many, varied uses of
simple IC voltage regulators exist, a constant current source provides a good example of one
possibility.
Increasing Maximum Output Current

e effective output current of a simple voltage regulator can be increased through the use of an
external bypass element as shown in Figure 14.22.
In this realization the bypass element is a power PNP BJT: it must be chosen with the
capability to provide ample output current and to dissipate enough power across its collector-
emitter terminals. e resistor, R, must be chosen so that the internal bias current of the voltage
regulator, IBias , does not turn on the external bypass BJT. is condition is met if
VBE.on/
R :
IBias
Special care must be taken in this realization to protect against a possible output short circuit.
Under this condition, the bypass element often must dissipate large quantities of power and may
fail.
Vin◦ •
R
3 Terminal
• Linear • ◦ Vo
Regulator
•
Figure 14.22: A series pass element to boost output current.
Increasing Input and/or Output Voltage Levels

It is often necessary to provide a regulated voltage larger than an available linear regulator. One
possible circuit topology that will increase the regulated voltage for a particular regulator is shown
in Figure 14.23. is circuit uses a zener diode in between the ground terminal of the regulator
and the actual circuit ground. e new regulated output voltage is sum of the regulator output
voltage and the series zener voltage:
Vo.new/ D Vo.reg/ C Vz1 :
Vin◦ • QP • 3 Terminal • • ◦ Vo
Linear
Regulator
•
R
ZP DP
• •
Overvoltage Protection
Z1
•
Figure 14.23: High output voltage output circuit topology.
Also shown in Figure 14.23 is an overvoltage protection circuit (shaded area and the diode
DP ). Under normal operation the input BJT, QP , is in saturation and the circuit operates as if
the protection circuit was not present. However, if the input voltage exceeds the sum of the two
zener voltages,
Vin > Vz1 C VzP ;
the input BJT, QP , will enter the forward-active region begin to dissipate power. e voltage drop
across the BJT collector-emitter terminals will protect the input of the regulator from overvoltage,
and excess current will be shunted through Rp ; Zp and Z1 . e protection diode, Dp , protects
the regulator against an output short circuit. While this protection circuit is shown in conjunction
with the zener diode realization of extending the output voltage, it can be used alone. With the
absence of zener diode, Z1 , the diode, DP , is also excluded. All elements in this overvoltage
protection circuit will dissipate large quantities of power when activated and must be rated for
that occurrence.
Using a Voltage Regulator to Provide a Constant Current

Another common regulated source necessary in many electronic applications is a constant current
source. ree terminal positive voltage regulators can be effectively used to provide this source as
shown in Figure 14.24.
Vin◦ • 3 Terminal
Voltage +
Regulator Vreg
R
−
IIB
•
Io Load
Figure 14.24: Adjustable constant current source regulator configuration.
In this configuration the output current, Io , can be adjusted to any value from the minimum
regulator bias current ( 8 mA) to the maximum current deliverable be the regulator, IL.max/ . e
output current is the sum of current through the variable resistor and the bias current through the
ground terminal of the regulator:
Vreg
Io D C IIB :
R
e input voltage for this configuration must always be greater than the sum of the minimum
input-output voltage for the regulator, the regulator voltage, and the voltage at the load:
Vin .Vin Vo /min C Vreg C Vo :
e choice of regulator is a balancing of conflicting requirements. Small Vreg is desirable to reduce

power dissipation and allow for large variation in Vo . Large Vreg gives a more precise setting of
the load current through the variable resistor. Five volt fixed regulators often provide a good
compromise.
14.4. TRANSIENT SUPPRESSION AND OVERVOLTAGE PROTECTION 1035
14.4 TRANSIENT SUPPRESSION AND OVERVOLTAGE
PROTECTION
A common problem in most electronic applications comes in the form of an inappropriately large
input voltage. Protection must be provided so that erroneous voltage application connection at the
input or transient overvoltages do not damage the circuitry. Transient high voltages are usually the
result of the release of stored electric energy in the form of a current or voltage pulse. In order to
ensure proper circuit protection against improper operation or actual damage, the energy within
the transient must be dissipated within an added suppressor. Transients may result from sources
within a circuit or have external sources. One typical internal source is inductive switching (as in
motor control circuitry). External sources of transients include line-voltage variations and electro-
magnetic interference (EMI). One particularly unfriendly environment (in terms of transients)
for electronic applications occurs in automotive applications.
Common Transient Suppressors and/or Overvoltage Protection Circuits limit the peak AC
or DC voltage and include:
• Carbon Block Spark Gap Suppressors
• Zener Diodes
• Varistors
• Selenium Rectifiers
• Overvoltage “Crowbar” Circuits
e first four items on this list are well suited as protection against short duration high-voltage
transients. In addition, zener diodes and Selenium rectifiers have good capability to protect against
longer duration overvoltages so long as their average power ratings are not exceeded. Overvoltage
crowbar circuits are best used as protection against long duration overvoltages or misapplication
of electrical power. Each of these protection circuits is connected as a shunt to the circuit to be
protected.
A carbon block spark gap suppressor is an effective means of keeping transient voltages below
a level of 300–1000 volts. It is commonly found in telecommunication and power distribution sys-
tem. e suppressor is simply two carbon electrodes, one connected through a resistor to ground,
separated by an air gap of approximately 0.1 mm. When a high voltage transient is encountered,
the energy in the transient is passed to ground through the arc in the air gap between the elec-
trodes. e main drawbacks to carbon block spark gap suppresser use is its relatively short lifetime
and the inherent variation in arcing voltage.
Zener diodes, discussed in Chapter 2 (Book 1), exhibit excellent voltage limiting properties.
ey are perhaps the most often used transient suppressor. Often a “back-to-back” connection,
as shown in Figure 14.25, is used to suppress transient overvoltages that are bipolar in nature:
many zener transient voltage suppressors are available commercially packaged as a back-to-back
pair. While typical zener diodes are designed to operate at less than their maximum power rating,
zener transient suppressors are designed to effectively limit large, short-duration power pulses.
e design change is accomplished by increasing junction area so as to withstand the high energy
surge of a transient. When zener diodes fail, they typically fail to a short circuit. is feature,
coupled with the shunt connection of zener protection circuits, ensures that the circuit is protected
even though the protection circuit has failed.
Or
Figure 14.25: Zener diodes connected for bipolar overvoltage protection.
A varistor is a non-linear resistor that has electrical properties similar to a back-to-back

zener diode connection. A varistor can therefore provide an alternative to zener diodes in many
applications. e device is constructed of metal (often zinc) oxides sintered into a polycrystalline
structure or silicon carbide sintered into a suitable ceramic binder forming a hard ceramic-like ma-
terial. As a result of the sintering process, highly resistive intergranular boundaries are distributed
throughout the volume of the device. e boundaries are the source of the voltage-dependent
non-linear behavior of the varistor. e distributed nature of the boundaries make the varistor
well suited for high power transient suppression. Compared to zener diodes, varistors are inex-
pensive. Varistors also share the attractive fail-to-short characteristic with zener diodes.
Figure 14.26: Varistor circuit symbol.
e non-linear behavior of a varistor can be described by its volt-ampere transfer relationship:
C
V D jI j .2 a/
; (14.22)
I
where the passive sign convention relates the voltage and current polarities⁸ and the two varistor
property-dependent constants are given by:
C D the voltage across the varistor at I D 1 A

a D a factor describing the non-linearity of the V-I curve. Typically,
0:5 a 0:83 W as a increases, the sharpness of the curve increases.
In Figure 14.27, the volt-ampere transfer relationship of a typical varistor .a D 0:7/ is compared
to that of a back-to-back zener diode connection. e difference in the sharpness of the cutoff is
evident.
Varistor
O I
Back-to-Back
Zener Diodes
Figure 14.27: Volt-ampere relationship for a varistor compared to a back-to-back Zener diode pair.
e major drawbacks to varistors can be significant. Varistors do not clamp voltages as

effectively as zener diodes and may, therefore, be unsuitable in many applications where an ab-
solute maximum voltage limit must be maintained. Also, they can only dissipate relatively small
amounts of average power and are degrade significantly when stressed near their maximum rat-
ings. ey can, however, offer a significant cost advantage over zener diodes. Varistors are best
used in applications for protection against rarely occurring transients.
Selenium rectifiers, in the reverse breakdown mode of operation, can clamp voltages in much
the same manner as zener diodes. An attractive feature of many Selenium rectifiers is the ability to
survive a limited number of surges greater than their maximum typical rating. Unfortunately they
do not have as sharp a “knee” in the V-I curve as the zener diode (though sharper than the varistor)
⁸e volt-ampere transfer relationship for a varistor is symmetric. e literature typically provides a relationship that assumes
current flow is always positive: V D CI .1 a/ .
and the ON resistance is somewhat greater. erefore, the use of Selenium rectifiers as overvoltage
protection devices is diminishing as the demands for protection become more stringent.
Overvoltage “Crowbar” Circuits protect loads with a switchable shunt element. is element
is often realized with SCR that is activated if overvoltage conditions exist. A simple form of
overvoltage crowbar circuit, utilizing a zener diode as the overvoltage sensing element, is shown in
Figure 14.28. In this circuit, an input voltage, Vin , that exceeds the SCR gate activation voltage plus
the zener breakdown voltage, will force current into the SCR gate activating the SCR. e SCR
will then shunt current away from the load protecting it from damage. One drawback of SCR
crowbar circuits is that they will not deactivate unless the source current goes to zero. Deactivation
of the SCR is usually accomplished by a series circuit breaker or fuse incorporated in series with
the source, Vin .
Vin◦ • • ◦
L
O
• •
A
D
◦ • • • ◦
Figure 14.28: A simple SCR crowbar circuit.
While a zener diode—SCR crowbar circuit is relatively inexpensive and easy to use, there are
several drawbacks to its use. ese drawbacks are mainly due to the properties of zener diodes. In
particular, the zener voltage values commercially available are limited, often have insufficient tol-
erances, and may not activate sharply enough (the knee of the diode curve may be too rounded).
ese drawbacks are particularly significant when the voltage protection limit must be fairly small:
many digital circuits require overvoltage protection at power voltages less than 10 V. A good so-
lution to these problems involves the use of an integrated circuit sensing circuit.
An overvoltage crowbar circuit using an IC sensing circuit is shown in Figure 14.29: the
shaded portion of the figure highlights the sensing circuit. In this IC package are contained two
OpAmps, a voltage reference circuit, a zener diode, a current source, and three BJTs.
e operation of the circuit is reliable and accurate.
In the normal, deactivated state, the input voltage to the protection circuit, Vin , is appro-
priately small:
R2 C R1
Vin < VREF :
R2
Vin◦ • • •
R1
◦
• • +
• −
OA2 • Q3
OA1 Q1 L
− O
+ Q2 •
A
R2 D
Voltage
Reference +V •
REF
−
• • • ◦
Figure 14.29: Crowbar protection using overvoltage sensing circuit.
is deactivated state assures that the first OpAmp, OA1 , provides a high voltage to the
base of Q1 , putting it into the saturation region. OA2 then provides a low voltage to Q2 and Q3
which are in cutoff. No current is supplied to the gate of the SCR which is, therefore, not activated.
Should Vin increase so that the input voltage fails to meet the constraints of Equation (14.22),
OA1 will turn off Q1 . e current source will then pass its current through the zener diode raising
the positive terminal of OA2 higher than VREF . e BJT combination Q2 and Q3 will turn on
and activate the SCR, shunting all the current away from the load.
Using an IC overvoltage sensing circuit to activate the SCR allows the circuit designer to
provide a temperature independent voltage reference, and adjust the crowbar voltage using the two
resistors, R1 and R2 . e sensing circuits are readily available from a wide range of manufacturers
and are usually found within the “power supply supervisory” listings. It is also common to package
a circuit equivalent to that shown in Figure 14.29 in a single IC package. ese crowbars are
available in a range of voltages and short-circuit current ratings.
While it is impossible to demonstrate the operation of every protection circuit, the protec-
tion methods discussed here provide a good sampling of typical techniques. Zener diodes provide
appropriate transient protection in most small-scale electronic applications. Higher power ap-
plications that need protection from longer duration overvoltages usually use crowbar devices.
Crowbar circuits are also often activated by temperature sensors (often a thermistor) to protect
against damage to a circuit due to overheating. IC overvoltage sensors occasionally are used to
deactivate a semiconductor switch in series with the load rather than the shunt SCR as described
here.
e study of power electronics should, more properly, be covered in an entire book rather than
in one short chapter. Here, the discussion has been restricted to a few common devices that an
electronic circuit designer will find necessary in order have clean, constant DC power as an input
to circuits with other major electronic functions. yristors were shown to be a useful family of
triggered switches dominated by the SCR and Triac. Both linear and switched voltage regulators
are commonly used: linear regulators dominate low-power applications, while switched regulators
find greater use in high-power applications. Several forms of active and passive protection circuits
were also discussed.

In the design of Analog-to-Digital (A/D) and Digital-to-Analog (D/A) converters. there is a
need for a precision voltage reference that is relatively invariant with input voltage and temperature
variation.
Design a 2.5 V precision voltage reference that will operate for input voltages ranging from
4 to 10 V.
Solution:
e three voltage reference topologies available are:
• Zener diode
• Constant-current Zener diode
• Bandgap
e basic Zener diode reference is somewhat dependent on input voltage and must, therefore,
be discarded. e constant-current Zener diode reference is a possibility, but the relatively small
possible difference between input an output voltage may pose a problem. erefore, the bandgap
reference seems the best choice and will be form the basis of the chosen design.
As described in Section 14.2, the bandgap reference output voltage is given by:

R3 IC1
VREF Vt ln C VBE3 :
R2 IC 2
Assuming that VBE3 D V D 0:7 V, this expression reduces to:

R3 IC1
2:5 D 0:026 ln C 0:7;
R2 IC 2
or

R3 IC1
ln D 69:231:
R2 IC 2
◦Vin
• • ◦ VREF
R1 I3 R3
• • Q3
Q1 • Q2
R2
A few arbitrary design choices must be made to continue. Choose

2:5 0:7
IC 2 D 0:5 mA ) R3 D D3:6 k:
IC 2
Also choose
IC1 D 1:0 mA ) R2 D 36:0 ;
and
2:5 0:7
) R1 D D 1:8 k:
IC1
e resistor, R, must be small enough so that at least 1.5 mA (IC1 C IC 2 ) will flow at the
smallest input voltage. e upper limit on input voltage merely puts a restriction on the power
dissipation. erefore,
4 V 2:5 V
R< D 1 k ) Choose R D 910 :
1:5 mA
e maximum power dissipated in the resistor R is:
.10 2:5/2
PR.max/ D D 61:8 mW:
910
A 1=4 W resistor will suffice.
Any high-ˇF BJTs can be used for this design. e ideal temperature variation for the BJTs
is given by the relationship of Equation (14.16). is expression reduces to:

VBE3 11600 R3 IC1
D ln D 5:98 mV=ı K:
T R2 IC 2
is is a rather large value: more realistic BJTs will provide a voltage with small, but non-zero
temperature variation.
14.6 PROBLEMS
14.1. Model the action of an SCR using the equivalent circuit of Figure 14.3b and SPICE.
Use BJTs with ˇF D 100. Apply a voltage, Vs , of 18 Vp p at 60 Hz in series with 100
across the anode-cathode terminals. Inject into the gate of the SCR model, 10 A current
pulses of 50 s duration from a source with an output resistance of 100 k. Verify the
operation of the SCR model as shown in Figure 14.3.
14.2. A macromodel for the 2N1599 SCR is available in the SPICE model libraries. Its ter-
minals are ordered in the model call as {anode gate cathode}. Repeat the functional test
of Problem 14.1 (the minimum gate trigger current is 2 mA: increase the magnitude of
the current pulses so that the SCR will properly trigger).
14.3. A macromodel for the 2N6073 Triac is available in the SPICE model libraries. Its ter-
minals are ordered in the model call as {MT2 gate MT1}. Repeat the functional test of
Problem 14.1 on a 100 Vp p sinusoid to show that positive gate current pulses trigger con-
duction in both directions (the minimum magnitude gate trigger current is about 20 mA:
increase the magnitude of the current pulses so that the SCR will properly trigger).
14.4. A macromodel for the 2N6073 Triac is available in the SPICE model libraries. Its ter-
minals are ordered in the model call as {MT2 gate MT1}. Repeat the functional test
of Problem 14.1 on a 100 Vp p sinusoid to show that negative gate current pulses trig-
ger conduction in both directions (the minimum gate magnitude trigger current is about
20 mA: increase the magnitude of the current pulses so that the SCR will properly trig-
ger).
14.5. A power conversion system is under design. e input to this system is standard 110 VAC
at 60 Hz: the output is variable-voltage DC supplied to a 100 resistive load. It has been
decided to achieve the design goals using a variable delay one-shot and an SCR as shown.
(a) Complete the design using a 2N1599 SCR and a capacitor that will provide no more
than 8% ripple.
(b) Use SPICE to verify proper operation when the SCR is triggered over 20% of the
input sinusoidal waveform.
(c) Use SPICE to verify proper operation when the SCR is triggered over 80% of the
14.6. PROBLEMS 1043
• •
110 V + Control 100 Ω C

60 Hz – System
(one shot)
• •
14.6. e power conversion system of Problem 14.5 is to be redesigned using a Triac rather
than an SCR. is redesign requires the addition of a full-wave rectifier bridge, but allows
greater efficiency of power conversion.
(a) Complete the design using a 2N6073 Triac and a capacitor that will provide no
more than 8% ripple.
(b) Use SPICE to verify proper operation when the Triac is triggered over 20% of the
(c) Use SPICE to verify proper operation when the Triac is triggered over 160% of the
14.7. e basic Zener diode voltage reference circuit of Figure 14.10 is proposed as a voltage
reference circuit with an output of 4 V. Assume the Zener diodes are characterized by a
Zener voltage, Vz D 4 V, and Zener resistance. rz D 40 . e resistor, R, in the voltage
reference circuit has value 10 k.
(a) Determine the nominal output voltage, Vref , of the circuit to an input, Vin D 16 V.
(b) Assume that Vin experiences an AC ripple of amplitude 2 Vp p. What is the AC

ripple in the output, Vref ?
14.8. e circuit shown is proposed as a voltage reference circuit with an output of 4 V. Assume
the Zener diodes are characterized by a Zener voltage, Vz D 4 V, and Zener resistance.
rz D 40 .
(a) Determine the nominal output voltage, Vref , of the circuit to an input, Vin D 16 V.
(b) Assume that Vin experiences an AC ripple of amplitude 2 Vp p. What is the AC

ripple in the output, Vref ?
Vin◦• •
5.6 kΩ
• βF = 120
• ◦• Vref
12 kΩ
14.9. Design a constant-current voltage reference with an output of 2.0 V. Assume an input
voltage ranging from 4 V to 6 V, Silicon BJTs and Zener diodes with the following prop-
erties:
minimum Zener current — 1 mA

Zener resistance — 5
ˇF — 150
14.10. A constant-current voltage reference is designed with the basic topology identified in
Figure 14.11 and the following circuit elements (parameters are found in the SPICE
libraries):
BJTs — 2N2222 Zener diode — 1N750

RSC — 680 R — 1.6 k
(a) Estimate the nominal output voltage.
(b) Assume the input voltage, Vin , varies between 8 V and 12 V, use SPICE to determine
the variation in the output voltage, Vref .
(c) Compare SPICE results to theory.
14.11. Design a bandgap voltage reference with an output of 1.2 V. Assume an input voltage
5 V. What is the ideal temperature variation of the transistor base-emitter junction
voltage?
14.12. Design a bandgap voltage reference with an output of 1.4 V. Assume an input voltage
12 V. What is the ideal temperature variation of the transistor base-emitter junction
voltage?
14.13. Design a 5 V series voltage regulator using the basic topology shown in Figure 14.13. e
input voltage falls in the range 6 V < Vin < 10 V. Assume the following components are
available:
14.6. PROBLEMS 1045
Precision voltage reference — 1.2 V
Comparator — LM111
Bipolar Junction Transistor — ˇF D 100
Resistors — any standard value
Verify correct operation using SPICE for a load of 100 . Note: the macromodel for
the LM111 comparator has an open-collector output—a pull-up resistor is required for
HIGH output.
14.14. Design a 3.3 V series voltage regulator using the basic topology shown in Figure 14.13.
e input voltage falls in the range 6 V < Vin < 12 V. Assume the following components
are available:

Verify correct operation using SPICE for a loads of 100 and 1 k. Note: the macro-
model for the LM111 comparator has an open-collector output—a pull-up resistor is
required for HIGH output.
14.15. Design a 5 V shunt voltage regulator using the basic topology shown in Figure 14.14. e
input voltage falls in the range 6 V < Vin < 10 V. Assume the following components are
available:

HIGH output.
14.16. Design a 3.3 V shunt voltage regulator using the basic topology shown in Figure 14.14.
e input voltage falls in the range 6 V < Vin < 10 V. Assume the following components
are available:

HIGH output.
14.17. Use SPICE and the macromodel for the LM7805C to verify that a C 5 V regulator can
correctly regulate to achieve a C 5 V output.
(a) Over what range of output current will the LM7805C macromodel provide correct
regulation?
(b) What is the minimum input voltage that provides correct regulation for an output
current of 100 mA? 10 mA?
correctly regulate to achieve a C 15 V output.
(a) Over what range of output current will the LM7815C macromodel provide correct
regulation?
(b) What is the minimum input voltage that provides correct regulation for an output
current of 100 mA? 10 mA?
correctly regulate to achieve a 5 V output. Assume the input voltage varies in the range,
7 < Vi < 15 and a load current of 150 mA.
14.20. Design a 7.5 V voltage regulator using a 5 V, three-terminal regulator and the basic topol-
ogy shown in Figure 14.20. e input voltage falls in the range 9 V < Vin < 15 V. Assume
the following components are available:
5 V fixed voltage regulator — LM7805C

OpAmp — A741
Verify correct operation using SPICE for a load of 100 .

14.21. Design a 16 V voltage regulator using a 12 V, three-terminal regulator and the basic topol-
ogy shown in Figure 14.20. e input voltage falls in the range 20 V < Vin < 30 V. As-
sume the following components are available:
12 V fixed voltage regulator — LM7812CT

OpAmp — A741
Verify correct operation using SPICE for a load of 200 mA.

14.6. PROBLEMS 1047
14.22. An automotive application requires a current of 10 ˙ 0:1 mA to be delivered to a variable
load (470 > Rload > 100 ). e input voltage to the system varies between 11 V and
16 V. Design a constant current source using a LM7805C 5 V regulator. Verify proper
operation of the design using SPICE.
14.23. e 78XX series of voltage regulators is limited to approximately 1.0 A output current
(with appropriate heat sinks). e current boost configuration of Figure 14.22 has been
selected for a design requiring a regulated output voltage at an output current, Io 5:0 A.
e input voltage is: Vin 10 V. Complete the design by specifying proper resistance
values and component power ratings. Assume ˇF D 100.
14.24. e 78XX series of voltage regulators is limited to approximately 1.0 A output current
(with appropriate heat sinks). e current boost configuration shown has been selected
for a design requiring a regulated output voltage at an output current, Io 5:0 A. e
input voltage is: Vin 10 V. Complete the design by specifying proper resistance values
and component power ratings. Assume ˇF D 100.
RSC
Vin◦• • • • Q2
Q1
Io
• • LM 7805C • ◦• Vref
R 5V
Regulator
14.25. Complete the design of the overvoltage protection circuit shown by specifying the power
ratings necessary for Qp and Zp if the input voltage is limited to 50 V. Use SPICE to
verify proper operation. Assume ˇF D 60 and a maximum load current of 250 mA.
Vin•◦ • QP • LM 7805C • ◦• Vo
5V
1 kΩ Regulator
•
Vz =10 V ZP
• •
Overvoltage Protection
14.26. It is necessary to provide a regulated voltage at 10 V with a maximum current of 100 mA.
e input voltage lies in the range, 15 < Vi < 55 V. A LM7805, 5 V regulator is the
only readily available component. While this regulator can supply adequate current, the
improper output voltage and an input voltage limitation of 35 V demands that additional
circuitry be added to the design.
(a) Using the basic circuit topology of Figure 14.23, design a voltage regulator that
will meet specifications. Be sure all component specifications include power ratings.
Assume ˇF D 60.
(b) Verify proper operation of the design using SPICE.
14.27. A Varistor that has a non-linearity factor, a D 0:80, and allows one ampere or current
at 50 V is being compared to back-to-back Zener diodes with SPICE parameters, IS
D 10 nA, IBV D 50 mA, and BV D 15 V.
(a) At what voltage does each voltage protection system allow the same current?
(b) What is the value of that current?
(c) If the current is increased 20% what voltage appears across each system?
14.28. Back-to-back 1N750 Zener diodes are proposed as a transient protection device for a 5 V
circuit. e device being protected is essentially resistive and draws a nominal current of
50 mA. Use SPICE to determine the following.
(a) e maximum voltage that will be applied to the load if an input current twice the
nominal value is applied to the protected device.
(b) e maximum voltage that will be applied to the load if a current spike of magnitude
150 mA and duration 0.1 s (rise and fall times 0:1 ns) is applied to the load.
14.29. An approximate model of a varistor can be generated in SPICE using a non-linear
voltage-controlled current source. e controlling voltage for the source is simply the
voltage across the source. e non-linear properties of the varistor can be approximated
as an odd-order polynomial in the voltage across the varistor.
(a) For a varistor that has a non-linearity factor, a D 0:80, which allows one ampere of
current at 50 V, determine an approximate expression for the current through the
varistor expressed as a fifth-order polynomial of the voltage across the varistor.
(b) Use SPICE to plot the V-I transfer relationship of this model.
(c) Compare this V-I transfer relationship to that of back-to-back Zener diodes with
SPICE parameters IS D 10 nA, BV D 15 V, and IBV D 50 mA.
(d) Compare the voltage across each system when subjected to a current consisting of a
2 mA constant current that momentarily (duration 1 s) jumps to 4 mA.
14.30. Design a simple SCR crowbar overvoltage protection circuit that activates at an input
voltage of C 10 V. Use the following parts:
Zener diode — any specified Zener voltage

SCR — 2n1599 (gate turn-on voltage 0.7 V: turn-on current 2 mA)
Assume a source output resistance of 10 .

Verify correct crowbar operation using SPICE for a load of 100 . Comment on the
accuracy of the crowbar voltage and what variation in design might be necessary.
14.31. Design a simple SCR crowbar overvoltage protection circuit that activates at an input
voltage of C 40 V. Use the following parts:
Zener diode — any specified Zener voltage

SCR — 2N1599 (gate turn-on voltage 0.7 V: turn-on current 2 mA)
Assume a source output resistance of 10 .

Verify correct crowbar operation using SPICE for a load of 1 k. Comment on the ac-
curacy of the crowbar voltage and what variation in design might be necessary.
REFERENCES
[1] ——-, Linear Circuits Data Book, Volume 3, Voltage Regulators and Supervisors, Texas In-
struments Inc., Dallas, 1989.
[2] ——-, Linear/Switchmode Voltage Regulator Handbook, 4th Ed., Motorola Inc., Phoenix
1989.
[3] ——-, yristor Device Data Manual, Motorola, Inc., Phoenix, 1992.
[4] Fisher, Marvin J., Power Electronics, PWS-Kent Publishing Co., Boston, 1991.
[5] Baliga, Jayant B. and Chen, Dan Y., Editors, Power Transistors: Device Design and Appli-
cations, the Institue of Electrical and Electronics Engineers, Inc., New York, 1984.
[6] Cherniak, Steve, A Review of Transients and eir Means of Suppression, Motorola, Inc.,
Phoenix 1991.
[7] Horowitz, Paul and Hill, Winfield, e Art of Electronics, 2nd Ed., Cambridge University
Press, Cambridge, 1989.
[8] Kassakian, John G., Schlecht, Martin F., and Verghese, George C., Principles of Power
Electronics, Addison-Wesley Publishing Co., Reading, 1991.
[9] Millman, Jacob, Microelectronics, Digital and Analog Circuits and Systems, McGraw-Hill
Book Co., New York, 1979.
[10] Mitchell, Daniel M., DC - DC Switching Regulator Analysis, McGraw-Hill Book Com-
pany, New York, 1988.
1051
CHAPTER 15
Communication Circuits
e rapid development of computer technology has been followed by an explosion in the de-
mand for high-speed low-cost telecommunication products to complement the growing demand
for information transfer. New communication systems have been exploited to satisfy the telecom-
munication needs of the public. For example, the rapid growth in private wireless communication,
most notably the cellular telephone, has increased the demand for high quality, low cost electronic
circuits.
As this chapter will show, many subsystems that make up modern communication systems
are designed using the basic principles established in the previous chapters. By integrating func-
tional electronic blocks consisting of simple amplifiers or filters, application-specific communi-
cation electronic subsystems can be designed. Although a complete discussion of communication
electronics requires volumes of books, this chapter presents an overview of some of the concepts
used in designing those circuits.
e discussion in this chapter is limited to circuits operating at modest frequencies (be-
low 20 MHz). In the RF range of frequencies, a different set of two port parameters, called S-
parameters, are used to quantify active and passive devices and circuits. S -parameters are based on
the devices or circuit behavior when terminating the network ports with a known impedance
rather than an open circuit or a short circuit. Another reason for using S -parameters lies in
the dependence of RF and microwave circuit analysis on the reflection (or Scattering, hence S -
parameter) of electromagnetic waves.
e topics in this chapter are representative of the types of circuits commonly used in
communications systems. Overviews are presented on analog-to-digital conversion, voltage-
controlled oscillators, mixers, phase-lock loops, filter concepts, modulator/demodulator design,
and issues important to good receiver design.
15.1 ANALOG-TO-DIGITAL CONVERSION

Most of the chapters in this text have been concerned exclusively with digital or exclusively analog
topics. However, many systems use mixed-mode signaling: mixed-mode systems process both
digital and analog signal characteristics. Consequently, the conversion of analog-to-digital signals
is a common practice in modern electronic systems.
For example, audio signals in the form of music are converted to digital signals using so-
phisticated analog-to-digital converters (ADC) and stored on compact disks (CD) for sale to the
public. Analog telephone voice signals are converted to digital signals for transmission on fiber
1052 15. COMMUNICATION CIRCUITS
optic systems. High Definition Television (HDTV) signals used digital signaling to transmit high
resolution video images.
As technology advances, more signals from various transducers (microphones, cameras,
medical sensors, and other sensors) are converted from analog to digital form for efficient and
reliable transmission.
ere are many different ADC circuits. Many incorporate digital integrated circuits which
have not been discussed in this book. erefore, the discussion in this chapter is limited to the
Flash ADC circuit. However, prior to describing the Flash ADC, an introduction to analog-to-
digital conversion principles is in order.
15.1.1 QUANTIZING AND SAMPLING

An analog signal voltage range is defined as the maximum peak-to-peak voltage excursion of
the signal as shown in Figure 15.1a. When the peak-to-peak amplitude of the analog signal is
divided into 2N equal quantization levels (or bands) and sampled at times T0 ; T1 ; T2 ; : : : ; Tn ,
discrete values of the signal voltage at the sampled times can be found. e result is a digitized
form of the analog signal. e analog signal with its associated quantization levels and sampling
times is shown in Figure 15.1b.
A (t)
111
Vpeak 110
101
100
011
t 010
001
000
−Vpeak T0 T1 T2 T3 T4 T5 T6 T7 t
(a) (b)
Figure 15.1: (a) Analog signal in time domain; (b) Quantizing times and sampling levels.
e resulting digital reconstruction of the analog signal in Figure 15.1 using N D 3 quan-
tization levels at sampling times T0 ; T1 ; T2 ; : : : ; Tn , is shown in Figure 15.2.
When the analog signal is sampled, the voltage level corresponding to the sampling time
is held at that quantization level until the next sample causes the level to shift. Notice that each
sampled quantization level takes a discrete value corresponding to the discrete quantizing levels
(in Figure 15.2 there are 8 levels). Upon completion of the sampling process, the ADC generates
15.1. ANALOG-TO-DIGITAL CONVERSION 1053
111
110
101
100
011
010
001
000
T0 T1 T2 T3 T4 T5 T6 T7 t
Figure 15.2: Digital signal reconstruction of analog signal.
a binary code representing the sampled quantization levels. In Figure 15.2, the number of discrete
quantization levels is 2N , where N D 3, so the ADC generates a binary code of 3 bits/sample.
Each discrete quantization level in the case where N D 3 has amplitude 2Vpeak =8).
15.1.2 QUANTIZING ERROR AND SAMPLING FREQUENCY

e waveform in Figure 15.2 is clearly not an exact duplicate of the analog waveform shown in
Figure 15.1. By low-pass filtering the digitized waveform, the high frequency components of the
signal can be eliminated and the square corners rounded to improve its likeness to the original
signal. However, because the sampled signal is forced to take on a discrete, quantized value, the
original voltage level, which may lie between the discrete levels, may not be reproduced. is type
of error is called quantizing error. In communications systems, this type of distortion is called
quantizing error.
e quantizing error can be reduced by generating more discrete voltage levels and reducing
the voltage sampling interval. For example, a 4-bit ADC converts an analog signal to 16 discrete
quantization levels: 14-bit ADCs converts an analog signal to 16,384 discrete quantization levels.
Although advantageous in many respects, high resolution (large number of quantization intervals,
2N ) creates a significant design problem when sampling small input signals due to random thermal
noise.
Another common form of distortion occurs when the incoming analog waveform is sam-
pled at too low a frequency, corresponding to an unacceptably large sampling interval. is prob-
lem is corrected by sampling at frequencies equal to or greater than required by the Nyquist
sampling criterion. e Nyquist criterion states that if the highest frequency component of a
waveform is fh , then the waveform must be sampled at least at the Nyquist frequency, 2fh .
15.1.3 FLASH ANALOG-TO-DIGITAL CONVERTERS
Common ADC topologies used in modern communications systems include the single-ramp
ADC, dual-ramp ADC, charge-redistribution ADC, and Flash ADC. All but the Flash ADC
require digital logic implementations. e basic strategy of the single-ramp ADC is to convert
the analog input voltage to a measurable time interval and transform that time interval to a digital
word. e dual-ramp ADC is a higher resolution form of the single-ramp ADC. e operation
of the charge-redistribution ADC is based on the cycling of charge about a binary weighted array
of capacitors.
One of the simplest ADC circuits involves a parallel set of voltage comparators used to
compare the incoming signal waveform voltage to a reference voltage. is form of ADC circuit
is commonly called a Flash ADC and is shown in Figure 15.3. e input waveform has been pro-
cessed by a sample-and-hold circuit like the one shown in Figure 15.4 and the output is typically
decoded to become binary.
VREF Vanalog (from sample-and-hold)

◦• ◦•
◦• − Ro
◦• ◦• ◦• D2
R ◦• +
◦• ◦•
◦• VH VL
− Ro
◦• ◦• ◦• D1
R ◦• +
◦• ◦•
◦• VH VL
− Ro
◦• ◦• ◦• D0
+
R
◦• ◦•
VH VL
Figure 15.3: 2-Bit (4 level) flash ADC with clamps to limit output voltage.
e function of the sample-and-hold circuit is to track the input and hold the input volt-
age level providing a stable output signal to the ADC during the sampling interval. e basic
storage device that “holds” the voltage in Figure 15.4 is the capacitor C . e capacitor charges
rapidly when the switch is closed. When the switch, usually a FET controlled by digital circuitry,
15.2. VOLTAGE-CONTROLLED OSCILLATORS 1055
Interval Control
Vwaveform
◦• + R
◦• ◦• ◦• ◦• +
− ◦• ◦•Vanalog
C −
Figure 15.4: Sample-and-hold circuit.
is open, the large time constant of the capacitor and the input resistance of the output buffer
OpAmp prevent the capacitor from discharging. us, a stable voltage is provided during the ac-
tual conversion process. For the circuit to operate properly, the charging time must be very short
with respect to the input waveform variations. e charging and discharging times associated
with the RC circuit are chosen to achieve the desired design accuracy and sampling time interval.
e operation of the parallel bank of comparators in a Flash ADC is based on the process-
ing of the waveform in relation to the known reference voltage derived from precision voltage
reference.¹ is reference voltage is divided by a series of resistors of equal value into the desired
number of quantization intervals. Using the parallel bank of comparators, the input waveform
sample is compared to each divided voltage: when the sample is larger, the comparator will output
a positive result. All comparators with divided reference voltage below the input sample voltage
will have positive outputs.
e high parallelism of the Flash ADC has the potential for very high-speed analog-to-
digital conversion. However, the difficulties presented by this type of ADC include the large
number of resistors and comparators required for a large number of quantization levels. Addi-
tionally, the output must be encoded into a binary code which requires additional circuitry. ese
encoders can be complex and may offset the high speed advantages of the Flash ADC.
Despite the potential drawbacks, the Flash ADC is in wide use and is considered as a good
design option for many systems where high-speed conversions are required. With the availability
of inexpensive OpAmps and high-speed programmable digital logic, Flash ADCs will most likely
remain as a good design option for many applications.
15.2 VOLTAGE-CONTROLLED OSCILLATORS

In communications circuits, it is often desirable to have the ability to change the oscillation fre-
quency of a oscillator by applying a voltage to the circuit. Oscillators that allow for control of the
frequency of oscillation by an applied voltage are called Voltage-Controlled Oscillators (VCO).²
¹Precision voltage references are presented in Chapter 14 of this book.
²A very simple, low-frequency VCO using multivibrators is presented in Section 13.2.
In practice, the Colpitts oscillator topology is most commonly used to design VCOs in
communication electronics. Several phenomena can be exploited to allow voltage control of the
oscillation frequency of an electronic oscillator. ey included:
• Bias-control to alter amplifier gain and device capacitance.
• Voltage-variable capacitors to alter the circuit resonant frequency.
• Voltage-variable resistors to alter gain.
e first two of these techniques are discussed in this section. Both arrangements alter the re-
active LC feedback network of oscillator as a function of an input voltage to alter the oscillation
frequency. e use of voltage-variable resistors (e.g., FETs operating in the ohmic region) is not
commonly found in VCOs for communication electronics applications: they are, however, used
in phase-shift oscillator-type VCOs in low frequency applications.
Bias-Controlled VCO
In Chapter 12, it was shown that the capacitance values of the LC reactive network of a BJT
Colpitts oscillator, shown in Figure 15.5, is dependent on the gain of the circuit.
◦• +VCC
◦•
RC
RB1
◦• vo L
CB ◦• ◦• ◦•
C2 C’1
◦• ◦•
◦•
RB2
RE CE
◦• ◦•
Figure 15.5: Colpitts oscillator circuit.
In order to achieve a particular frequency of oscillation, the capacitance values C10 and C2
are highly dependent on the gain of the BJT circuit. e value of C1 D C10 C Ci , where Ci is the
BJT equivalent input capacitance is given by,
C1 D C10 C Ci
D C10 C C C C .1 C gm R/ (15.1)
D C10 C C C C f1 C gm1 ŒRB1 ==RB2 ==RC == .rb C r /g :
e small signal capacitance values associated with the BJT are,

CJC
C D ; (15.2)
VCB 0:33
1C
0:75
and

gm
C D C : (15.3)
2fT
It is evident from Equations (15.1) to (15.3) that the capacitance C1 is highly dependent of the
small-signal mutual conductance, gm , of the transistor. Since the mutual conductance of a BJT
is a function of the bias condition, C1 p is a also a function of the bias current. By changing C1 ,
the oscillation frequency, fo D .1=2/ .C1 C C2 /=.LC1 C2 /, can be altered while maintaining
a constant value for C2 and L.
One method of varying the oscillation frequency of a Colpitts oscillator is, therefore, to
change the bias condition of the transistor. Figure 15.6 is one implementation of a Colpitts Bias-
Controlled VCO. e transistor Q2 is a constant current source where the bias current is con-
trolled by Vm . e collector current through Q1 is increased by increasing the control voltage Vm
in Q2 . An increase in the bias current of Q1 will result in a corresponding increase in the capacitor
C1 . e capacitor CE acts as an emitter bypass capacitor for Q1 . e resistor RB1 is a bias resistor
for Q1 .
◦•+VCC
RC
◦• vo L
CB ◦• ◦• ◦•
C2 C’1
◦• Q1
◦•
RB1
◦•
CE
Vm ◦• ◦• Q2
RB2
RB3
RE
◦•
◦•−VEE
Figure 15.6: Bias-controlled BJT Colpitts VCO.
Example 15.1 Bias-Controlled Colpitts Oscillator Tuning Range

Find the frequency tuning range as a function of the bias control voltage, Vm , for the BJT Col-
pitts VCO shown. e bias control voltage range is: 10 < Vm < 10 V. e BJTs have identical
parameters.
e transistor parameters are:
ˇF D 200 VA D 200 V
rb D 30 Cobo D 5 pF
fT D 250 MHz.
15 V◦• +VCC
◦•
RC
1 kΩ
L
IC1 ◦• vo 6.8 µH
RB1
CB 13.2 kΩ ◦• ◦• ◦•
6.8 µF
C2 C’1
◦• Q1
◦•
RB2
13.2 kΩ 1 pF 22 pF
IE1
= −IC2 ◦•
CE
RB3 68 µF
Vm ◦• ◦• Q2
62 kΩ
RB4
22 kΩ RE
15 kΩ
◦•
−15 V ◦• −VEE
Solution:
Determine the DC condition of the circuit by solving for IC1 ; VCE1 , and VCE2 over the
tuning voltage range, Vm . e quiescent collector current for Q1 is:
2 3
Vm RB4
C V V 1
ˇF 1 ˇF 2 6 RB3 C RB4 EE 7
IC1 D 6 7:
ˇF 1 C 1 ˇF 2 C 1 4 RB4 ==RB3 5
RE C
ˇF 2 C 1
e ranges for the collector current of Q1 ; VCE1 , and VCE2 for the bias voltage input of in value
from 10 < Vm < 10 V are:
0.77 mA < IC1 < 1.12 mA
7.08 V < VCE1 < 7.43 V
5.05 V < VCE < 10.24 V.
ese voltage and collector current ranges confirm that the transistors are in the forward-active
region of operation.
e mutual conductance and input resistance of Q1 are,
jIC1 j jIC1 j
gm1 D D ;
Vt 0:026
ˇF 1 ˇF 1 V t 0:026 ˇF 1
Ri D rb1 C r1 r1 D D D :
gm1 jIC1 j jIC1 j
For Q1 the capacitance, C1 D Cobo D 5 pF. e capacitance, C1 , of Q1 is given by

gm1
C1 D C1 :
2fT
One of the oscillator capacitors, C1 , is dependent on the bias condition of Q1 ,
gm1
C1 D C10 C C1 C C1 Œ1 C gm1 .Ri ==RB1 ==RB2 ==RC / ;
2fT
and the frequency of oscillation is given by,
s
1 C1 C C2
fo D :
2 LC1 C2
Since C1 is a function of the bias conditions of Q1 , the frequency of oscillation is also a function
of bias conditions. Using the equations above, the MathCAD routine shown below is used to find
the frequency of oscillation as a function of the bias control voltage.
12
C1p WD 22 10 C2 WD 1:0 10 12 L WD 6:8 10 6 VEE WD 15
ˇF WD 200 C WD 5 10 12 f t WD 250 106 V WD 0:7
i
i WD 0 : : : 50 V mi WD 10 C 50 20
0 1
V mi 22
2 C V V
ˇF B 22 C 62 EE C
IC1i WD B@
C
A
ˇF C 1 1620
15000 C
ˇF C 1
IC1i ˇF 0:026
gmi WD ri WD
0:026 IC1i
" #
1
gmi 1 1 1
C1i WD C1p C C C C 1 C gmi C C
2 f t 6600 1000 ri
s
1 C1i C C2
f oi WD :
2 L C1i C2
e resulting graph is shown below.

61.23
61.22
Frequency (MHz)
61.21
61.2
61.19
61.18
−10 −8 −6 −4 −2 0 2 4 6 8 10
Bias Control Voltage
e graph indicates that the VCO tuning range is approximately 61.18 MHz < fo <
61.23 MHz for 10 < Vm < 10 V, and is quite linear.
e gain of the circuit is, for all practical purposes, invariant. erefore, the Barkhausen
criterion for oscillation is satisfied over the bias control voltage range.
Varicap VCO
By far the most common method for controlling the oscillation frequency of an oscillator is with
a voltage using a varactor diode. e capacitance of a varactor diode (sometimes called a tuning
diode, voltage-variable capacitance diode, or varicap) is dependent on the reverse bias voltage
across the diode. e depletion capacitance of a diode was presented in Chapter 10 (Book 3) and
is repeated here for convenience,
Cjo
Cj D ; (15.4)
Vd m
1
o
where
Cjo small-signal junction capacitance at zero voltage bias (SPICE parameter CJO)
o junction built in potential (SPICE parameters VJ)
m junction grading coefficient, 0.2 < m 0:5 (SPICE parameter MJ).
e symbol for a varactor diode is shown in Figure 15.7.
A common varactor diode is the MV2102.³ e parameters of interest for this device are
0 D 0:7266 V; Cjo D 17:88 pF, and m D 0:424. A graph of the capacitance as a function of the
reverse bias voltage is shown in Figure 15.8.
³Multisim™ provides a SPICE model for the MV2102 varactor diode as manufactured by Zetex Semiconductors as the
FMMV2102 varactor diode.
+ Vd −
◦• ◦•
Figure 15.7: Circuit symbol for a varactor diode.
18
16
14
12
Cj
(pF)
10
4
0 2 4 6 8 10 12 14 16 18 20
Vd
Reverse Bias Voltage (V)
Figure 15.8: Capacitance as a function of reverse bias voltage for an MV2102 varactor diode.
◦• +VCC
◦•
RC
RB1 ◦• Vm < VC
◦• vo L
VC ◦• ◦• ◦•
C2 C’1
◦• ◦•
◦•
◦•
CB RB2
RE CE
◦• ◦•
Figure 15.9: Varactor diode-based VCO.

A BJT-based Colpitts VCO can be designed by connecting a varactor diode in parallel (in
an AC sense) to C2 as shown in Figure 15.9. is has the effect of increasing the value of C2 .
Increasing C2 decreases the oscillation frequency by approximately the square-root of the
increase in C2 . Care must be taken so that the voltage at the anode of the diode, Vm , is smaller
than the collector voltage, VC of the BJT so as to not affect the bias conditions of the transistor.
Example 15.2
Tuning voltage of VCO with varactor diode.
For the circuit below, what is the range of the tuning voltage, Vm , so that the VCO will
tune over the frequency range of 10.5 MHz fo 10.7 MHz?
Assume that the transistor parameters are:
ˇF D 200; VA D 150 V; rb D 30 ,
C D 3 pF, and fT D 250 MHz.
+15 V ◦• +VCC
◦•
RC
2.2 kΩ ◦• Vm D (MV2201)
1
+
Vd L
− ◦• vo 1.0 µH
RB1 ◦• ◦• •
C2 C’1
220 pF 0.01 µF
◦• ◦• ◦•
CB ◦•
68 µF RB2
120 kΩ RE CE
6.49 kΩ 68 µF
◦• ◦•
Solution:
e DC conditions of this circuit were established in Example 12.2. e capacitance, C1 ,
was found to be C1 D 10:2 nF.
e oscillation frequency of the VCO without the varactor diode is:
s s
1 C1 C C2 1 10:2 10 9 C 220 10 12
fo D D D 10:85 MHz:
2 LC1 C2 2 10 6 10:2 10 9 220 10 12
is result implies that for small varicap capacitances, the oscillation frequency approaches
10.85 MHz.
In order to meet the specification for the maximum VCO frequency of 10.7 MHz, C2 D
226:15 pF. e capacitance value of the varicap must add to the physical capacitance in the cir-
cuit: 226:15 pF 220 pF D 6:15 pF. From the MV2102 characteristic graph of capacitance as a
function of reverse bias voltage in Figure 15.8, 6.15 pF corresponds to Vd D 8:28 V.
For the minimum VCO frequency specification of 10.5 MHz, C2 D 235 pF. e capaci-
tance value of the varicap must be 235 pF 220 pF D 15 pF. From the MV2202 characteristic
graph of capacitance as a function of reverse bias voltage in Figure 15.8, 15 pF corresponds to
Vd D 0:37 V.
Since IC D 1 mA (found in Example 12.2), the DC voltage at the collector of the BJT is,
VC D Vo;DC D VCC IC RC D 15 .0:001/ .2200/ D 12:8 V:
For a slowly varying voltage, Vm , the reverse bias voltage across the varactor diode is,
Vd D Vo;DC Vm :
e tuning voltage is then,
Vm D Vo;DC Vd :
e tuning voltage for a 10.5 MHz oscillation frequency is then,
Vm D Vo;DC Vd D 12:8 0:37 D 12:43 V:
e tuning voltage for a 10.7 MHz oscillation frequency is then,
Vm D Vo;DC Vd D 12:8 8:28 D 4:52 V:
erefore, the calculated tuning voltage range is: 4:52 V < Vm < 12:43 V.
15.3 MIXERS
A mixer uses the non-linearity of a device to produce intermodulation⁴ products. In most appli-
cations, a mixer is used to generate the difference frequency between the input signal (commonly
called the RF in radio frequency applications) and the local oscillator (called the LO; this is just a
stable oscillator circuit). Consider the output from a device with non-linear characteristics,
vo D VDC C a1 vi C a2 vi2 C a3 vi3 C : (15.5)
When two sinusoids are mixed, the input voltage can be represented as,
vi D X1 cos !RF t C X2 cos !LO t: (15.6)

⁴Intermodulation distortion was discussed in Chapter 7 (Book 2). Intermodulation products are those frequency components
that are produced at the output of a device with non-linear characteristics with two inputs of different frequency.
15.3. MIXERS 1065
Substituting Equation (15.6) into Equation (15.5) yields,
vO DVDC C a1 .X1 cos !RF t C X2 cos !LO t / C a2 .X1 cos !RF t C X2 cos !LO t /2
C a3 .X1 cos !RF t C X2 cos !LO t/3 C : (15.7)
By using trigonometric identities, Equation (15.7) yields the magnitude and frequency compo-
nents of the output signal that includes the difference frequency !RF !LO ,
vo D C a2 X1 X2 cos .!RF !LO / t C : (15.8)
is desired difference frequency can be recovered using a bandpass filter.

In typical applications, two signals, RF and LO are applied to the mixer, from which the
difference (or other) intermodulation distortion product is selected. In a receiver, the known signal
is provided by the local oscillator; the unknown signal is the RF . ese two signals are mixed and
filtered. is process of intentionally creating intermodulation products is called heterodyning. e
output of the mixing and filtering process in a receiver is the intermediate frequency (IF ).
Heterodyning has many advantages. One of the advantages heterodyning in a receiver lies
in the reduction of operating frequency from the RF . at is, the RF signal is typically a very high
frequency signal. By mixing the RF with an LO of a specified frequency, the IF is significantly
lower in frequency than the RF , making circuit design less complex.
e symbol for a mixer is shown in Figure 15.10.
◦• × ◦•
◦•
Figure 15.10: Symbol for a mixer.
15.3.1 BJT MIXERS

Typically, fundamental building block mixer designs include small-signal RF amplifiers. ere-
fore, an understanding of small-signal RF amplifier design is critical in the design of mixers. A
small-signal BJT RF amplifier will be used to demonstrate this design technique.
Small-Signal RF Amplifier Design

As in all electronic circuit design, the design of small-signal RF amplifiers involves a great number
of choices and exercise in good judgment. Logically derived rules-of-thumb may be applied to
narrow the options available to the designer.
For example, a single-transistor RF amplifier may utilize a self-biasing scheme for maxi-
mum temperature and device variance stability, as shown in Figure 15.11.
+VCC ◦• ◦•
Rdn Cdn
T1 (k = 1)
◦• ◦• ◦•
+
L1 L2 RL vo (t)
RB1 −
◦•
◦• ◦•
IC Ct
CC
vi (t ) ◦• ◦• Q1
+
◦•
VB
RB2 RE IE CE
−
◦•
Figure 15.11: Small-signal RF amplifier—self-bias configuration.
e design process for this amplifier is as follows:
• Establish stable quiescent conditions
• Optimize collector bias currents for maximum output power
• Decouple the power supplies
• Establish the value of the DC blocking capacitor
• Determine the tuning capacitor value to select the desired signal product
• Determine the effective load at the BJT collector using the transformer Q
For quiescent point stability defined by a 1% (or less) change in collector current for a 10% change
in ˇF , the biasing rule-of-thumb is,
RB ˇF
1; (15.9)
RE 9
where
RB D RB1 ==RB2 : (15.10)

15.3. MIXERS 1067
Another rule of thumb sets the voltage across RE to 10% of VCC ,
VCC
RE D : (15.11)
10IE
A convenient value for RB2 is,
VB VB ˇF
RB2 D D ; (15.12)
10IB 10IC
where
VB D IE RE C VBE ; and VBE 0:7 V:
Optimum collector bias current is based on the maximum output (RF ) power Po and power supply
voltage VCC . A transformer-coupled class A amplifier can achieve a maximum efficiency of 50%
at full output voltage swing. If VE is 10% of VCC , then the power supply is providing
PDC D 0:9VCC IC ; (15.13)
to the collector of the transistor. For a 50% efficiency,
PO
PDC D D 2PO ; (15.14)

such that
2PO
IC D : (15.15)
0:9VCC
For example, if PO D 10 mW and VCC D 12 V; IC D 20 mW=.0:9 12 V/ D 1:85 mA. e
emitter resistance is then RE D 0:1.12 V/=1:85 mA D 649 .
Rdn and Cdn form a lowpass filter called a decoupling network which provides an AC low
impedance point between the collector and base. e decoupling network also isolates the am-
plifier from the power supply rail from possible feedback to other amplifiers. RF chokes are not
recommended as a replacement for Rdn because of potential resonance effects with Cdn . A value
of Rdn D 100 is typical for low power amplifiers and will result in only a few tenths of volts
coupled away from the amplifier. Cdn is a bypass capacitor that is chosen for a reactance of one
order of magnitude less than the resistance. For example, if the amplifier is used at 455 kHz and
Rdn D 100 , then XC 10 so that Cdn 0:035 F. Cdn is in series with CE (AC path). Be-
cause CE typically has a reactance of a few ohms, it is appropriate to make Cdn D CE .
e emitter bypass capacitor CE provides an AC low impedance for the transistor emitter.
It is typically sufficient in RF circuit design (low impedance circuits) to make XCE an order of
magnitude less than the inverse of the transconductance of the transistor,
1 Vt
XCE D D : (15.16)
10gm 10IC
e value of the DC blocking capacitor CC is determined in the same way as a bypass except
that its reactance should be an order of magnitude less that the amplifier input impedance: that
is, XCC D Zin =10, where Zin is the amplifier input impedance. e Zin of an RF amplifier must
include all input capacitances.
e capacitor C t is a tuning capacitance to tune to the proper Q and bandwidth at the IF
frequency,
1
Ct D ; (15.17)
.2fIF /2 L1
where fIF is the IF frequency.
At the output, the effective quality factor, Qeff of the transformer must be determined to
determine the load reflected onto the collector of the transistor. First, the reactance of the pri-
mary of the transformer XL1 is determined. Knowing the desired bandwidth of fIF ; BW IF ; Qeff D
0
fIF =BW eff : then RL1 D XL1 Qeff and
q
0
np =ns D RL1=RL
:
Active Mixer Design

e design of an active mixer is the same as that of the small-signal RF amplifier. e only dif-
ference is an additional input for the local oscillator (LO) as shown in Figure 15.12.
+VCC ◦• ◦•
Rdn Cdn
RLO
T1 (k = 1)
vLO (t ) ◦• ◦• ◦• ◦•
+
CLO L1 L2 RL vo (t)
RB1 −
◦•
◦• ◦•
IC Ct
CC
vi (t ) ◦• ◦• ◦• Q1
+
◦•
VB
RB2 RE IE CE
−
◦•
Figure 15.12: Active mixer.

15.3. MIXERS 1069
e coupling capacitor CLO is,
1
CLO D ; (15.18)
2fLO RLO
where RLO is the LO source resistance.
15.3.2 DUAL GATE FET MIXER

A dual-gate FET is an n-channel depletion type FET (commonly a GaAs MESFET) with two
independently insulated gate terminals. MESFETs operate essentially like a MOSFET, but can
be used at very high frequencies, on the order of several GHz. ese FETs have a series arrange-
ment of two separate channels, with each channels having independent gate control. e circuit
symbol for the n-channel depletion type dual-gate MESFET is shown in Figure 15.13a, with the
simplified symbol in Figure 15.13b. Dual-gate MESFETs are used at very high frequencies and
are commonly used in mixer, modulator, and Automatic Gain Control (AGC) circuits. When
Gate 2 is at AC ground, the dual-gate FET may be represented as a common-source, common-
gate (CS-CG) pair, referred to as the cascode circuit, shown in Figure 15.14.
D D
◦• ◦•
G2 ◦• G2 ◦•
G1 ◦• G1 ◦•
◦• ◦•
S S
(a) (b)
Figure 15.13: (a) Dual-gate n-channel depletion MESFET symbol; (b) Simplified dual-gate MES-
FET circuit symbol.
D
◦•
G2◦•
G1 ◦•
◦•
S
Figure 15.14: Dual-gate n-channel depletion MESFET equivalent representation.

In mixer/modulator applications, the LO is applied to Gate 1, and the output taken from
the drain (common-source configuration). e baseband signal is applied to Gate 2 to modulate
the LO signal.
A dual-gate n-channel depletion MESFET mixer makes use of the isolated gates for good
isolation between the LO and the baseband is shown in Figure 15.15. e IF output is transformer
coupled for impedance matching and isolation.
Bias of AGC Voltage V• DD
◦• ◦
◦• ◦• VIF
RG2 Ct
C1
VLO◦• ◦• ◦• ◦•
RGG
◦•
VRF◦• ◦• ◦•
C2 RS
CS
RG1
◦•
Figure 15.15: Dual-gate n-channel depletion type MESFET mixer.
15.4 PHASE-LOCK LOOPS

e phase-lock loop (PLL) is used to track the phase and frequency of a signal. It is often used
in the receiver in both amplitude modulated (AM) and frequency modulated (FM) systems. In
addition to AM and FM receiver applications, PLLs are used in control applications, such as in
a compact disk (CD) player, to track the rotational speed of the CD.
e PLL is a feedback system as shown in Figure 15.16. In the PLL, the feedback signal
is intended to follow the phase and frequency of the input signal. However, in the case where
the input and feedback signals are not equal, the difference between the two, called the error
signal, will change the feedback signal. e feedback signal will continue to change and until it
again matches the input signal. e feedback quantity that is compared with the input signal is
a generalized phase angle .t /. A generalized phase angle is composed of a frequency and phase
component: that is,
.t / D !c t C c .t / ; (15.19)
where !c is a set frequency, often called the carrier frequency in communication systems, and
c .t/ is a time varying phase.
e frequency of the output signal of the VCO is adjusted until its generalized phase angle
is close to that of the input signal of the PLL. When the generalized phase angles of the input
15.4. PHASE-LOCK LOOPS 1071
Phase Detector Lowpass
Vc, fc, θc Vp, fc ± fo, θc Vd
(Mixer) Loop Filter
Kd KaH(s)
Voltage
Vo, fo, θo Controlled
Oscillator
Ko
Figure 15.16: Block diagram of a phase-lock loop.
signal and the output of the VCO are nearly identical, the two signals are synchronized. ere
is, however, a constant phase difference between the two signals due to signal delay through the
PLL.
Although several different analog and digital implementations of the PLL are widely used,
one of the most common configurations uses a mixer as a phase comparator, a loop filter with a
response Ka H.s/, and a VCO. e error or difference voltage, Vd , is the output of the loop filter
which is the controlling voltage to the VCO. For a quiescent VCO frequency of !c , the error
voltage Vd D 0, and the loop is said to be in lock.
Phase Detector
When the PLL is in lock, the output voltage of the phase detector is the difference fre-
quency signal with phase difference, or static phase error, e D c o . If the input signal
to the mixer phase detector is vc .t / D Vc sin.!c t C c /, the reference signal from the VCO is
vo .t/ D Vo sin.!c t C /, and !c D !o , then the output signal of the mixer phase detector is,
Vc Vo Vc Vo
Vp .t/ D vc .t/ vo .t/ D K cos e K cos .2!o t C e / ; (15.20)
2 2
where K is the mixer gain.
Since the lowpass loop filter eliminates the second harmonic term from the output of the
mixer phase detector, only the first term of Equation (15.20) is considered: that is,
Vc Vo
Vp D K cos d : (15.21)
2
For the case where the input frequency, fs , is equal to the free-running quiescent frequency of
the VCO, fo ; e D =2 and the difference voltage Vd D 0. erefore, the output voltage of the
phase detector is also zero. e error signal is proportional to phase differences about 90ı . For
small changes in phase e ,

e C e ; (15.22)
2
and the mixer phase detector output is,
Vc Vo Vc Vo
Vp D K cos C e D K sin .e /
2 2 2 (15.23)
Vc Vo
Ke :
2
For small phase perturbation, e ,
Vc Vo K
Vp e ; (15.24)
2
under the assumption that
Vp D Kd .c o / ; (15.25)
where Kd is the phase detector scale factor defined as,
Vc V0 K
Kd D :
2
e gain of each of the components of the PLL must be defined in order to find the closed loop
transfer function. When the loop is in lock, the gain factor of the phase detector is,
Vp
Kd D V=rad: (15.26)
sin e
In PLLs, the phase e is usually designed to be small so that a pulse of noise will not throw the
loop out of lock.
Loop Filter
e lowpass loop filter can be passive or active. When passive filters are used, an amplifier with
gain Ka is usually required to increase the amplitude of the filtered difference signal. Two lowpass
passive filters are shown in Figure 15.17. A first or second order Butterworth lowpass filter may
be used as the active loop filter in the PLL.
For the simple lowpass filter without gain in Figure 15.17a, the transfer function is,
1
H .s/ D : (15.27)
1 C sR1 C
For the lag-lead loop filter without gain shown in Figure 15.17b, the transfer function is,
1 C sR2 C
H .s/ D : (15.28)
1 C s .R1 C R2 / C
R1 R1
◦• ◦• ◦• ◦• ◦• ◦•
+ + + +
R2
vi C vo vi vo
C
− − − −
◦• ◦• ◦• ◦• ◦• ◦•
(a) (b)
Figure 15.17: Two passive lowpass loop filter configurations.
Voltage-Controlled Oscillator
e output frequency of the VCO is expressed as,
Ko
fo D ff C vd ; (15.29)
2
where
fo is the oscillator output frequency in Hertz,

ff is the quiescent frequency of the VCO in Hertz, and
Ko is the VCO voltage to frequency relationship in radians per volt (rad/V).
Equation (15.29) can be written in terms of radian frequency,
!o D !f C Ko vd : (15.30)
e total generalized phase angle of the output of the VCO is,

Z t

.t/ D !f C ! dt D !f t C o .t/ ; (15.31)
0
where ! is the frequency deviation from !f .

erefore, the phase term is defined as,
Z t
o .t / D ! dt; (15.32)
0
or
d o .t/
D ! D Ko vd : (15.33)
dt
e difference voltage, vd , is a DC voltage when the loop is in lock. When not the PLL
is not in lock, vd is a voltage corresponding to the difference frequency (fc fo ) that draws the
VCO in to synchronization with the input signal. When the PLL is in lock, the VCO output
frequency equals that of the input signal. However, there is a phase difference detected by the
phase detector between the VCO and input signals. is difference is called the static phase error,
e . e static phase error is used to maintain the necessary control voltage on the VCO to maintain
the required frequency to keep the PLL in lock.
In the s-domain, Equation (15.33) is,
Vd .s/
ô .s/ D Ko ; (15.34)
s
which clearly shows that the VCO performs as an integrator for phase errors. As an integrator,
the VCO helps maintain PLL lock through momentary disturbances.
Closed-Loop Transfer Function

e closed loop transfer function of a PLL is found by determining the ratio ô .s/=ˆc .s/, where
ô .s/ and ˆc .s/ are frequency domain representations of o .t / and c .t /, respectively. is quan-
tity provides a measure of the loop response to changes in the input phase or frequency. e VCO
input signal is,
Vd .s/ D Ve .s/ H .s/ Ka ; (15.35)
and
Ve .s/ D Kd ê .s/ : (15.36)
e DC loop gain is,

Ve .s/ Vd .s/ ! !
Kv D Kd Ka Ko D D : (15.37)
ê .s/ Ve .s/ Vd .s/ ê .s/
Substituting Equations (15.35) through (15.37) into (15.34) yields,
H .s/
ô .s/ D Kv ê .s/ : (15.38)
s
e open-loop transfer function is defined as,
ô .s/ H .s/
P .s/ D D Kv ; (15.39)
ê .s/ s
and the closed-loop transfer function is,
ô .s/ P .s/ Kv H .s/
F .s/ D D D : (15.40)
ˆc .s/ 1 C P .s/ s C Kv H .s/
From Equation (15.40), it is apparent that the transfer function of the loop filter is a major factor
in determining the loop performance. When the filter bandwidth is reduced, the response time
to changes in phase or frequency is increased, and helps maintain loop lock against momentary
disturbances of the input signal.
Other types of phase detectors are also used in commercial PLLs. e type of phase detec-
tor circuit selected depends on many factors including, cost, size, speed, noise performance, and
manufacturability. Mixer phase detectors are most commonly used in applications where little
VCO frequency deviation from the free-running state is required. For high-speed performance,
digital phase detectors using Emitter-Coupled Logic (ECL) circuitry are usually preferred and
are commercially available in single chip PLL packages.
Example 15.3 Loop Characteristics

For the PLL shown below, determine:
1. Gain of the OpAmp amplifier
2. Loop gain in units of 1/seconds and in dBs at ! D 1 rad/s
3. VCO output frequency when the PLL is phase-locked
4. Static phase error, e , and Vd when the PLL is phase-locked.

Kd = 0.1V/rad
Vp Vp Ka
A +
fc = 110 kHz
̟/2 θp ◦• ◦•Vd
−
◦• ◦•
R2
R1
3.3 kΩ
1 kΩ
VCO
fFR = 120 kHz
Ko = −30 kHz/V
Solution:
(a) Gain of the OpAmp amplifier.

e OpAmp amplifier is in the non-inverting configuration. erefore, the gain of the
amplifier is,
R2 3:3 k
Ka D 1 C D1C D 4:3:
R1 1k
(b) Loop gain in units of 1/seconds and in dBs at ! D 1 rad/s.
Kv D Kd Ka Ko D .0:1 rad=V/ .4:3/ . 30 kHz=rad/ D 12:9 kHz=V:
Converting 12:9 kHz=V to units of 1/s,

Kv D 12:9 kcycles=s rad 2 rad=cycle D 81; 053 s 1 :
Expressed in dB,
Kv;dB D 20 log .jKv j/ D 20 log .81053/ D 98:2 dB at 1 rad=s:
(c) VCO output frequency when the PLL is phase-locked.

When the PLL is locked, the VCO frequency is, by definition, fo D fi D 110 kHz. Only
a phase difference can exist between the input signal and the VCO output at the phase
detector. is phase difference is called the static phase error that yields a difference voltage
output from the loop filter which provides sufficient frequency control voltage to the VCO
to maintain frequency lock.
(d) Static phase error, e , and Vd when the PLL is phase-locked.
e VCO control voltage, Vd , is,
fc fo .110 kHz 120 kHz/
Vd D D D 0:33 V:
Ko 30 kHz=V
Since the gain of the OpAmp amplifier is 4.3, the output of the phase detector/filter, Vp , is
0:33 V
Vp D D 0:077 V:
4:3
e static phase error is,
Vp 0:077 V
e D D D 0:77 rad:
kd 0:1 V=rad
Hold-In Range
e range of frequencies over which the loop maintains lock is called the hold-in range. For a
PLL where the amplifier does not saturate and the VCO has a wide frequency range, the phase
detector characteristic limits the hold-in range. As static phase error increases due to increasing
input frequency, fc , a limit for the output of the phase detector is reached beyond which the
phase detector cannot supply additional corrective control voltage to the VCO. If the phase de-
tector cannot produce more than Vp;max , the total range of the phase detector output is ˙Vp;max ,
15.5. ACTIVE AND PASSIVE FILTER DESIGN 1077
for a total range the static phase error e D c o is radians. e hold-in frequency is the
minimum to maximum input frequency range fc;max fc;min D fH ,
Kv
fH D ; (15.41)
4
where Kv is in radians/second.
15.5 ACTIVE AND PASSIVE FILTER DESIGN

Signal filtering is often central to the design of many communication subsystems. e isolation
or elimination of information contained in frequency ranges is of critical importance. In simple
amplitude modulation (AM) radio receivers, for example, the user selects one radio station using a
bandpass filter techniques. Other radio stations occupying frequencies close to the selected radio
station are eliminated. e standard AM broadcast band in North America is from 535 kHz to
1605 kHz.
In Chapter 9 (Book 3), active filter concepts using OpAmps were introduced. One of the
advantages of using active filters included the addition of some gain. However, due to their limited
gain-bandwidth product, active filters using OpAmps see little use in communication system
design.
e two types of frequency selective circuit configurations most commonly used in com-
munication systems are the passive LC filter (low, high, and bandpass responses) and the tuned
amplifier (bandpass response). In this section, an overview of these two types of frequency selec-
tive circuit configurations for use in bandpass applications is provided.
15.5.1 PASSIVE LC FILTERS

A capacitor coupled low-pass filter configuration is shown in Figure 15.18. is type of filter con-
sists of L and C components connected in a “ladder” network with component values, gn , deter-
mined by the polynomial coefficients for the desired type of filter (i.e., Butterworth or Chebyshev
polynomials) and the required system input and output impedances. For this section, the system
input and output impedances are assumed to be the same value (a typical value for many RF
applications is 50 ). Similarly, the gn values are normalized to these identical input and output
resistances. e determination of component values begins with the specifications and procedures
outlined in Chapter 9 (Book 3) and specified source and load resistances.
For simplicity, Chebyshev filters are commonly chosen to be odd-order filters: this choice results
in identical input and output resistances. erefore, the first and last filter normalized component
values, go and gN C1 , are equal to 1 for both Butterworth and these odd-order Chebyshev filters.
By setting the first and last normalized component values, go and gN C1 respectively, equal
to 1 (equal input and output resistance R), the intermediate inductor and capacitor values for the
filters are found to be:
gn gn R
C D and L D ;
2fc R 2fc
RG = go = 1 g2
◦• ◦• ◦•
+ g1 g3 gN+1
−
◦• ◦• ◦•
Figure 15.18: Low pass filter “ladder” network.
where
fc is the cutoff frequency (Hz),

R is the input and output resistance (commonly 50 );
gn are the Butterworth or Chebyshev polynomial values.
For Butterworth filters, the polynomial values, gn , are obtained by doubling the factored poly-
nomial damping coefficients (Table 9.2 (Book 3))—a first order factor results in a g value of 2.
Determination of the Chebyshev filter values is a more complex operation: a selection of values
is listed in Table 15.1.
High-pass and band-pass filter designs are achieved using techniques similar to those de-
scribed above and in Chapter 9 (Book 3) by replacing the normalized prototype low-pass filter
components with those shown in Table 15.2.
For band-pass and band-stop values, the bandwidth BW is
BW D !U !L ;
where
!U is the upper cutoff frequency of the band-pass or band-stop filter

!L is the lower cutoff frequency of the band-pass or band-stop filter:
Table 15.1: Normalized Chebyshev filter values
Low-Pass Chebyshev Filter: 0.5 dB Ripple

N g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11
1 0.6986 1.0000
2 1.4029 0.7071 1.9841
3 1.5963 1.0967 1.5963 1.0000
4 1.6703 1.1926 2.3661 9.8419 1.9841
5 1.7058 1.2296 2.5408 1.2296 1.7058 1.0000
6 1.7254 1.2479 2.6064 1.3137 2.4758 0.8696 1.9841
7 1.7372 1.2583 2.6381 1.3444 2.6381 1.2583 1.7372 1.0000
8 1.7451 1.2647 2.6564 1.3590 2.6964 1.3389 2.5093 0.8796 1.9841
9 1.7504 1.2690 2.6678 1.3673 2.7939 1.3673 2.6678 1.2690 1.7504 1.0000
10 1.7543 1.2721 2.6754 1.3275 2.7392 1.3806 2.7231 1.3485 2.5239 0.8842 1.9841
Low-Pass Chebyshev Filter: 3 dB Ripple

N g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11
1 1.9953 1.0000
2 3.1013 0.5339 5.8095
3 3.3487 0.7117 3.3487 1.0000
4 3.4389 0.7483 4.3471 0.5920 5.8095
5 3.4817 0.7619 4.5381 0.7618 3.4817 1.0000
6 3.5045 0.7685 4.6061 0.7929 4.4641 0.6033 5.8095
7 3.5182 0.7723 4.6386 0.8039 4.6386 0.7723 3.5182 1.0000
8 3.5277 0.7745 4.6575 0.8089 4.6990 0.8018 4.4990 0.6073 5.8095
9 3.5340 0.7760 4.6692 0.8118 4.7272 0.8118 4.6692 0.7760 3.5340 1.0000
10 3.5384 0.7771 4.6768 0.8136 4.7425 0.8164 4.7260 0.8051 4.5142 0.6091 5.8095
Table 15.2: Component transformation from low-pass values
Low-pass Low-pass High- Bandpass Bandstop

Prototype pass
L
BW
L 1 1 (BW)L
L = gk
ωc ωc L (BW)L ωo2
BW
ωo2 L
1
(BW)C
C 1
C = gk C BW
ωc ωc C
BW ω2oC
(BW)C
ωo2

Design a Butterworth low-pass filter with 3 dB cut-off frequency of 900 MHz and a stop band
attenuation of 22 dB at 1.8 GHz. e source and load impedances are 50 .
Solution:
e first task is to find the required order of the filter which fulfills the specifications. Using
the technique developed in Chapter 9 (Book 3), the order is found to be:
s

22=20 1800 2N log 1022=10 1
10 D 1C or N D D 3:65:
900 2 log.1800=900/
Since filters must be integer order, a 4t h order filter is necessary.

e normalized component values for the low-pass filter are determined from the fourth-
order Butterworth damping coefficients as tabulated in Table 9.2 (Book 3). Each normalized
component value is double a Butterworth damping coefficient:
g1 D g4 D 2 0:3827 D 0:7654
g2 D g3 D 2 0:9239 D 1:8478:
e value of g5 D 1 is the normalized load resistance that is equal to the normalized source re-
sistance, g0 D 1.
e filter component values are computed to be:
R0 D 1.50/ Source Resistance D 50
C1 D 0:7654=.2fc .50// Shunt Capacitor, C1 D 2:71 pF
L2 D 1:8478.50/=.2fc / Series Inductor, L2 D 16:33 nH
C3 D 1:8478=.2fc .50// Shunt Capacitor, C3 D 6:54 pF
L4 D 0:7654.50/=.2fc / Series Inductor, L4 D 6:77 nH
RL D 1.50/ Load Resistance D 50 .
50 Ω 16.33 nH 6.77 nH
◦• ◦• ◦•
+
−
2.71 pF 6.54 pF 50 Ω
◦• ◦• ◦•
e SPICE simulation normalized frequency response is shown in Figure 15.19.
−10
(900.0000 M, −3.0172dB)
Magnitude
−20
−30
(1.8000 G, −24.1123dB)
−40
100 M 1G
Frequency (Hz)
Figure 15.19: Low pass filter response for Example 15.4.
15.5.2 TUNED AMPLIFIERS

Tuned amplifiers are designed to amplify a narrow band of frequencies centered about the center
frequency fo . ey can be used as amplifying bandpass filters in contrast to the passive LC filters
previously discussed. Unlike wideband amplifiers that were presented in previous chapters, the
design of tuned amplifiers requires careful design to avoid oscillations due to the reactive load
and the internal reactive feedback elements of the transistor. Since tuned amplifiers only operate
over a narrow band of frequencies (˙ 5% of the center frequency), the two-port parameters of
the active device at the center frequency are used in the design.
e simplest, and most common, form of tuned amplifier is the single-tuned amplifier.
e single-tuned amplifier is designed using a FET, BJT, or OpAmp. Naturally, the OpAmp
implementation suffers from bandwidth limitations due to the OpAmp gain-bandwidth product.
e one common denominator found in different types of single-tuned amplifiers is the use
of a passive parallel resonant circuit shown in Figure 15.20a using a non-ideal finite-Q (unloaded)
inductor and capacitor. e non-ideal inductor can be modeled as an ideal inductor with a series
resistor, r , as shown in Figure 15.20b.
◦• ◦•
◦• ◦•
L
C L C
(Qu)
r
◦• ◦•
◦• ◦•
(a) (b)
Figure 15.20: Passive parallel resonant circuit.
e relationship between the unloaded Qu of the inductor, resonant frequency, and the inherent
series resistance, r , is,
!o L
Qu D : (15.42)
r
e admittance of the circuit is,
1
Y D j!C C
r C j!L
(15.43)
r !L
D 2 C j !C :
r C ! 2 L2 r 2 C ! 2 L2
At the resonant frequency, ! D !o and the imaginary component goes to zero. erefore,
!o L
!o C D : (15.44)
r2 C !o 2 L2
Solving for !o yields the expression for the resonant frequency in terms of the passive components,
r r 2
1
!o D : (15.45)
LC L
Using Equation (15.42), Equation (15.45) can be re-written in terms of the unloaded Q of the
inductor,
s
1 Qu2
!o D : (15.46)
LC Qu2 C 1
A finite Q inductor has the effect of reducing the resonant natural frequency of an ideal
LC circuit by a factor of Qu2 =.Qu2 C 1/. erefore, the series RL branch in Figure 15.20b can
be replaced with a resistor Rp and Lp in parallel, creating a parallel RLC circuit as shown in
Figure 15.21.
◦•
◦•
C Lp Rp
◦•
◦•
Figure 15.21: Parallel equivalent circuit of LC circuit using non-ideal inductors.
e parallel equivalent circuit parameters have the values,

Rp D r Qu2 C 1 ; (15.47)
and

Qu2 C 1
Lp D Ls : (15.48)
Qu2
If r !L then,
!2L
Rp D D !LQu D rQu2 : (15.49)
r
e impedance of the parallel equivalent circuit is,
Rp
Z .!/ D : (15.50)
! !o
1 C j Qu
!o !
A single-tuned amplifier uses the parallel LC resonant circuit (commonly called the tank circuit)
in place of a load resistor. e small resistance inherent in the non-ideal inductor must be taken in
to account when biasing the circuit. Since the impedance is highest at the resonant frequency, fo ,
the gain of the circuit peaks at that frequency. For frequencies far from fo , the load impedance
is small which has the effect of reducing gain.
FET Single-Tuned Amplifier

A simple single-tuned NMOSFET amplifier is shown in Figure 15.22. e resonant components
of this tuned amplifier are RD ==rd ; CT ==Co , and LT , where Co is the effective output capacitance
of the NMOSFET. e inductor is non-ideal with a unloaded Q factor specified by Qu .
V
◦• DD
◦•
Cr LT
(Qu)
◦• ◦• ◦•
+
◦• ◦•
+
◦• vo
vi RG
RS CS
− −
◦• ◦• ◦• ◦• ◦•
Figure 15.22: Single-tuned NMOSFET amplifier.
Using the parallel equivalent model of an LC tank circuit shown in Figure 15.21, the small-signal
model of the single-tuned NMOSFET amplifier of Figure 15.22 is shown in Figure 15.23. e
resistance Rp is the resistance associated with inductor.
e voltage transfer characteristic of the circuit is,
0 1
vo gm gm B
B s C
C;
Av D D D (15.51)
vi 1 C @ G 1 A
G C sC C s2 C s C
sLp C Lp C
◦• ◦• ◦• ◦• ◦• ◦• ◦• ◦• ◦• ◦•
+ + +
gmvgs
vi RG Ci vgs rd Co CT Lp Rp vi
− − −
◦• ◦• ◦• ◦• ◦• ◦• ◦• ◦• ◦• ◦•
Figure 15.23: Small-signal equivalent circuit of an NMOSFET single-tuned amplifier.
where
1
GD ; and C D Co C CT :
Rp ==rd
e magnitude of the gain is,
2 3
6 7
gm 6 ! 7
jAv .j!/j D 6s 7 (15.52)
C 6 2 7 :
4 G 2 1 2
5
! C !
C Lp C
Equation (15.52) is maximum-valued when the circuit is operating at the resonant frequency, !o ,
with bandwidth !3 dB defined as,
1 1
!o D p and !3 dB D : (15.53)
Lp C RC
e gain at resonance is,
gm
jAv .j !o /j D D gm rd ==Rp : (15.54)
G
BJT Single-Tuned Amplifier

A BJT tuned amplifier is shown in Figure 15.24. Note that the resonant circuit is at the input of
the transistor amplifier VCC .
e current gain of the circuit shown in Figure 15.24 is,
io gm gm
Av D D D ; (15.55)
ii 1 R
G C sC C 1 C sRC C
sLp sLp
where
C D CT C Ci ; R D RB1 ==RB2 ==RP ; G D 1=R:
Equation (15.55) is of the same form as Equation (15.51). erefore, the expression for the res-
onant frequency and bandwidth of the circuit is identical to that of the FET tuned amplifier.
VCC
◦•
◦•
RC
RB1
◦• ◦
+
◦• ◦• ◦• ◦•
+
◦• vo
LT
vi CT RB2
(Qu) RE CE
− −
◦• ◦• ◦• ◦• ◦• ◦• ◦•
Figure 15.24: BJT tuned amplifier.
15.6 MODULATOR/DEMODULATOR DESIGN

Modulation is the process of combining information with a separate waveform to allow efficient
transmission. Demodulation is the process of recovering information from waveform that has
been altered to carry that information. ere are a variety of modulator and demodulator de-
sign options. Modulators can be designed from combinations of mixers, non-linear amplifiers,
VCOs, diode circuits, and filters. Similarly, demodulators can be designed from combinations of
electronic circuits. Many of the design options can be explored through discussion of amplitude
modulation (AM) and frequency modulation (FM).
AM Modulation
In AM systems, it is typical to use mixers in the modulator to shift the baseband (or “raw” in-
formation such as audio) signal to a higher frequency to allow for transmission on an assigned
carrier frequency. In AM radio receivers, the FCC approved radio frequency range is 540 kHz to
1600 kHz. Each radio station is allocated a frequency in that frequency range at 10 kHz incre-
ments.
In AM modulation, the baseband information alters the amplitude of a sinusoid at a sig-
nificantly higher frequency than the highest baseband frequency. e high frequency sinusoid is
called the carrier frequency. e heterodyning process is used to demodulate AM signals by shift-
ing the AM radio frequency signal down to a lower IF frequency. AM radio receivers typically
use 455 kHz IF electronics to process the modulated signal.
A simple Double-Side Band-Suppressed Carrier (DSB-SC) form of amplitude modulation
using a mixer is shown in Figure 15.25.
15.6. MODULATOR/DEMODULATOR DESIGN 1087
m (t) m (t)cos(ωc t)
×
cos(ωc t)
LO
Figure 15.25: DSB-SC mixer modulator.
In many instances, it is desirable to transmit not only the baseband information which has been
up-converted to a higher frequency, but to also sent the carrier signal. Common examples of this
type of AM are AM radio transmission where the station carrier frequency is transmitted with
the up-converted information, and television signals. One possible method of transmitting a DSB
plus a carrier (DSB+C) signal is shown in Figure 15.26.
m (t) m (t)cos(ωc t) (A + m (t))cos(ωc t)

+
× ∑
+
cos(ωc t)
Gain
LO
A
Figure 15.26: DSBCC modulator.
AM Demodulation
An envelope detector is the most common circuit used for converting of AM to baseband signal.
An envelope detector is simply a lowpass filter allowing only the baseband signal to pass while
eliminating the IF component generated after a mixer down-converts the modulated signal from
the high carrier frequency. A simple envelope detector is shown in Figure 15.27. e diode allows
only those signals greater than 0 V to pass through the detector. e input signal to the envelope
detector is AM with carrier signal,
VIF .t / D ŒA C m .t / cos !IF t; (15.56)
where
A is a constant DC voltage
m.t / is the baseband signal
!IF is the IF frequency (e.g., 455 kHz).
D
◦• ◦• ◦• ◦•
+ +
vIF R C vo
− −
◦• ◦• ◦• ◦•
Figure 15.27: Envelope detection for AM.
An alternate technique to demodulate AM signals uses synchronous detection. e AM signal of

Equation (15.56) is demodulated by multiplying the signal (using a mixer) by a LO signal of the
same carrier frequency as shown in Figure 15.28, where !IF D !c .
VIF (t) Vd (t) Lowpass Vo (t)

× Filter
2B cos[ωct + фo(t)]
LO
Figure 15.28: Synchronous direct conversion AM demodulator.
e output of the mixer for !IF D !c is:
vd .t/ D 2B ŒA C m .t / cos .!IF t / cos .!IF t C o /

D B ŒA C m .t / Œcos .!IF t !IF t o / C cos .!IF t C !IF t C o / (15.57)
D B ŒA C m .t / Œcos o C cos .2!IF t C o / :
e mixer output consists of a baseband signal, BŒA C m.t/ cos o , and a modulated signal at
the second harmonic frequency of the carrier, BŒA C m.t / cos.2!IF t C o /. e lowpass filter
removes the high frequency component so that the resulting output is the demodulated baseband
signal with some gain and DC bias,
Vd .t/ D B ŒA C m .t / cos o : (15.58)
Unfortunately, since the input phase angle of the signal is not known, the output voltage
can be very small. A phase difference o D 0 yields the maximum output voltage. is implies that
the LO must be phase-locked to the carrier signal. In this case, the demodulation is truly one of
coherent detection which has superior signal-to-noise performance over non-coherent detection
methods such as with the use of envelope detectors. To insure that the LO is in phase-locked to
the input carrier signal, a PLL can be used. e complete diagram of the PLL AM demodulator
is shown in Figure 15.29. Since the phase detector causes the loop to lock with the VCO 90ı out
of phase with the input, a 90ı phase shifter is placed between the output of the VCO and the
mixer demodulator.
Phase Detector PLL

VIF (t) Vd (t) Lowpass
◦• × Loop Filter
Voltage
◦• Controlled
Oscillator
90˚
Mixer Demodulator
×
Vo (t)
Lowpass
Figure 15.29: Phase-locked coherent AM demodulator.
RF frequency phase-shift networks that shift the phase by 90ı at a single frequency are usually
designed as LC circuits.
FM Modulation
In frequency modulated transmission, the baseband information alters the frequency of a sinusoid
at a significantly higher frequency than the highest baseband frequency, whereas in phase mod-
ulated transmission, the baseband information alters the phase of a sinusoid. One of the most
common methods used to generate frequency or phase modulated (FM and PM , respectively)
signals is to use a VCO. By applying a time varying signal to reverse-bias a varactor diode in a
VCO, an angle (generalized angle: either phase or frequency) modulated signal can be generated.
One cannot distinguish the difference between an FM or PM signal by merely observing its time
domain characteristics.
PM modulation is characterized by the following,

'PM .t/ D A cos !c t kp sin !c t ; (15.59)
and FM modulation is characterized by the following,
Z
'FM .t/ D A cos !c t kf sin !c t m .˛/ d˛ ; (15.60)
where
' is a voltage or current signal
kf and kp are FM and PM constants, respectively
A is a constant.
Other methods for generating PM and FM signals are shown in Figure 15.30, in which DSB-SC
modulators are used for generation of the angle modulated signals.
m (t) DSB-SC −Akpm (t) sin(ωct) φPM (t)

+ ∑
Modulator
+
−A sin(ωct)
̟/2
Gain A cos(ωct)
A
(a)
m (t) a (t) DSB-SC −Akf a(t)sin(ωct) φFM (t)

+
∫ Modulator
∑
+
−A sin(ωct)
̟/2
Gain A cos(ωct)
LO A
(b)
Figure 15.30: (a) PM modulator using DSB-SC modulator; (b) FM modulator using DSB-SC mod-
ulator.
FM Demodulation
ere are a number of different methods for demodulating FM signals after down conversion to
the IF . One common method uses a differentiator in series with an envelope detector. As shown
in Figure 15.31. e output signal from an envelope detector is low pass filtered to provide an
output signal proportional (by a constant kf ) to the original baseband signal.
d Envelope A[ωIF + kf m(t)]

dt Detector
Figure 15.31: FM demodulation by direct differentiation.
Another common type of FM demodulator is the discriminator circuit. is FM demodulator is

often called a slope detector since the principle of detection is based on the detection of the signal
amplitude variation as it traverses the slope of the resonant response of the circuit as shown in
Figure 15.32.
D
◦• ◦• ◦• ◦• ◦• ◦•
+ +
vIF R1 C1 R2 C2 vo
− −
◦• ◦• ◦• ◦• ◦• ◦•
(a)
vo( f )
vo( t )
fo f
fc
(b)
Figure 15.32: (a) Discriminator (slope detection) circuit; (b) Method of demodulating FM signals.
Although conceptually simple, discriminator circuits are sensitive to amplitude variations

in the input signal. Variations in the input modulated signal will produce a falsely demodulated
baseband signal. One solution is to apply the input modulated signal to a limiter prior to demod-
ulation with a discriminator. However, this requirement has eliminated the use of discriminators
in most production entertainment receiver circuits in favor of ratio detectors. In fact, although
many integrated circuit receivers incorporate what are called discriminators, they are actually ratio
detectors.
e ratio detector, shown in Figure 15.33, is similar in operation to discriminators except for
its balanced peak-detector configuration which makes it less susceptible to amplitude variations
in the input modulated signal.
D
Cc ◦• ◦• ◦• ◦•
+ + + +
◦• ◦•
+ v2 C2 v’a C0 R0 va R1 vc +
RFC − −
◦• − ◦• ◦• ◦• − vo + ◦• ◦• − C1
vIF v3
+ − +
+
− v2 v’b C0 R0
vb R1 vd −
◦•
+
− ◦• ◦• ◦• − ◦• −
Figure 15.33: Ratio detector.
e ratio detector operates similarly to a half-wave rectifier with two diodes in series and an
RC filter. e radio frequency choke (RFC) is placed in the circuit for DC isolation. e filtered
output is v3 which is proportional to jv2 j where v2 is the IF phasor voltage on the secondary of
the transformer, and is the diode empirical scaling constant. jv2 j and v3 are essentially inde-
pendent of frequency over the operating bandwidth of the detector. Since v3 is divided across the
two R1 resistors and is symmetrical with respect to ground, vc and vd are of equal amplitude and
v3
vc D vd D ; (15.61)
2
and
v3 D vc C vd : (15.62)
e phasor IF voltage, va0 , between the anode of the top diode and ground is,
v 0a D vIF C v2 ; (15.63)
and the phasor IF voltage, vb0 , between the cathode of the bottom diode and ground is,
v 0b D vIF v2 : (15.64)
e rectified voltages across the two resistors of value R0 are,
va D jvIF C v2 j ; (15.65)
15.7. RECEIVER DESIGN ISSUES 1093
and
vb D jvIF v2 j : (15.66)
e output voltage across the resistor bridge and across the capacitor, C1 , are,
vo D vd vb ; (15.67)
and
v3 D va C vb : (15.68)
Substituting Equations (15.61) and (15.68) into (15.67) yields the output voltage with respect to
the voltages across the two resistors of value R0 ,
v3 va vb va vb
vo D vb D C vb D : (15.69)
2 2 2 2
In steady-state, the diodes conduct during a small portion of each IF cycle. During con-
duction, the capacitors are recharged. e diodes will conduct if the instantaneous IF voltages
va0 and vb0 are greater than the instantaneous voltages va and vb . e peak values of va0 and vb0
drops and the diode conduction period cut short when the input signal level drops. For a given
FM frequency deviation, ! , the Q of the circuit on the secondary of the transformer increases
making †v1 =v2 smaller. is increases the ratio detector output as ! increases.
A PLL can be used to demodulate FM signals. If the PLL is locked onto an input frequency,
the control voltage for the VCO from the loop filter/amplifier is proportional to the VCO’s shift
in frequency from its free-running frequency. e control voltage shifts with a shifting input
signal to the PLL. If the input to the PLL is an FM signal, the VCO control voltage from the
loop filter/amplifier yields the demodulated output. e PLL is able to demodulate FM signals
with a higher degree of linearity than other FM demodulation techniques.
15.7 RECEIVER DESIGN ISSUES

Many factors are used to determine rate receiver performance. e following specifications are
commonly applied to a wide variety of communications receivers.
Sensitivity
Sensitivity is a measure of the weakest received signal that allows acceptable reproduction of the
original signal. Ultimately, the sensitivity is limited by the noise generated by the receiver elec-
tronic circuits. erefore, the receiver output noise is an important factor in quantifying sensitiv-
ity. Sensitivity is defined as the minimum carrier signal input voltage that will produce a specified
signal-to-noise power ratio (SNR) at the output of the intermediate frequency (IF ) section.
Noise Figure
e noise figure (NF ) of a two-port network is a measure of the degradation of the SNR between
the input and output terminals. A two-port network with noise is shown in Figure 15.34 with
input signal power, Psi , and input noise power, Pni , and corresponding output signal power, Pso ,
and output noise power, Pno .
Psi Pso
Network with gain
Pni Ga Pno
Figure 15.34: Two-port network with noisy input and output.
e noise figure as defined over a specified bandwidth is,

input SNR Psi =Pni Pno Pne
NF D D D D1C ; (15.70)
output SNR Pso =Pno Ga Pni Ga Pni
where Pne is the noise power generated by the two-port network.
e value of noise figure is most commonly expressed in terms of decibels:
NF dB D 10 log .NF/ ; (15.71)
for a noise-free network, the input and output SNRs are equal and NF D 1 D 0 dB.
Selectivity
Selectivity is a measure of the receiver’s ability to capture a desired station and eliminate unwanted
signals. is quality is determined in large part by the frequency response of the frequency selec-
tive circuits of the receiver.
Image Rejection
Image rejection is a measure of the attenuation of unwanted sum and difference frequencies pro-
duced by the mixer. Large values are desirable: typical values are about 50 dB.
Intermediate Frequency Rejection

e ratio of inputs at the IF and the desired carrier frequency that produce an equal output from
the mixer is defined as the IF rejection ratio.
Intermodulation Distortion
Intermodulation distortion (IMD) is distortion products created by the non-linear response of
the electronic circuit when excited by two (or more) sinusoidal inputs. IMD produces unwanted
signals that may interfere with, and corrupt the desired signal.
e common theme that prevails in the receiver qualities mentioned are:
• Frequency selectivity
• Noise
• Distortion
By increasing frequency sensitivity, and decreasing noise and distortion in each subsystem.

A sampling of communication electronic circuits was presented in this chapter. Many variants of
the circuit discussed here are being used in a variety of communication system applications.
e circuits and concepts discussed in this chapter clearly shows that most of the circuits
used can be designed and analyzed by the methods discussed thus far in this book. An analog-to-
digital converter used OpAmp comparators to yield a digital representation of the time-varying
input signal. A transistor mixer circuit is merely a small-signal amplifier with two inputs that take
advantage of the nonlinear characteristics of the active device. A voltage controlled oscillator was
shown to be an oscillator circuit with a voltage-variable reactive network. A phase-lock loop is
a subsystem composed of a mixer, loop filter/amplifier, and a voltage controlled oscillator. e
selection of filter configurations was shown to be dependent on the frequency range of operation,
with passive filters used when the frequencies are higher than the audio range. Communications
modulators and demodulators are designed using mixers, diode circuits, and PLLs.
Summary Design Example: Cable Television Converter

It is common to transmit the modulated information on a RF and microwave frequencies. ere-
fore, the received signal must be down-converted prior to demodulation. A down-converter is
required by consumers with non-cable ready television sets in order to receive cable television sig-
nals. Cable television signals typically range in frequency from 55 MHz (channel 2) to 300 MHz
to 1 GHz, depending on the number of standard television signals transmitted by the local cable
television operator.⁵ Since the cable television frequency assignments for channels greater than
13 are different from the broadcast channel frequency assignments, non-cable ready television
sets will not be able to receive channels from the cable that are greater than 13.
To solve this problem, a converter unit is provided to the customer. e purpose of the
converter unit is to down-convert all cable-transmitted channels to channel 3. e output of the
converter unit is applied to the television set with its channel selector tuned to channel 3. Cable
channel selection is performed by the converter unit. Other functions are built into the cable
converter unit including de-scrambling capability to block reception of premium entertainment
channels. e down-conversion to channel 3 (61.25 MHz carrier) is accomplished by a mixer.
e allocated bandwidth per channel is 6 MHz. e frequency range allocated to channel 3 is
60 MHz–66 MHz.
⁵e frequency range depends on the number of standard NTSC format channels. Operational frequency range may be sig-
nificantly different when High Definition Television (HDTV) signals are transmitted.
Several mixer topologies can be considered. e two mixer topologies considered for this
design are:
• BJT active mixer
• Dual-gate FET mixer
For low cost, an inexpensive BJT active mixer may be most appropriate. Typical RF BJT specifi-
cations are:
ˇF D 50; VA D 150 V; rb D 30 ; fT D 5 GHz at 30 mA

Cibo D 8 pF at VEB D 0:5 V; Cobo D 1 pF at VCB D 5 V:
To down-convert channel 7 at a carrier frequency (RF frequency) of 174.25 MHz, the VCO-
LO is set at fLO D 61:25 MHz C 174:25 MHz D 235:5 MHz, resistance RLO D 200 . e IF
frequency is 61.26 MHz.
e mixer is to deliver 10 mW to a 50 load with an efficiency of 50%. e output RF
transformer has a primary inductance of 1.0 H. A 12 V DC power supply is available.
e BJT mixer configuration is shown below:
Rdn
+ VCC ◦• ◦•
Cdn
RLO T1(k = 1)
vLO(t) ◦• ◦• ◦• ◦•
◦• +
L1 L2 RL
CLO vo(t)
RB1 −◦•
◦• ◦•
IC Ct
Cc
vRF(t) ◦• ◦• ◦• Q1
+
◦•
RB2 VB
RE IE CE
−
◦•
DC Design
For VE D 0:1VCC ,
2PO 2 .0:01/
IC D D D 1:85 mA:
0:9VCC 0:9 .12/
For stable BJT operation,
VCC VCC .ˇF C 1/ 12 .51/
RE D D D D 661 680 ;
10IE 10ˇF IC 10 .50/ .0:00185/
VB VB ˇF ˇF . IE RE C VBE / 50 Œ0:00189 .680/ C 0:7
RB2 D D D D D 5:37 k 5:6 k:
10IB 10IC 10IC 0:0185
For quiescent point stability defined by a 1% (or less) change in collector current for a 10% change
in ˇF , the biasing rule-of-thumb is,

ˇF 50
RB RE 1 D 680 1 D 3:1 k 3:0 k;
9 9
where RB D RB1 ==RB2 .
Solving for RB1 yields, RB1 6:2 k.
AC Design
Let the decoupling network resistance, Rdn D 100 . e reactance of the capacitor Cdn must
therefore be, XC 10 , for 61.25 MHz. erefore, the decoupling capacitor is, Cdn 260 pF
or Cdn D 330 pF.
Since CE is in series with Cdn in the AC path, let CE D Cdn .
e emitter bypass capacitor CE provides an AC low impedance for the transistor emitter,
1 Vt 0:026
XCE D D D D 1:4 :
10gm 10IC 10 .0:00185/
erefore,
1 1
CE D D D 1850 pF 2200 pF:
!IF XCE 2 61:25 106 .1:4/
e value of the DC blocking capacitor CC is determined in the same way as a bypass except that
its reactance should be an order of magnitude less that the amplifier input impedance: that is,
XCC D Zin =10, where Zin is the amplifier input impedance.
Zin RB == .rb C r / 3000 == .30 C 703/
XCC D D D 59 :
10 10 10
erefore,
1 1
CC D D D 15:4 pF 15 pF:
!RF XCC 2 174:25 106 .59/
e coupling capacitor CLO is,
1 1
CLO D D D 3:3 pF:
2fLO RLO 2 235:5 106 .200/
e capacitor C t is a tuning capacitance to tune to the proper Q and bandwidth at the IF fre-
quency,
1 1
Ct D 2
D 2 D 6:8 pF:
.2fIF / L1 2 61:25 106 1 10 6
Since video signals are contained in a non-symmetric frequency range about the carrier frequency,
with the carrier signal positioned at 1.25 MHz above the lower frequency corresponding to the
lowest frequency of the channel range. e highest frequency corresponding to the channel range
is 4.75 MHz above the carrier. erefore, the design of the IF mixer bandwidth should contain
fIF ˙ 4:75 MHz. In order to contain those frequencies, a bandwidth of ˙14:25 MHz, which is
wider than ˙4:75 MHz, is used. e output from the mixer will be applied to a filter to appro-
priately shape the video signal.
Knowing the desired bandwidth of fIF and BW IF , the effective quality factor, Qeff of the
transformer is,
Qeff D fIF =BW eff D 61:25 106 =14:25 106 D 4:3:
en the reactance of the primary of the transformer XL1 is,

0
RL1 D XL1 Qeff D 2.61:25 106 /.106 /.4:3/ D 1:65 k:
e transformer turns ratio is,

q p
0
np =ns D RL1 =RL D 1650 =50 D 5:7:
e input impedance of the filter which follows the mixer is 50 .
15.9 PROBLEMS
15.1. Design an 4-bit Flash ADC to digitize an analog signal with a peak-to-peak voltage of
5 V. Assume ideal OpAmps and powered by a ˙12 V power supply. Include the sample-
and-hold circuit.
15.2. A sample-and-hold circuit has a holding capacitor of 50 pF, and the leakage current in
the HOLD mode is 1 nA. If the HOLD interval is 50 s find the percentage output
decay rate (called droop).
15.3. A sample-and hold circuit has a holding capacitor of 100 pF, and the equivalent leakage
resistance in the HOLD mode is 15 G. Estimate the percentage output decay rate
(droop) if the hold interval is 100 s.
15.4. In the circuit of Figure 15.4, let R D 15 k and C D 500 pF. e input bias current
of the output OpAmp is 300 nA. Estimate the percent output decay rate (droop) if the
HOLD interval is 1 V.
15.9. PROBLEMS 1099
15.5. Consider an 8-bit Flash ADC. If the voltage supply VCC consists of a DC voltage VC
and a ripple voltage with peak value ˙. Find to insure that the error produced by
affects no bits other than the lowest significant bit (LSB).
15.6. Design a 1 MHz BJT-bias controlled Colpitts 1 MHz VCO with a ˙10 kHz tuning
range, using a 3.3 H inductor in the reactive feedback path. Find the frequency tuning
range as a function of the bias control voltage, Vm , for the oscillator. e BJTs have
identical parameters:
ˇF D 200; VA D 200 V; rb D 30 ; CJC D 14 pF; and fT D 250 MHz:
15.7. Generate the graph of the MV2102 characteristics for reverse-bias voltages of 0 V to 20 V
as shown in Figure 15.8. e varactor parameters are:
‰0 D 0:7266 V; Cjo D 17:88 pF; and m D 0:424:
15.8. Complete the design of the VCO circuit shown, for a tuning range of 4.95 MHz fo
5:05 MHz. Determine the required range of the tuning voltage, Vm .
Assume that the transistor parameters are:
ˇF D 200, VA D 150 V,
rb D 30 , fT D 250 MHz,
Cibo D 6:5 pF at VEB D 0:5 V,
Cobo D 3:3 pF at VCB D 5 V.
+15
◦• V
◦•
1 kΩ Vm
◦•
+ D1 MV2102
Vd
−
120 kΩ ◦• ◦•
3.0 µH
C2 C1’
◦• Vo ◦• ◦• ◦• ◦•
68 µF
◦•
120 kΩ
68 µF
6.49 kΩ
◦• ◦•
15.9. Design an NMOSFET-based Colpitts VCO at with a tuning rage of 1.97 MHz fo
2.03 MHz using an MV2102 varactor diode. Determine the required range of the tuning
voltage, Vm . e FET parameters of interest are:

A C 15 V power supply is available.

Simulate the circuit using SPICE and confirm the oscillation frequency. How is the
oscillation frequency affected when the temperature is changed to 50ı C?
15.10. Design a 1 MHz Hartley VCO with a ˙ 10 kHz tuning range, using an auto-transformer
and an MV2102 varactor diode. Find the frequency tuning range as a function of the
diode tuning voltage, Vm . e BJT parameters are:
ˇF D 200; VA D 200 V; rb D 30 ; CJC D 14 pF; and fT D 250 MHz:
15.11. Design an active mixer using a BJT with the following parameters:
ˇF D 200; VA D 150 V; rb D 30 ;
Cibo D 3 pF at VEB D 0:5 V; Cobo D 1 pF at VCB D 5 V; and fT D 750 MHz:
e mixer is to deliver 6 mW to a 50 load with an efficiency of 40%. e RF input

frequency is 100 MHz and the IF is 10.7 MHz. e primary inductance of the output
transformer is 0.3 mH (infinite Q). e IF bandwidth is 500 kHz. Use SPICE to confirm
the operation of the mixer (inspect the frequency spectra).
15.12. Design an active mixer using a BJT with the following parameters:
ˇF D 200; VA D 150 V; rb D 30 ;
Cibo D 7 pF at VEB D 0:5 V; Cobo D 4 pF at VCB D 5 V; and fT D 350 MHz:
e mixer is to deliver 15 mW to a 75 load with an efficiency of 40%. e RF input

frequency is 2 MHz and the IF is 455 kHz. e primary inductance of the output trans-
former is 0.3 mH (infinite Q). e IF bandwidth is 25 kHz. Use SPICE to confirm the
operation of the mixer (inspect the frequency spectra).
15.13. For the dual-gate FET mixer shown, determine:
(a) the bias voltage at both gates

(b) the drain and source bias voltages for ID D 2 mA.
15.9. PROBLEMS 1101
(c) the value of L in order to use a 10 pF .max/ variable capacitor at mid capacity if the
stray and FET drain capacitances total 3 pF for an IF of 45 MHz.
VBias VDD
+7 V +15 V
◦• ◦•
◦• ◦• VIF
C1 Ct L
RG2
1000 pF 10 kΩ
VLO◦• ◦• ◦• ◦•
RGG
820 kΩ
◦•
VRF◦• ◦• ◦•
C2 RG1 RS
1000 pF CS
270 kΩ 270 Ω
1000 pF
◦•
15.14. Define phase-locked.

15.15. A phase comparator with triangular transfer characteristic has a maximum output voltage
of 4 V. Determine the gain in Volts/radian and Volts/degree of phase.
15.16. An analog phase detector with two input generators (no VCO) has a beat-frequency
output of 4 V peak-to-peak at 100 Hz. Determine the phase detector gain (sensitivity) in
Volts/radian and Volts/degree of phase.
15.17. A VCO is linear between 250 kHz and 330 kHz. e corresponding input voltages are
220 mV and 220 mV, respectively.
(a) Determine the VCO gain (sensitivity).
(b) Determine the free-running frequency.
15.18. For a PLL with Kd D 0:5 V=rad; Ka D 4, and Ko D 30 kHz=V, a VCO free-running
frequency of 200 kHz and a triangular characteristic:
(a) Determine the PLL loop gain.
(b) Determine the VCO input voltage for the PLL locked to a 180 kHz input signal.
(c) Determine the maximum voltage output from the phase detector.
(d) Determine the hold-in frequency range.
15.19. Complete the system design of the PLL shown for a loop gain of 100 dB at 1 rad/s.
Determine the static phase error, e , and Vd when the PLL is phase-locked.
Kd
Vp Vp Ka
A +
fc = 110 kHz
̟/2 θp ◦• ◦•Vd
−
◦• ◦•
R1 R2
3.3 kΩ
1 kΩ
VCO
fFR = 120 kHz
Ko = −30 kHz/V
15.20. Design a capacitor coupled constant-k bandpass filter centered at 10.7 MHz ˙ 200 kHz,
1 dB maximum ripple, 800 kHz ˙ 100 kHz 3 dB bandwidth, and 25 dB attenuation at
11.5 MHz. e source and load resistors are 75 and the available inductors have a
quality factor of 70. Confirm the design using SPICE.
15.21. A high-selectivity AM receiver has a 455 kHz IF with a 10 kHz, 3 dB bandwidth re-
quirement. Interference at 427.5 kHz coming through the mixer and RF amplifier must
be reduced by 48 dB. Assume a 50 system. e available inductors have a Qu D 100.
Design the filter and confirm its operation using SPICE.
15.22. Perform a SPICE simulation of Example 15.4.
15.23. Design a capacitor coupled bandpass filter with a minimum number of resonators, ripple
0.3 dB, center frequency D 2 MHz, 3 dB bandwidth D 100 kHz, and 36 dB attenua-
tion at 2169 kHz, in a 1 k system. e available inductors have a Qu D 100. Confirm
15.24. A 2.11 GHz, 28.6 MHz bandwidth satellite receiver must reject an adjacent channel
transmitter by 60 dB. Carriers are 36 MHz apart. e filter passband ripple must not ex-
ceed 0.5 dB, and the insertion loss must not exceed 4.4 dB. A cavity filter with Qu D 1000
is used.
(a) How many resonators are required?
(b) What is the actual ripple?
(c) What will be the insertion loss?
15.25. Design a single-tuned FET amplifier with a center frequency at 500 kHz, Q D 50,
and gain jAv j > 5 using an inductor L D 10 H with Qu D 200. e source and
load resistors are each 1 k. e FET parameters are: IDSS D 5 mA; VPO D 2 V; VA D
150 V; Crss D 6:5 pF; Ciss D 35 pF. Confirm the design using SPICE.
15.26. Design a single-tuned BJT amplifier with a center frequency at 220 kHz, Q D 50, and
gain jAv j > 5 using an inductor L D 10 H with Qu D 200. e source and load re-
sistors are each 1 k. e BJT parameters are: ˇF D 200; fT D 400 MHz, VA D 200 V,
and Cobo D 2 pF. Confirm the design using SPICE.
15.27. Complete the design of the envelope detector shown for an IF frequency of 455 kHz,
V D 0:7 V, and P D 1 k.
◦• ◦• ◦• ◦•
+ D +
vIF R C vo
− −
◦• ◦• ◦• ◦•
15.28. Design a LC =2 phase-shifter at an IF frequency of 10.7 MHz. What is the signal
attenuation at the IF ?
15.29. Design a direct differentiation FM demodulator for an IF frequency of 1 MHz.
15.30. Derive the total system noise figure, NF sys , for the two amplifier system shown below.
Pna1 and Pna2 are the noise powers generated by the two amplifiers. e amplifier gains
are Ga1 and Ga2 , with corresponding noise figures NF 1 and NF 2 .
Ga1 Ga2
NF1 NF2
Pni Pni
Pna1 Pna2
Pno1 Pno
REFERENCES
[1] Ghausi, M. S., Electronic Devices and Circuits: Discrete and Integrated, Holt, Rinehart and
Winston, New York, 1985.
[2] Hayward, W. H., Introduction to Radio Frequency Design, Prentice-Hall, Englewood Cliffs,
1982.
[3] Krauss, H. L., Bostian, C. W., and Raab, F. H., Solid State Radio Engineering, John Wiley
& Sons, New York, 1980.
[4] Lathi, B. P., Modern Digital and Analog Communication Systems, 2nd Ed., Holt, Rinehart,
and Winston, Philadelphia, 1989.
[5] Millman, J. and Halkias, C. C., Integrated Electronics: Analog and Digital Circuits and Sys-
tems, McGraw-Hill Book Company, New York, 1972.
[6] Roden, M. S., Analog and Digital Communication Systems, 3rd Ed., Prentice-Hall, Engle-
wood Cliffs, 1991.
[7] Sedra, A. S. and Smith, K. C., Microelectronic Circuits, 3rd Ed., Holt, Rinehart, and Win-
ston, Philadelphia, 1991.
[8] Schilling, D. L. and Belove, C., Electronic Circuits, 3rd Ed., McGraw-Hill Book Company,
New York, 1989.
[9] Smith, J., Modern Communication Circuits, McGraw-Hill Book Company, New York,
1986.
[10] Young, P. H., Electronic Communication Techniques, 3rd Ed., Merrill Publishing Company,
New York, 1994.
1105
CHAPTER 16
Digital Circuits
A digital electronic circuit is a device that operates on single or multiple input signals to produce
an output that is limited to one of a few possibilities. e most common circuits are binary digital
circuits: those circuits that have a single output limited to only two output states. e two-state
behavior of digital circuits leads to referring to two-state a circuit as a “gate”: it is either open or
closed—ON or OFF. Gates are often connected in series with other gates. Gates that drive others
are “master” gates: gates that are driven are “slave” gates. A single gate can perform both master
and slave operations to individual surrounding gates.
Short introductions to the operation of selected binary digital circuits are presented in the
introductory chapters on transistor functionality. Chapter 3 (Book 1) discusses the essential op-
erating principles of two bipolar logic families using simple linear models of the BJT. Chap-
ter 4 (Book 1) discusses MOS logic inverters using the principles of load lines. While it is as-
sumed that the those chapters are prerequisites to this chapter, several digital circuit operating
principles are presented that warrant repetition. Among the most important are:
• Logic Voltage Levels,
• Noise Margin, and
• Fan-out.
e output of a digital circuit is characterized by two voltage levels: a logic HIGH voltage
and a logic LOW voltage. ese voltages are symbolized as VoH and VoL , respectively. e input
is also characterized by two voltage levels: the level above which all inputs are a logic HIGH,
ViH.min/ , and the level below which all inputs are a logic LOW, ViL.max/ . For purposes of noise
immunity it is important that the output and input voltage levels not be the same. Specifically
VoH > ViH.min/ and VoL < ViL.max/ :
e measures of this noise immunity are the noise margins NM(HIGH) and NM(LOW):
NM(HIGH) D VoH ViH.min/ ;
and
NM(LOW) D ViL.max/ VoL :

1106 16. DIGITAL CIRCUITS
VoH
High Noise Margin
V
Master ViH(min) Slave H
O
Gate Gate I
L
G
Output Input H
T
Voltage Voltage A
E
G
R
ViL(max) E
Low Noise Margin

VoL
Figure 16.1: A physical interpretation of noise margin.
A descriptive diagram of the noise margins as well as slave input and master output voltage levels
is shown in Figure 16.1.
Fan-out is a measure of the number of similar slave gates that a master gate can drive
without producing logical errors. Typically, current loading determines the fan-out of a gate, but,
as in the case of MOS gates, gate speed can be the determining factor. Fan-in is another term
often found in the literature: it identifies the number of gate inputs.
While it is impossible to completely describe all types of digital circuits and all aspects
of their operation in a single chapter, this chapter strives to present the essential aspects of the
major digital circuits commonly in use. e fundamentals of the speed of digital logic transitions
begins the discussion of both bipolar and MOS gates. ree families of bipolar gates and two
families of MOS gates are discussed extensively. Regenerative logic circuits (latches, flip-flops,
and Schmitt triggers) arepresented as are the fundamentals of memory circuits. e chapter ends
with a descriptive section on Gallium Arsenide logic circuits.
16.1 THE SWITCHING SPEED OF BIPOLAR JUNCTION

TRANSISTORS
Bipolar Digital Logic gates depend on the transition of the output of a BJT from one logic
level to another. In the case of classic TTL logic gates this transition takes place between the
cut-off and saturation regions of the output transistor. e speed at which any gate operates is
limited by the transition speeds of its constituent transistors. Similarly, the maximum clock rate
at which a synchronous digital system will operate is limited by transistor transition speed. e
transition speed of a transistor is a function of the physical parameters of the transistor and of the
components in the circuit surrounding the transistor. While it is impossible to analyze the effect
of all possible circuit topologies on switching speed, an analysis of the switching speed the simple
BJT inverter provides much insight into all BJT switching.
16.1. THE SWITCHING SPEED OF BIPOLAR JUNCTION TRANSISTORS 1107
As shown in Figure 16.2, a general BJT inverter consists of a common-emitter BJT with
évenin sources connected to the base and collector terminals. ese évenin sources represent
the surrounding logic gate circuitry.
V
◦• cc
◦• ◦•Vout
Rb
Vin +
−
◦•
Figure 16.2: A simple BJT inverter.
As the input voltage changes between logic levels, the output will change to the opposite logic
levels. is transition can not take place instantaneously: various delays must occur. Conceptually,
the response of simple BJT inverter to a rectangular pulse is shown in Figure 16.3.
V(1)
Vin
V(0) V(0)
t0 t1 t2 t3 t4 t5
Vout V(1) V(1)
V(0)
Figure 16.3: e response of an inverter to a digital pulse.
e pulse response consists regions of constancy and regions of transition. In the regions of tran-
sition there are four significant time periods.
• Delay Time D td D t1 t0
• Rise Time D tr D t2 t1
• Storage Time D ts D t4 t3
• Fall Time D tf D t5 t4
e delay time is the time between the pulse transition and when the response transitions 10%
of the distance between HIGH and LOW states. e rise time is the time for a 10% to 90%
transition from HIGH to LOW. e term rise time refers to the BJT collector current change: as
the voltage transitions from a HIGH to LOW, the collector current rises from a minimum to a
maximum value. e storage time and fall time measure the equivalent time periods in the LOW
to HIGH transition.
Rise Time
Perhaps the easiest region to analyze is the rise time. Here the BJT is in the forward-active re-
gion of operation. In this region of operation, the transistor speed is most often described by the
forward time constant, F , or by its frequency-domain equivalent, the unity-gain frequency, !T .¹
1
F : (16.1)
!T
While the forward time constant is a useful parameter (for example, it is necessary in SPICE
analysis), a more relevant parameter for gate speed calculations is the forward-active region time
constant, f :
ˇF 1
f D ˇF F D : (16.2)
!T !3 dB
Transitions between two steady-state levels, Xi and Xf , in the forward-active region are described
by a simple exponential relationship with this time constant:
.t to /
f
X .t / D Xf Xf Xi e : (16.3)
It can easily be shown that rise time of a simple exponential transition is:
rise time 2:2f : (16.4)
Unfortunately, a transition entirely in the forward-active region is the type of transition typical
of BJT logic gates. In a BJT gate, the LOW logic level is characterized by the saturation region
of the BJT. us, the apparent final steady-state level is not the same as the actual final level. e
BJT collector rise is consistent with a final collector current, Icf D ˇF Ib and the time constant f .
e transition is completed when the collector current reaches its saturation value, Ic.sat/ < ˇF Ib .
A significantly reduced rise time results. Figure 16.4 is a graphical interpretation of the reduction
in rise time.
e rise time can be calculated by determining the 90% and 10% times, t2 and t1 , respectively.
Assume the external circuit parameters define the two currents, Ic.sat/ and Ib1 :
Vcc Vce.sat/
Ic.sat/ D ; (16.5)
Rc
¹e unity gain frequency is defined as the radian frequency at which the common-emitter gain is unity. It is discussed fully
in Section 10.4 (Book 3).
ßFIb
Ic
Saturated Transition Ic(sat)
tr Forward-Active Transition
0
0 τf 2 τf 3 τf 4 τf
2.2 τf
Figure 16.4: Saturated transition rise time.
and
Vi Vbe
Ib1 D : (16.6)
Rb
For a saturated LOW output, define the current ratio, N1 , as:
ˇF Ib1
N1 D : (16.7)
Ic.sat/
N1 is an indicator of the degree in which the BJT has been driven into the saturation region: it is
called the saturation overdrive factor. Values of N1 near unity indicate that the BJT is barely into
the saturation region: larger values indicate a large excess of base current over what is necessary
to saturate the BJT. e time for the collector current to achieve 90% of the saturated collector
current is the solution to the expressions:
t2

0:9Ic.sat/ D N1 Ic.sat/ 1 e f : (16.8)
Similarly, the time to achieve 10% of the saturated collector current is the solution to:
t1

f
0:1Ic.sat/ D N1 Ic.sat/ 1 e : (16.9)
e rise time, tr , is the difference of t2 and t1 :

N1 0:1
tr D t2 t1 D f ln : (16.10)
N1 0:9
As N1 increases the rise time is made smaller. is seems to indicate that a strongly saturated BJT
is desirable in terms of gate speed: other factors will show strong saturation is not desirable.
Delay Time
e delay time indicates the time between the input signal transition and the start of the rise time.
Its primary components² are:
• td1 —the time for minority carriers to transit the base and reach the collector
• td 2 —the time for the collector current to rise to 10% of its final value
Statistical analysis shows that the first of these factors is given by:
F f
td1 D : (16.11)
3 3 ˇF
e second factor is a portion of the exponential collector current change and can be derived in
the same fashion. e 0% to 10% portion of the collector current rise takes place in time:

N1
td 2 D f ln : (16.12)
N1 0:1
e delay time is the sum of these factors.

N1 1
td D td1 C td 2 f ln C : (16.13)
N1 0:1 3 ˇF
Fall Time
e fall time, tf , is analogous to the rise time. It indicates the time for the BJT collector current
to fall from 90% to 10% of its saturated value. is fall in collector current occurs as the transistor
transition in the forward-active region from saturation to cut-off. e expression for fall time is
therefore:
N2 0:9
tf D t4 t3 D f ln : (16.14)
N2 0:1
Here a reverse overdrive factor, N2 , is defined as the ratio of ˇ times the instantaneous base turn-
off current to the saturation collector current:
ˇF Ib2
N2 D ; (16.15)
Ic.sat/
where
Vbe.active/
Ib2 D : (16.16)
Rb
Notice that N2 is a negative quantity. Large magnitude N2 indicates a short fall time.
²Another factor is the time required to charge the base-emitter junction to the cut-in voltage. Here it is assumed that this factor
is small compared to the other delay time factors.
Storage Time
e storage time indicates the time between the input signal transition and the start of the fall
time. Its primary components³ are:
• ts1 —the time for minority carriers to transit the base and reach the collector
• ts2 —the time for the collector current to rise to 10% of its final value
• ts3 —the time to dissipate the excess charge stored in the base of the saturated BJT.
e first two factors are direct analogs of similar components in the delay time:
F f
ts1 D ; (16.17)
3 3 ˇF
and

N2 1
ts2 D f ln : (16.18)
N2 0:9
e third factor, ts3 , is related to an exponential decay of base charge when the BJT is in the
saturation region. is decay has a time constant, s , that is a function of the forward-active
region time constant, f , and its inverse-active region counterpart, r . In most situations these
two time constants are approximately equal and
s f C ˇR .f C r / f C ˇR .f C f / D f .1 C 2ˇR /: (16.19)
is dual dependence is due to the forward biased condition of both the base-emitter and the
base-collector junctions of a saturated BJT. As a consequence, the saturation time constant is
significantly longer than either of the other time constants. e time for base charge dissipation
is given by:

N1 N2
ts3 D s ln : (16.20)
1 N2
e total storage time is given by the sum of the individual components:

f N2 1 N1 N2
ts C f ln C s ln : (16.21)
3 ˇF N2 0:9 1 N2
Large magnitude N2 (a negative quantity) will decrease the storage time. However, large N1 will
significantly increase the storage time. is is especially significant since the storage time constant
is larger than the forward-active region time constant, s > f . If the transistor does not enter
the saturation region (N1 D 1/; ts3 D 0 and the storage time is composed of only the first two
components of Equation (16.21).
³Another factor is the time required to charge the base-emitter junction to the cut-in voltage. Here it is assumed that this factor
is small compared to the other delay time factors.
Summary
While the switching speed of BJT is largely dependent on the physical parameters of the transistor
itself, the surrounding circuit parameters also have significant effect. Rise time and fall time are
strongly dependent on the overdrive factors, N1 and N2 , respectively. In each case, an increase in
the magnitude of the overdrive factor reduces the respective time. Delay time is also decreased
by large N1 as is storage time by large magnitude N2 . Unfortunately storage time can be greatly
increased by large N1 (saturated BJTs). e propagation delay of a TTL inverter can be described
in terms of the transition times derived. Its component terms are:
tr tf
tPHL td C and tPLH ts C : (16.22)
2 2
e average propagation delay is given by:
tPHL C tPLH 1 1
tPD D .td C ts / C tr C tf : (16.23)
2 2 4
16.2 BIPOLAR DIGITAL GATE CIRCUITS

Bipolar logic gates are divided into four fundamental logic gate families: diode-transistor logic
(DTL), transistor-transistor logic (TTL), emitter-coupled logic (ECL), and integrated injection
logic (I2 L). While the original form of DTL is now obsolete, these four families of gates form
the foundation for all modern bipolar logic gates. Advancements in the design of these gates that
have taken place are generally for the purpose of improving gate performance in one or more of
the following areas:
• Speed of operation
• Power consumption
• Noise rejection
• Fan-out
Unfortunately, an improvement in one aspect of gate performance may degrade performance
in another. Good design is a balance of often-conflicting design constraints: modern logic gate
design is an example of the balancing of these constraints. It is the purpose of this section to
explore some of the designs common in digital gates.
e principles of operation of several basic digital logic gates that use bipolar junction tran-
sistors is presented, using quasistatic analysis techniques, in Section 3.5 (Book 1). Power con-
sumption, fan-out, and many aspects of noise rejection can be analyzed using these simple, linear
techniques. Determination of the speed at which a bipolar logic gate operates can be using the
basic techniques presented in Section 16.1. Since TTL found its origins in DTL, modern design
in the two logic families will be discussed together. ECL and I2 L will be discussed separately.
16.2. BIPOLAR DIGITAL GATE CIRCUITS 1113
16.2.1 TTL AND DTL LOGIC GATES
e output voltage levels of a common DTL and TTL logic circuit is developed as the output
BJT switches between two regions of operation: cut-off and saturation. It is these two stable states
that make these families of gates reliable and predictable.
Vcc
◦•
◦•
Ra Rc2 Rc3
◦• ◦• Vo
V1 ◦• Q1 Q2
V2 ◦•
◦• Q3
V3 ◦•
Rb
◦•
Figure 16.5: Basic TTL NAND gate.
e NAND gate forms the fundamental logical unit in both DTL and TTL logic: all other gate
logic operations can be derived from this fundamental unit. e basic circuit topology of a simple
TTL NAND logic gate is shown in Figure 16.5. is gate is typically operated with a supply
voltage of 5 V and consists of several resistors and three BJTs. e input BJT, Q1 , is constructed
with multiple emitters (three emitters are shown: other numbers are common) which serve as the
individual logic inputs to the gate. When any of the logic inputs is a logic LOW, Q1 enters the
saturation region. ere is an insufficiently high voltage at the base of Q2 to forward bias the
base-emitter junctions of Q2 and Q3 , thus Q2 and Q3 are OFF and a logic HIGH output is
produced. A LOW logic output occurs when all inputs are HIGH. When this input condition
occurs, Q1 enters the inverse-active region.⁴ Q2 turns ON and forces Q3 into the saturation
region, production a logic LOW. Depending on exact resistor values and BJT parameters, Q2
typically enters the saturation region, although not as strongly as Q3 . e nominal output logic
levels for this simple, unloaded gate are:⁵
VoH D 5 V and VoL D 0:2 V:
⁴In many situations (large fan-out), the master gate can not supply enough current to sustain the inverse-active region of Q1
in the slave gate. In that case, Q1 is in an inverse saturation state: both junction are forward biased, but the base-collector
junction is more forward biased than the base-emitter junction.
⁵Logic levels, noise margins, and fan-out for this gate are calculated in Section 3.5 (Book 1).
e extremes of the input levels are:
ViH.min/ D 1:8 V and ViL.max/ D 1:1 V:
ese levels result in noise margins of:
NM(HIGH) D VoH ViH.min/ D 5 1:8 3:2 V:

NM(LOW) D ViL.max/ VoL D 1:1 0:2 0:9 V:
While this simple gate topology operates well, it has several properties that are undesirable for
current IC realizations. Most problematic are its relatively high power consumption and low speed
of operation.
e low speed operation of simple TTL and DTL logic gates stems from junction charge
buildup in BJTs that enter the saturation region. As was seen with the simple bipolar inverter,
strongly saturated BJTs exhibit a relatively long storage time. is long storage time slows the
digital transitions necessary in a logic gate. In the TTL NAND gate under analysis, both the
logic LOW and logic HIGH states have BJTs in saturation. A logic LOW implies that Q1 is in
saturation and a logic HIGH, implies that Q2 and Q3 are in saturation.
Each junction must dissipate its stored charge when the gate transitions its output between
logic levels. e speed of the charge dissipation strongly depends upon the évenin resistance
apparent to the junction. It is in this évenin resistance that a conflict between two TTL gate
design goals is most apparent. Any attempt to increase the speed of the gate by reducing the resis-
tance values results in an increase in the gate average power consumption. Similarly, reducing the
average power consumption by increasing the resistor values results in slower gate performance.
With this basic gate topology, power consumption and gate speed can only be simultaneously im-
proved by lowering the supply voltage: unfortunately this action reduces the HIGH noise margin,
NM(HIGH).
Gate performance can be improved in several areas simultaneously only with changes in
the basic topology of the gate. Historically these changes have taken place gradually and have
resulted in a series of TTL gate families. e changes have been centered on two basic design
techniques:
• active charge dissipation, and
• transistor saturation control.
While it is not feasible to extensively discuss each variation of gate topology in this text, a brief
look at several TTL gate alterations is instructive in the study of logic gate speed.
Active Charge Dissipation

In typical TTL gates the output BJT, Q3 , is the most strongly saturated transistor. In addi-
tion, the active elements surrounding Q1 and Q2 provided relatively low-impedance paths for
rapid dissipation of built-up charge. erefore, the greatest benefit is obtained by focusing efforts
at increasing the gate speed about the output transistor. For a LOW output, Q3 is saturated:
both base-emitter and base-collector junctions are forward biased. While the charge build-up
is largest in the base-emitter junction, it is the base-collector junction that must undergo the
greatest change in charge distribution as Q3 switches state from saturation to cut-off. In order to
quickly remove the charge from the base-collector junction, the collector resistor is replaced by a
low-impedance active load, as shown in Figure 16.6. is particular circuit topology is referred to
as an active pull-up or sometimes a “totem-pole” output.
With active pull-up output, the saturated transistor, Q3 , sees a évenin load at the col-
lector consisting of the dynamic resistance of a diode in series with the output resistance of a
common-collector amplifier:
Rc2
Rth rd C :
ˇF 4 C 1
Vcc
◦•
◦•
Rc3
Rc2
Ra ◦• Q4
◦• ◦• Vo
V1 ◦• Q1 Q2
V2 ◦•
◦• Q3
V3 ◦•
Rb
◦•
Figure 16.6: TTL gate with active pull-up.
is apparent resistance is much smaller than that of the collector resistor in the simple TTL
topology while the évenin voltage has not significantly changed. ese changes have the effect
of reducing the overdrive factor, N1 , during discharge:
ˇF I b
N1.discharge/ D ;
Ic.eff /
where

Vcc Vbe.active/ V Vce.sat/
Ic.eff / D > Ic.sat/ :
Rth
e storage time for Q3 is significantly reduced thereby reducing the collector current fall time
and increasing the gate speed. Since the actual value of the collector current at saturation, Ic.sat/ ,
remains essentially unchanged, active pull-up has little effect on the collector current rise time.
Gate operation with active pull-up is much the same as with a resistor as the output collector
load. e input circuitry of the TTL gate remains unchanged, therefore the input logic voltage
levels remain unchanged. e output LOW voltage remains the same at VCE.sat/ 0.2 V: only the
output HIGH voltage changes. For a logic HIGH output, Q2 and Q3 are cut-off. It is assumed
that a load attached to the output of the gate draws some current, thus Q4 is in the forward-active
region. e nominal output voltage level is the source voltage reduced by the voltage drops across
the resistor, Rc2 , the base-emitter junction of Q4 , and the diode:

VoH D Vcc VRc2 C VBE4.on/ C V Vcc 1:5 3:5 V:
e reduction in the nominal output HIGH level decreases the HIGH noise margin,
NM(HIGH):
NM(HIGH) D VoH ViH.min/ D 3:5 1:8 1:7 V:
is form of active pull-up is the output stage found in 74XX/54XX series TTL gates. Added
benefits of this active pull-up circuit topology are a decrease in average power consumption of
10–20% over the simple resistive pull-up configuration and a very slight improvement in fanout.
Both improvements are due to Q4 being in the cut-off region of operation for a LOW output.
Example 16.1
Determine the fan-out of the active pull-up NAND gate shown in Figure 16.6. e pertinent
circuit parameters are:
Vcc D 5 V Ra D 3:9 k Rb D 1:0 k
Rc2 D 1:5 k Rc3 D 130 .
e physical realization is in Silicon with BJT parameters:
ˇF D 50 ˇR D 2:
Solution:
e determination of fan-out is much the same as that of the resistive pull-up circuit (Ex-
ample 3.5 (Book 1)). Fan-out in TTL gates is determined by a master gate with a LOW output
driving a slave gate. e input current for a slave gate with a low input (0.2 V) is found to be:
5:0 0:2 0:8
Iin D D 1:026 mA:
3:9 k
◦• 5 V
3.9 kΩ
Iin
0.2 V◦• Q1
If the master gate is driven by other gates of the same type, it is unreasonable to assume that large
amount of current is entering the emitter of Q1 (it would draw the input voltage below zero). For
fan-out calculations it is safer to assume the worst case scenario where the input current to the
master gate is approximately zero. Under that scenario
IB2 IB1
5 .0:8 C 0:8 C 0:7/
IB2 D 692 A:
3:9 k
5V
◦•
◦• ◦•
130 kΩ
3.9 kΩ 1.5 kΩ
◦•
0.2 V
5 V◦• ◦• ◦• ◦•
(or less) 0.2 V
0.8 V
1 kΩ ◦•
0.8 V
◦•
In this state, there is insufficient voltage between the base of Q4 and the output terminal to
forward bias both the base-emitter junction of Q4 and the diode. erefore, Q4 in the master
gate is OFF. In order to determine the ratio of collector to base currents in the output transistor,
Q3 , the collector current of Q2 must be calculated:
5 0:8 0:2
IC 2 D D 2:667 mA:
1:5 k
e base current of Q3 is therefore:
0:8
IB3 D IB2 C IC 2 D 2:559 mA:
1k
e no-load collector current of Q3 ; IC 3.nl/ , in the master gate is zero due to Q4 being in the
cut-off region: thus the master gate fan-out is determined from the saturation conditions on Q3 :
IC 3 < ˇF IB3 ;
or
IC 3.nl/ C N.Iin / < ˇF IB3 ;
or
0 mA C N.1:026 mA/ < 50.2:559 mA/ ) N < 124:7:
e fan-out of this gate is 124 gates of similar construction. is is an increase of only
one gate over the fan-out for the resistive pull-up gate discussed in Example 2.8 (Book 1)).
Additional changes in the circuit topology can bring further improvements. e circuit of
Figure 16.7 shows two such topological changes. e active pull-up circuit in this TTL NAND
gate realization consists of two BJTs connected as a Darlington pair⁶ rather than the BJT-diode
connection previously discussed. Also shown is an active pull-down circuit connected to the base
of the output transistor, Q3 .
e Darlington active pair pull-up, formed by Q4 and Q5 , presents a very low évenin resistance
to the collector of Q3 and further reduces the saturation overdrive factor, N1 :

1 Rc2 Rc2
Rth Rb4 == :
ˇF 4 C 1 ˇF 5 C 1 .ˇF 4 C 1/ .ˇF 5 C 1/
is Darlington pull-up topology was first commercially seen in the 74HXX/54HXX high-speed
series of TTL gates. e active pull-down circuit also shown in Figure 16.7 is formed by two
resistors, Rb3 and Rb6 , and a transistor, Q6 . e effect of this configuration is to present a low
évenin resistance to the base of Q3 :
Rb6
Rb3th :
ˇF 6 C 1
Lowering the apparent base resistance increases the pull-down base current thereby increasing
the reverse overdrive factor, N2 . Increased reverse overdrive factor lowers both the storage and fall
times for Q3 .
Saturation Control
Any attempt to quickly remove charge stored in the junctions of a saturated transistor by reducing
various évenin resistances has physical limits. e next logical step in improving gate perfor-
mance is centered in limiting the charge build-up by controlling the region of operation of the
⁶Darlington pairs are discussed in Section 6.2 (Book 2).
Vcc◦ ◦•
Rc2 Rc3
Ra
◦•
◦• Q5
◦• Q4
Rb4
◦• ◦• Vo
V1 ◦• Q1 Q2
V2 ◦•
◦• ◦• Q3
V3 ◦•
Rb3
Rb6
Q6
◦•
Figure 16.7: TTL gate with active pull-down and improved pull-up.
transistor. Specifically, if the transistors never enter the saturation region, the component of the
storage time related to the transistor storage time constant, s , will become insignificant. Since
this component can easily be the greatest contributor to slow transition times, gate speed will
be dramatically improved. An exclusion from the saturation region can be accomplished if the
base-collector junction is shunted by a low-V diode that is less subject to charge-storage effects
than the transistor base-collector junction. e diode shunting the base-collector junction will
not allow that junction to become sufficiently forward biased thereby keeping the BJT in the
forward-active region. While a Germanium diode (V 0:3 V) seems ideal for the purpose of
BJT saturation control,⁷ fabrication of Silicon BJTs and Germanium diodes on the same IC chip
is not practical. Schottky-barrier diodes are the ideal alternative.
Schottky-barrier diodes are formed with a metal-semiconductor junction rather than the
usual p-n semiconductor junction. A representation of the metal-semiconductor junction and the
circuit symbol for a Schottky-barrier diode is shown in Figure 16.8. At the junction between a
metal and a semiconductor, the metal acts as a p-type impurity. If the semiconductor is n-type,
the junction acts as a diode. e V-I characteristic of a Schottky-barrier diode is indistinguishable
⁷e shunting of the base-collector junction of a Silicon BJT with a Germanium diode is referred to as Baker clamping a Silicon
transistor.
from that of a p-n junction except that the cut-in voltage, V , is somewhat smaller. Depending on
the doping of the semiconductor and the metal used, V ranges between 0.2 V and 0.5 V with Sil-
icon as the semiconductor. A typical IC realization of a Schottky-barrier diode using Aluminum
results in V 0.4 V. One particular advantage of a Schottky-barrier diode is the extremely small
charge storage time (equivalently, a small junction capacitance) associated with the junction. is
storage time is typically at least an order of magnitude smaller that an equivalently sized p-n
junction.
A K A n-type K
◦• ◦• ◦• metal semiconductor ◦•
Figure 16.8: A Schottky-barrier diode.
Transistors that incorporate a Schottky-barrier diode shunting the base-collector junction

are referred to as Schottky transistors. e circuit symbol for a Schottky npn transistor and a
conceptual IC realization of this transistor are shown in Figure 16.9. e metallic base electrode
bridges the p-type material that is the base and the n-type material that forms the collector allow-
ing it to serve dual purposes: to be the base contact and also to form the base-collector shunting
Schottky diode.⁸
B E C
◦•
•◦ ◦• n+ n+
p substrate
p p
◦•
◦• ◦• n
◦• p substrate
◦•
(a) (b)
Figure 16.9: A Schottky transistor: (a) Circuit symbol; (b) IC realization.
If all saturating transistors in a TTL or DTL gate are replaced by Schottky transistors, the
speed of the gate will be significantly improved. e 74SXX/54SXX series of TTL gates have
the same topology as the gate shown in Figure 16.7 with all BJTs except Q4 replaced by Schottky
transistors (Q4 is not a saturating transistor). Other than reduced BJT storage time, the change to
Schottky transistors has little effect on the performance of the NAND gate. e greatest change
is in the nominal logic levels. e HIGH output level remains unchanged at VoH 3.5 V, but the
LOW level is increased slightly. Since the output transistor, Q3 , no longer saturates with a logic
⁸e collector region of this BJT is shown with both an n and nC region. is process prevents the formation of a Schottky
barrier diode at the metal-semiconductor junction.
LOW output the new low output is given by:
VoL D VBE3.active/ V D 0:7 0:4 0:3 V:
Similarly, the extremes of the input logic levels are given by:
ViH.min/ D VBE3.active/ C VBE2.active/ C .VBE1.active/ V / 1:7 V;
and
ViL.max/ D VBE3.cut-in/ C VBE2.active/ .VBE1.active/ V / 0:9 V:
e change in input and output logic levels also alters the noise margins. e noise margins for a
Schottky TTL gate (74SXX) are given by:
NM(HIGH) D VoH ViH.min/ D 3:5 1:7 1:8 V

Further improvements in IC fabrication techniques have allowed designers to return to a DTL

input to reduce power consumption. e 74LSXX/54LSXX series of low-power Schottky gate
(Figure 16.10) is an example of the return to DTL gate topology with active pull-up and pull-
down improvements.
e return to DTL technology was facilitated by the Schottky transistor, Q2 . Since this
BJT no longer enters the saturation region, it is not necessary to have active elements to speed
the charge dissipation during logic transitions. Q1 was one such active element: it can return to
a DTL topology without significant loss of gate speed. Another common gate design feature is
shown at the inputs terminals of the TTL gate shown in Figure 16.10. e inputs of this series of
gates are protected against transient current surges with a reverse-biased Schottky diode shunting
each input to ground.
Open-Collector Outputs
TTL gates are also available with no internal provision for either active or passive pull-up of the
output transistor. Such a gate is identified as having an open-collector output. e two primary
advantages of an open-collector output are:
• wired-AND operations can be simply created
• simple external loads are easily driven
Open-collector outputs as also useful in driving a simple load such as a LED or a relay. An example
of wired-AND is shown in Figure 16.11. In this circuit, the outputs of two open-collector NAND
gates are connected through an external resistor to positive power. e system output can only go
HIGH if both NAND gate output BJTs are OFF. Since the output BJT OFF state is associated
with a HIGH output, the logical operation is an AND operation on the outputs of the two gates.
V
◦• cc
◦•
Rc2 Rc3
◦•
Ra
◦• Q5
V1 ◦• ◦• ◦• ◦• ◦• ◦• Q4
V2 ◦• ◦• ◦•
Rb4
V3 ◦• ◦• ◦• Q2 ◦• ◦• ◦• Vo
◦• ◦• Q3
Rb3
Rb6
Q6
◦•
Figure 16.10: Low-power Schottky DTL (LS) gate with active pull-up and pull-down.
In order to ensure proper operation of a wired-AND, the external resistor, RL , has a min-
imum value. It must be chosen so that:
VCC VOL.max/
RL > :
IOL.max/ N IIL
e denominator terms are defined as: IOL.max/ is the maximum output current that the output
BJT of a gate can sink (ˇF IB /; NIIL is the current drawn by N gates with a LOW input. Gates
with internal passive pull-up resistors typically violate the constraints on RL and therefore must
not be connected in this manner. If gates with active pull-up are connected in this manner, ex-
cessive power will be dissipated in the output stage of an individual gate leading to gate failure.
Open collector gates, when properly terminated, have passive pull-up: as such they exhibit
relatively long propagation delays compared to gates with active pull-up.
V
◦• cc
◦• ◦•
RL
A ◦• ◦• ◦• (AB)(A’B’)
B ◦•
◦•
open-collector
NANDgate #1
◦•
A’◦• ◦•
B’◦•
open-collector
NANDgate #2
Figure 16.11: Two open-collector NAND gates with outputs forming a wired-AND.
16.2.2 ECL LOGIC GATES

e basic functional topology of all ECL gates is shown in Figure 16.12. All ECL gates use this
basic topology only with variations in the individual components. e current switch is always in
the form of several BJTs sharing a common connection at the emitter terminal. is configuration,
essentially a very high-gain differential amplifier, ensures that the emitter-coupled BJTs never
enter the saturation region: switching is between the forward-active region and cut-off. As such,
ECL gates have a short storage time and are inherently the quickest form of bipolar logic. e
bias network provides stable voltage references and the output driver buffers the output of the
current switch to increase fan-out and match impedance for optimal transmission.
e significant advantages of the ECL gate family over other bipolar logic families include:
• Complementary outputs. Most logic elements offer both the logic function and its com-
plement (i.e., OR/NOR). Additional logic inverters are eliminated from designs reducing
timing delays and power consumption.
• Constant supply current. e current drain remains essentially constant regardless of gate
logic state. e power supply design requirements are therefore simplified.
Logic ◦• ◦• Logic
◦• Current Output
Inputs ◦• Switch Driver ◦• Outputs
Bias
Network
Vcc◦• ◦• ◦• ◦• Vcc
Figure 16.12: Basic ECL gate topology.
• Low switching noise. e differential amplifier and common-collector amplifier switching

sections of ECL logic have very low current transients. In addition, the low voltage variation
in logic states ensures that charging of any stray capacitance results in small current variation.
• Low crosstalk. Crosstalk in digital systems is proportional to the derivative of voltage sig-
nals. Low logic-level voltage differences, as well as greatly reduced BJT storage times, allow
for effective control of signal rise and fall times without significantly slowing gate speed.
Voltage rise and fall rates can be reduced in ECL by a factor of five (or more) over typical
TTL rates.
• High fan-out. e pairing of high input impedance with low output impedance allows for
large fan-out.
e disadvantages are primarily higher power consumption, lower noise margins, and additional
design constraints in the IC environment. ECL is operated with a negative power supply to reduce
the effects of noise and power supply variation on gate output.
e basic operation of an early ECL OR gate⁹ was described in Section 3.5 (Book 1). In
that basic circuit the bias network is an externally supplied reference voltage. Also, the output
common-collector buffer has a pull-down resistor.¹⁰ Later ECL gate families incorporate several
improvements. One series of gates that incorporates the significant changes in ECL topology is
the ECL 10K series. e topology of an ECL 10K OR/NOR gate is shown in Figure 16.13.
e circuit topology of the 10K series differs from the basic gate in several ways:
• Internal bias network. A bias network is included in the IC realization of the gate to provide
a reference voltage to the differential amplifier.
• Ground separation. Two separate ground terminals are provided so that power supply tran-
sients due to switching in the differential amplifier are not passed through the ground to
the output buffers.
⁹e gate described in Section 3.5 (Book 1) has the topology of a MECL I circuit. MECL II has identical topology except
the bias network is included in the IC realization.
¹⁰A pull-down resistor at the emitter of the output BJT ensures that the output will appropriately be pulled LOW.
GND1◦• ◦• ◦• ◦• ◦• ◦• GND2
R1
RC2 RC3 Q6
◦•
◦• Q4
◦• Q5 ◦• A + B (OR)
A ◦• ◦• Q1 B◦• ◦• Q2 Q3 ◦• A + B (NOR)
◦• ◦•
VBB
◦• ◦•
RIN1 RIN2 REP R2 R3
◦• ◦• ◦• ◦• −5.2 V
Inputs Differential Bias Network Output Buffers

Amplifier
Figure 16.13: Basic ECL 10K OR/NOR gate.
• Relocation of pull-down. e relatively low-value, output-emitter, pull-down resistors have

been eliminated and replaced by high-value, resistors on the input BJTs. Benefits include re-
duced power consumption, more reliable gate operation with floating inputs, and increased
gate life.
Logic levels remain unchanged at:
VoH 0:72 V and VoL 1:60 V:
One problem that is common in ECL gates is the variation of the logic levels due to variation
in the power supply voltage or due to temperature changes. Various advanced ECL circuits have
addressed these issues at the expense of circuit complexity. One such advanced circuit topology is
that of the ECL 100K series shown in Figure 16.14. Notice that the increase in power consump-
tion due to added circuitry has been compensated for by a reduction in the power supply voltage
magnitude from 5.2 V to 4.5 V.
16.2.3 I2 L LOGIC GATES

While TTL and ECL circuits are a good choice for small-scale (SSI) and medium-scale (MSI)
integrated circuits, they have limited use in large-scale (LSI) and are not practical for very large-
GND1 ◦• ◦• ◦• ◦• ◦• GND2
RC2 RC3 Q10 R3 R5
RD ◦•
◦• ◦• ◦• ◦• Q4
◦•
R4
A ◦• ◦• Q1 B◦• ◦• Q2 Q3 ◦•
V1
Q8
◦• ◦• Q9 ◦• ◦• A + B (OR)
◦•
V2
R6 R2 ◦• Q11
◦• Q7
◦•
R7
REP Q5 ◦• Q6
R1
◦• ◦• ◦• ◦•
◦• −4.5 V
Inputs Differential Bias Network Output Buffers

Amplifier
Figure 16.14: ECL 100K OR gate.
scale (VLSI) applications. e primary reasons for these limitations on the use of TTL and ECL
circuits are:
• Relatively high power consumption, and
• Relatively large surface area of IC realization.
Integrated injection logic¹¹ (I2 L) blends high speed with high surface area density and low
power consumption. In addition, the simple gate structure of I2 L provides multifunction outputs.
For example, the simple two-input OR/NORgate shown in Figure 16.15 provides four logical
operations as outputs: the complement of each input, AN and BN , and the OR/NOR functions,
A C B and A C B .
¹¹I2 L is also known as merged transistor logic (MTL).

◦• ◦• A + B (NOR)
◦•
Vcc Vcc Vcc
◦• ◦• ◦•
◦•
Io1 Io2 Io3 ◦•
◦• A ◦• B ◦• A + B (OR)
A ◦• ◦• Q1 B ◦• ◦• Q2 ◦• Q3
Figure 16.15: Simple I2 L OR/NOR logic gate.
e basic element of an I2 L gate is a multiple-collector npn BJT driven at the base with
a simple pnp BJT current source (Figure 16.16). e unique feature of this element is its single
input and multiple outputs.
V
◦• cc
Rbias
V
◦• cc
◦• C1
Q2 ◦• C2
Io ◦• C1
◦• C3 ◦• C2
Q1 ◦• C3
A ◦• ◦•
A ◦• ◦• Q1
◦•
(a) (b)
Figure 16.16: Basic I2 L digital gate element: (a) Circuit diagram; (b) Equivalent circuit.
e operation of the basic I2 L element is simple if it is remembered that at least one of the
multiple collector outputs must be connected to the input of another element in a master/slave
pairing. If the master gate input, A, is HIGH, Q1 enters the saturation region and the master
gate output at each of the multiple collectors is VCE.sat/ . If the master gate input is LOW, Q1
enters the cut-off region. e slave gate sees a high impedance input from the master gate. e
current source forces the slave gate Q1 into saturation which, in turn, forces the slave gate input
and the master gate output to VBE.sat/ . All other collectors of the master gate will also be raised
to that voltage level. e output logical voltage levels are therefore:
VoH D VBE.sat/ 0:8 V and VoL D VCE.sat/ 0:2 V:
e input logical levels are the levels at which a BJT can be considered to be ON or OFF:
ViH.min/ D V 0:7 V and ViL.max/ D VBE.on/ 0:6 V:
ese voltage levels are all within 0:6 V with the transition region only 0:1 V wide. Obviously
I2 L gates are not appropriate for use in a noisy environment. e noise margins are:
NM(HIGH) D VoH ViH.min/ D 0:8 0:7 0:1 V

Fan-out considerations are particularly simple to visualize in I2 L gates. A HIGH output

implies no interaction between master and slave gate: there is no limit on the number of slave
gates imposed by a logic HIGH output. For a LOW output, the master gate output BJT must
be in saturation and the slave gate output BJT in cut-off. e slave gate therefore supplies Io to
the collector of the master gate output BJT. e condition for saturation is:
ˇF IB IC ) ˇF Io NIo ) fan-out D ˇF :
It must be noted that the physical structure of the multiple-collector BJT limits the forward
current gain, ˇF . In most cases ˇF for a multiple-collector BJT is much smaller than that of
modern, simple BJTs: consequently, the fan-out of an I2 L gate is typically less than ten gates of
similar construction. If the output to the final gate of a logical operation is to be taken off the chip,
it is necessary to passively pull-up the collector of the output BJT. is can be accomplished with
a resistor connected between any of the output BJT collector terminals and a positive voltage
supply.
e interconnection of the two BJTs that make up an I2 L gate simplifies IC realization
of the gate structure. e p-type base of the current source is directly connected to the p-type
emitter of the inverter: similarly, the n-type collector of the current source connects to the n-type
base of the inverter. ese interconnections lead to shared regions in the IC realization as shown
in Figure 16.16. A single resistor is usually used for all I2 L gates on a chip. A multiple collector
structure can be constructed in a similar fashion to the multiple emitter structure of the input
transistor of TTL gates.
16.3 DYNAMIC PROPERTIES OF METAL OXIDE

SEMICONDUCTOR TRANSISTORS
Metal Oxide Semiconductor (MOS) Digital Logic gates depend on the transition of the output
of a MOSFET from one logic level to another. As in bipolar transitions, the speed at which
16.3. DYNAMIC PROPERTIES OF METAL OXIDE SEMICONDUCTOR TRANSISTORS 1129
V cc◦•
R bias A C1 C2 C3
n+ n+ n+
p pp
n
n+ substrate
Figure 16.17: IC realization of an I2 L gate with three collectors.
any gate operates is limited by the physical parameters of its constituent transistors and of the
components in the circuit surrounding the transistor. While it is impossible to analyze the effect
of all possible circuit topologies on switching speed, an analysis of the switching speed the simple
CMOS inverter provides much insight into all MOS switching.¹² As shown in Figure 16.18, a
general CMOS inverter consists of two complementary MOS transistors: the input to the inverter
is at the connection of the two FET gate terminals and the output is at the connection of the
drain terminals. Here it is assumed that the master inverter shown drives a similar-topology slave
inverter. is slave inverter is represented by its input impedance: a capacitor in parallel with a
very large resistance. As the input resistance of a FET is essentially infinite, it is assumed to have
no significant effect on any further calculations.
V• DD
◦
Q2
Load
Vin◦• ◦• ◦• ◦• ◦• ◦• ◦•Vo
Q1 CL
Figure 16.18: Typical CMOS inverter, capacitively loaded.
e response of the CMOS inverter to a logic LOW to HIGH input transition is shown in
Figure 16.19. For a CMOS inverter these logic levels are:
ViL 0 V and ViH VDD :

¹²is digital CMOS inverter is initially discussed in Section 3.4 (Book 1).
VDD
Vin
V(0)
Q1Sat
Vo
Q1Ohmic
V(0)
t0 t1 t2
Figure 16.19: Transient response of a CMOS inverter.
As in the case of a bipolar inverter, the digital transition can not be instantaneous and must
experience some delay. Due to the symmetry of the CMOS circuit, the mathematical expressions
for the rise and fall time will be functionally identical. e rise and fall times themselves will
vary with the transistor characteristic. Specifically, the rise and fall times are dependent on the
n-channel and p-channel FET transconductance parameters, Kn and Kp , respectively, as well as
the respective threshold voltages.
e response to a digital step consists of regions of constancy and a region of transition. In
the region of transition there are two significant time periods.
• Delay Time D td D t1 t0
• Rise Time D tr D t2 t1
e delay time is the time between the input pulse transition and when the response transitions
10% of the distance between HIGH and LOW states. e rise time is the time for a 10% to
90% transition from HIGH to LOW. e term rise time is used to match the definitions in
bipolar circuitry. In NMOS gate circuits, it refers to the FET drain current change: as the voltage
transitions from a HIGH to LOW, the drain current rises from a minimum to a maximum value.
It is a misnomer for CMOS circuits: the drain current is zero for both logic states.
During the delay time .to t < t1 /, the n-channel MOSFET is in the saturation region
of operation and is described by the voltage-current relationship:¹³
ID D K.VGS VT /2 : (16.24)
Since the input voltage to the inverter is a constant value .Vin D VDD ) during this time period, it
can be seen through Equation (16.24), that the drain current is constant during the delay time.
¹³e voltage-current relationships for FETs of all types are presented in Table 4.2 (Book 1).
e load capacitance can therefor be assumed to discharge linearly:
CL Vo
ID t D CL Vo ) td D : (16.25)
ID
e change in the output voltage, Vo , is 10% of the supply voltage: Vo D 0:1VDD . e total
delay time can therefore be easily computed:
0:1 CL VDD
td D : (16.26)
K . VDD VT /2
e rise time has two components:
tr D tr1 C tr2 ; (16.27)
where tr1 is the portion of the rise time where Q1 is in the saturation region and tr2 is the portion
where Q1 is in the ohmic region. e transition between the saturation and ohmic regions of a
enhancement region MOSFET occurs when:
VDS D VGS VT ) Vo D VDD VT : (16.28)
As during the delay time, the drain current is constant for a saturation region FET and the load
capacitor discharges linearly during tr1 :
CL Vo
tr1 D ; (16.29)
ID
or
CL ..VDD VT / 0:9VDD / CL .VT 0:1 VDD /
tr1 D 2
D : (16.30)
K .VDD VT / K.VDD VT /2
During the second portion of the rise time, Q1 is in the ohmic region and can be described by
the expression:
2

ID D K 2 .VGS VT / VDS VDS : (16.31)
e load capacitor discharge is described by the differential form of its voltage-current relation-
ship:
d Vo
ID D CL : (16.32)
dt
Simultaneously solving Equations (16.31) and (16.32) leads to an integral expression for tr2 :
Z 0:1VDD
CL d Vo
tr2 D 2 : (16.33)
2K .VDD VT / VDD VT Vo
Vo
2 .VDD VT /
Evaluation of the integral gives the expression for the second portion of the rise time:

CL VDD VT
tr2 D ln 20 1 : (16.34)
2K .VDD VT / VDD
e total rise time for the CMOS inverter is the sum of the rise time components:

CL .VT 0:1VDD / 1 VDD VT
tr D C ln 20 1 : (16.35)
K .VDD VT / .VDD VT / 2 VDD
A comparison of the expressions for delay time (Equation (16.26)) and the rise time (Equa-
tion (16.13)) shows that the rise time dominates the delays inherent in digital CMOS switching.
In addition, both the rise time and the delay time are directly proportional to the capacitance of
the load. is dependence on load capacitance is the determining factor in MOS gate fan-out.
When many slave gates are connected to the output of a single master gate, the input capacitance
of the slave gates add. e rise and delay times increase directly in proportion to the number of
slave gates attached to the output of the master gate. Transition speed requirements put an upper
limit on this number.
As with the bipolar inverter, propagation delay is a useful descriptor of the gate speed. e
propagation delay of a CMOS inverter can be described in terms of the transition times derived.
Its component terms are:
tr
tPHL td C (n-channel FET parameters): (16.36)
2
e LOW to HIGH propagation time has the same mathematical form but the transconductance
parameter of the p-channel FET must be used.
tr
tPLH td C (p-channel FET parameters): (16.37)
2
e average propagation time is given by:
tP D 1=2.tPHL C tPLH /: (16.38)
Example 16.2
A CMOS inverter is fabricated using a 5 V supply and MOSFETs with the following properties:
KN D 0:1 mA=V2 (n-channel) jVT j D 1

2
KP D 0:25 mA=V (p-channel):
Determine the average propagation delay time if it is driving a capacitive load of 5 pF.
Solution:
Equation (16.26) yields the delay times:
12
0:1CL VDD 0:156 10
td D D :
K.VDD VT /2 K
e HIGH to LOW transition uses KN while the LOW to HIGH transition uses KP
tdHL D 1:56 ns tdLH D 0:625 ns:
Similarly, the rise times can be calculated from Equation (16.35):
1:849 10 12
tr D
K
trHL D 18:49 ns trLH D 7:40 ns:
e individual propagation delays are given by
tPHL tdHL C 1=2trHL D 10:81 ns
tPLH tdLH C 1=2trLH D 4:32 ns:
e average propagation delay is the average of the individual propagation delays:
tP D 1=2.tPHL C tPLH / 7:56 ns:
An NMOS inverter is similar to a CMOS inverter but fabricated with an n-channel active
load rather than the p-channel switch. Transition time calculations are similar to those described
for the CMOS inverter, with the exception that the switching transistor, Q1 , is always in the
ohmic region. e expansion of NMOS inverter calculations to cover NMOS gates is complicated
further due to the dependence of the LOW output voltage, VoL , on the exact state of the multiple
switching transistors inherent to MOS gates. CMOS and NMOS gates operate at essentially the
same speed if comparable FETs are used.
FET Latch-up
e IC realization of MOS gate structures produces, in addition to the MOS structures, para-
sitic bipolar structures. While the npn and pnp structures that produce parasitic BJTs are usu-
ally benign, pnpn structures can produce a parasitic silicon-controlled rectifier (SCR).¹⁴ An SCR
is a form of latching switch that is activated by the proper injection of a small current or by a
high-derivative voltage pulse. Once the SCR structure is activated, the high currents that result,
combined with the latching property of the SCR, lead to catastrophic failure of the MOS device.
Modern IC design of MOS structures includes transient protection structures so that the possi-
bility of parasitic SCR latch-up is minimized in all but the noisiest of environments. Still, MOS
ICs are particularly sensitive to damage by static discharge.
¹⁴SCRs are discussed extensively in Section 14.1.
V• DD
◦ V in
◦•
V in V DD
◦• ◦•
Vin◦• ◦• ◦• ◦• Vo ◦• ◦• ◦•
p+ n+ n+ p+ p+ n+
p p
n substrate
Figure 16.20: CMOS inverter and conceptual IC realization.
16.4 MOS DIGITAL GATE CIRCUITS

e two basic logic operations in MOS gates are NAND and NOR. In order to create these
logic operations, MOSFETs are used essentially as switches. e two logic operations can be
conceptualized (Figure 16.21) as a resistive load in series with either a series connection of several
switches to ground (NAND) or a parallel connection of several switches to ground (NOR). In the
NAND configuration, the output will be LOW only if both of the series switches are closed: in
the NOR configuration, the output is LOW if either of the parallel switches is closed. In MOS
realizations of such logic gates, the FET can be used for all components of the gate: the switches
as well as the active resistive loads. e extremely low current draw at the controlling terminal of
a FET switch, the gate terminal, facilitates cascading these simple logic gates without many of
the problems caused by loading.
MOS logic gate circuits can be constructed using MOS transistors of the same type or
transistors of mixed types. NMOS circuits use n-channel FETs exclusively, albeit often with a
mix of depletion and enhancement mode FETs. PMOS is the complementary form of NMOS
using p-channel FETs only. CMOS (complementary MOS) uses a mixture of complementary,
enhancement mode, n-channel and p-channel FETs. Of these three types, NMOS and CMOS
are the most common: discussion here is restricted to the fundamental gates common to NMOS
and CMOS logic.
NMOS Gates
NMOS gates are used extensively in LSI and VLSI microprocessors, memories, and other cir-
cuitry, but are not commonly available as individually packaged circuits. All elements of basic
NMOS logic gates are fabricated from n-channel FETs: the switches are enhancement-mode
NMOS FETs and the active resistive load can be either an enhancement mode or depletion-
mode NMOS FET. e logic gate action is essentially the same for each type of active load: for
simplicity, discussion here will be limited to enhancement type active loads. e circuit diagrams
16.4. MOS DIGITAL GATE CIRCUITS 1135
◦• V
◦• V
◦• ◦• AB
◦• ◦• ◦• A + B
A
◦•
A B
◦• ◦•
B ◦• ◦•
(a) (b)
Figure 16.21: Two-input logic gates using simple controlled switches: (a) NAND; (b) NOR.
for basic, two-input NMOS NAND and NOR gates, using enhancement mode active loads, are
shown in Figure 16.22. It should be noted that the geometry of all the switching FETs is identical,
but the active load FET usually has different characterizing parameters.
V DD
◦•
◦•
V DD
◦•
◦•
◦• ◦• AB
A ◦•
A ◦•
◦• ◦• A + B
B◦•
B ◦•
◦•
(a) (b)
Figure 16.22: Two input NMOS logic gates (enhancement mode active load): (a) NAND; (b) NOR.
While the fundamentals of NMOS gate operation are fairly easily understood, the specifics
can be more complicated. Analysis of a NOR gate is mathematically the least complicated: dis-
cussion will begin with the NOR gate and the progress to the NAND gate. e short-circuit
connection between the drain and gate terminals of the active load ensures that the load FET is
always in the saturation region of operation: VGS D VDS . e equation that relates the load FET
drain current to its gate-source voltage is found in Table 4.2 (Book 1):
IDR D KR .VGSR VT /2 : (16.39)
An additional subscript is added to the FET parameters to specify the FET under consideration:
“R” indicates the active resistive load and “S” indicates the switching FETs.¹⁵
In a two-input NOR gate, two LOW inputs produce simple results. For the switching
FETs, VGS < VT implies that the drain current, IDS , is zero valued. Consequently, the drain cur-
rent of the load FET must be zero valued. Substitution into Equation (16.39) yields:
0 D KR .VGSR VT /2 ) VGSR D VT : (16.40)
e output of the gate goes to a HIGH state, VoH :
VoH D VDD VGSR D VDD VT : (16.41)
One or more HIGH inputs to the NOR gate implies that some current flows through the FETs.
Any switching FET with a HIGH input is forced into the ohmic region. Solving for currents
and voltages requires the use of additional FET characteristic equations. e current charac-
teristic equation for enhancement mode FETs operating in the ohmic region is also found in
Table 4.2 (Book 1):
2

IDS D KS 2 .VGSS VT / VDSS VDSS : (16.42)
Since there exists the possibility for N switching FETs to be simultaneously ON, the relationship
between switch and load drain currents is given by:
IDR D NIDS ; (16.43)
or

KR .VGSR VT /2 D N KS 2 .VGSS VT / VDSS 2
VDSS : (16.44)
Kirchhoff ’s laws relate VGSR to VDSS :
VGSR D VDD VDSS : (16.45)
Equation (16.44) becomes a quadratic equation in the LOW output voltage level, VoL D VDSS :
as a function of the number of HIGH inputs, N , the voltage supply, VDD , the FET threshold
voltage, VT , the FET transconductance factors, KR and KS , and the input voltage, VGSS :

KR .VDD VDSS VT /2 D N KS 2 .VGSS VT / VDSS VDSS 2
: (16.46)
¹⁵It is assumed in this discussion that the threshold voltage, VT , is the same for all FETs in the circuit. In IC fabrication this
is a realistic design assumption.
e quadratic functional form of Equation (16.46) obscures intuition. Of most significance is a
decrease in the output voltage, VDSS , as NKS =KR increases. For most designs, it is important to
set a maximum value on this LOW output. e maximum value will occur for only one switch
ON .N D 1/. A particular design goal will the restrict the minimum ratio of transconductance
factors, KS =KR . e usual implication of this restriction is switching FETs that are significantly
wider than the load FET.

Given a 5 V power supply. Design a three-input NOR gate to have the following output logic
levels when driven by a gate of the same design:
VoH D 3:8 V VoL.max/ D 0:9 V:
Solution:
An NMOS circuit topology similar to Figure 16.22b but with three inputs and three switch-
ing FETs will satisfy the design requirements. All that remains to be determined is an acceptable
set of FET parameters, VT ; KR and KS .
V DD
◦•
A ◦• ◦•
B◦•
◦• ◦• ◦•
C◦•
◦• ◦•
e HIGH output level is given by Equation (16.41):
VoH D VDD VT ;
or
3:8 D 5 VT ) VT D 1:2 V:
e maximum LOW output level is determined with only one switching FET on. For this con-
dition the input voltage VGSS D VoH and the output voltage VDSS D VoL.max/ :
KR .5 0:9 1:2/2 D 1KS Œ2.3:8 1:2/.0:9/ .0:9/2 ;
or
KR D 0:460KS or more exactly KR 0:460KS :

In order to keep drain currents reasonable, the value of the transconductance factors must be kept
reasonably small. Since there are no specific design constraints on FET transconductance factors,
a drain current of approximately 1.93 mA will result in:
KR D 230 A=V2 and KS D 500 A=V2 :
Other similar values will produce acceptable results. e LOW output logic level can be found to
be: 0.9 V for a single HIGH input, 0.527 V for 2 HIGH inputs, and 0.373 V for 3 HIGH inputs.
e analysis of an NMOS NAND gate is similar to that of the NOR gate but complicated by the
series connection of the switching FETs. e HIGH output voltage is determined in the same
manner as for a NOR gate and produces the same result:
VoH D VDD VT : (16.47)
e series connection of switching FETs adds complexity to the LOW output voltage calculation.
While the gate-source voltage, VGS1S , of the grounded-source FET is simply the input voltage,
subsequent switching FETs have VGS reduced by the drain-source voltages of any intervening
FETs. In the two-input NAND gate circuit of Figure 16.22a, the upper switching FET has a
gate-source voltage (assuming the gate is driven by a similar gate):
VGS2S D Vin VDS1S D VDD VT VDS1S ; (16.48)
while the grounded-source switching FET has gate-source voltage:
VGS1S D Vin D VDD VT : (16.49)
Of course the NAND gate output voltage for a logic LOW is given by the sum of the switching
FET drain-source voltages:
N
X
VoL D VDS iS D VDS1S C VDS2S ; (16.50)
iD1
where N is the number of series switching FETs. e series connection of N identical switching
FETs creates N equations relating the drain currents:

KR .VDD VoL VT /2 D KS 2 .VGSiS VT / VDiSS VDiSS 2
(16.51)
i D 1; 2; : : : ; N:
e simultaneous solution of Equations (16.48) and (16.49) determines the LOW output voltage
level.
Given a 5 V power supply. Design a three-input NAND gate to have the following output logic
levels when driven by a gate of the same design:
V DD
◦•
◦•
◦• ◦•
A ◦•
B◦•
C◦•
Solution:
An NMOS circuit topology similar to Figure 16.22a but with three inputs and three switch-
ing FETs will satisfy the design requirements. All that remains to be determined is an acceptable
set of FET parameters, VT ; KR and KS .
e HIGH output level is given by Equation (16.41)
VoH D VDD VT ;
or
3:8 D 5 VT ) VT D 1:2 V:
e maximum LOW output level is determined by simultaneously solving Equations (16.50)
and (16.51) (four total equations):
0:5 D VDS1S C VDS2S C VDS3S
KR .VoL 1:2/2 D 1KS Œ2.3:8 1:2/.VDS1S / .VDS1S /2
KR .VoL 1:2/2 D 1KS Œ2.3:8 1:2 VDS1S /.VDS2S / .VDS2S /2 ;
and
KR .VoL 1:2/2 D 1KS Œ2.3:8 1:2 VDS1S VDS2S /.VDS3S / .VDS3S /2 :
ere are no easy, closed-form techniques for solving 4 non-linear, simultaneous equations. A
MathCAD solution to find the ratio of the transconductance factors follows:
MathCAD Solution for the ratio of FET transconductance factors for three input NAND gate
VT := 1.2 VoL := 0.5
Guess values for the ratio and the three drain-source voltages
ratio := 1 V1 := .2 V2 := .2 V3 := .3
Given
V1 + V2 + V3 = VoL (VoL − VT)2 = ratio [2 ∙ (3.8 − 1.2 – V1) ∙ V2 − V22]
(VoL − VT)2 + ratio [2 ∙ (3.8 − 1.2) V1 − V12] (VoL − VT)2 = ratio [2 ∙ (3.8 − 1.2 – V1 – V2) ∙ V3 − V32]
0.155
Find (V1, V2, V3, ratio) = 0.166
0.179
0.626
e minimum ratio of transconductance factors for a 0.5 V LOW output voltage is therefore:
KS
0:626:
KR
Choosing the same load FET KR as Example 16.3, implies that the NAND gate will draw the
same power for a LOW output as the NOR gate in that example. is design choice leads to:
KR D 230 A=V2 and KS 144 A=V2 :
Choosing the same switch FET KS as Example 16.3 reduces the output LOW voltage to VoL
0.25 V, and greatly simplifies IC layout. For these reasons, a reasonable choice might be:
KS D 500 A=V2 :
Other choices will fulfill the design goals adequately. For example, identical FETs results in VoL
0.4 V.
As was previously stated, the active load for an NMOS gate can be either an enhancement
mode or depletion mode FET. When NMOS gates use a depletion-mode load, the gate and
source terminals of the active load are shorted together: this connection ensures that the depletion-
mode load is always in the saturation region of operation. In the depletion-mode case, the IC
fabrication procedures are more complex but typically lead to faster switching speeds. Analysis
techniques, while not discussed here, are similar to those of the enhancement-mode active load
case.
Rather than switches mixed with active, resistive loads, it is possible to produce NAND
and NOR logic operations using only controlled switches. In this type of realization, the resistive
load is replaced by a group of oppositely controlled switches. As shown in Figure 16.23, each input
simultaneously produces an action on one of the positively controlled switches and the opposite
action on its counterpart in the negatively controlled switches. CMOS logic gates are founded on
this realization of logical switching.
◦• V ◦• V
◦• ◦•
Negatively A
A Controlled ◦•
B
◦• ◦• Switches
B
AB ◦• ◦• ◦• ◦•
◦• ◦• ◦• ◦• A + B
A Positively
◦• Controlled A B
Switches ◦• ◦•
B
◦• ◦• ◦•
(a) (b)
Figure 16.23: Conceptual switch-only two-input logic gates: (a) NAND; (b) NOR.
CMOS Gates
CMOS logic gates are available in SSI packages and are found in many LSI and VLSI applications
such as calculators and watches. e very popular 74HCXX series of logic gates is an example
of SSI CMOS logic. As the physical scale of IC circuit realization becomes smaller, CMOS is
becoming the most significant form of MOS gate in VLSI applications. Part of this rise in CMOS
circuitry is due to its very low power consumption.
In standard CMOS each input is connected to an individual NMOS FET and a PMOS
FET. e complementary channel FETs act as opposite-acting switches with this connection.
A logic HIGH signal closes the NMOS switch and opens the PMOS switch: a LOW signal
produces the reverse actions. An example of this dual connection, a two-input NAND gate, is
shown in Figure 16.24a. is NAND gate consists of two NMOS transistors in series connected
to two PMOS transistors in parallel. Whenever an input turns one of the NMOS FETs ON, the
corresponding PMOS FET is turned OFF (i.e., Qn1 ON implies Qp1 OFF). us, the output
is switched to its LOW state only if both NMOS transistors are ON (both inputs HIGH), but
connected to VDD when either PMOS in ON (either input LOW). is is the ideal form for
a NAND gate. A two-input NOR gate is the exact dual structure of the NAND gate: there
are two parallel NMOS FETs transistors connected to two series PMOS FETs, as shown in
Figure 16.24b. Each additional input adds two FETs: one of each type connected in series or
parallel, as appropriate, to its matching-type FETs.
V V DD
◦•
DD ◦•
◦•
Qp1 Qp2 A ◦• ◦• Qp1
◦• ◦• AB
Qn2 B◦• ◦• Qp2
A ◦• ◦•
◦• ◦• A + B
B◦• ◦• Qn1 Qn1 Qn2
◦•
(a) (b)
Figure 16.24: Two input CMOS logic gates: (a) NAND; (b) NOR.
CMOS gates are characterized by very stable logic voltage levels. Each FET switches be-
tween cut-off and ohmic regions operation. In the cut-off region of operation, no drain current
flows through the FET. In the CMOS gate, ohmic region FETs are, in all stable states, in se-
ries with a cut-off FET (or combinations of cut-off FETs) and must also have no drain current.
Consequently, CMOS gates consume power only during the switching transient. During this
transient, a short-duration current pulse flow through the FETs, leading to low total power con-
sumption. Unfortunately, it also generates significant electrical noise.
e transfer characteristic of a CMOS gate can be approached by analyzing the states of
the individual FETs. An ohmic region FETs is described by:
2

ID D KS 2 .VGS VT / VDS VDS : (16.52)
If the drain current must be zero-valued, the implication of this simple application of Kirchhoff ’s
current law is:
VDS D 0:
e logic voltage levels of a CMOS gate are therefore limited by the supply voltage and ground:
VoH D VDD and VoL D 0:
e voltage at which the logic transitions occur is not easily characterized for CMOS gate
circuits. It is a function of the p-channel and n-channel FET transconductance factors, KP and
KN , as well as which inputs are in transition. A typical transfer relationship for a two-input
CMOS NAND gate is shown in Figure 16.25. When only input A is in transition, the transition
occurs at the lowest voltage: only B in transition occurs at a slightly higher input voltage. When
both inputs are simultaneously in transition, the transition occurs at its highest voltage level.
Vo
VDD
B only
A & B together
A only
0 Vin
VDD
Figure 16.25: Two-input CMOS NAND gate transfer relationship.
e spread in the transition region can be investigated by observing the midpoint of the
output voltage transition (Vo D 1=2VDD ) for the two extreme cases. For simplicity of discussion,
assume the output is in transition from logic LOW to HIGH.
For a logic LOW, both inputs to a NAND gate are high and the FETs are in the following regions
of operation:
• Qn1 and Qn2 in ohmic region
• Qp1 and Qp2 in cut-off
e lowest voltage transition occurs when the input voltage, Vin , is connected to terminal A. At
the midpoint of the transition for this case, Qn2 and Qp2 enter the saturation region while the
two other FETs remain in their previous states. e currents through the FETs are:
IDp2 D Kp .Vin VDD C VT /2 (16.53)

2
IDn2 D Kn .Vin VDS1 VT / (16.54)
2
IDn1 D Kn f2.VDD VT /VDS1 .VDS1 / g: (16.55)
Simultaneous solution of these three equations, knowing that the currents must have the same
magnitude, leads to the value of the input voltage, Vin , at which the transition occurs. If both
inputs transition at the same time, Qp1 is also in the saturation region at the midpoint of the
transition. is difference in FET state leads to an increased n-channel drain current since both
p-channel FETs are contributing to the total current.
As with NMOS gates, CMOS gates are optimized for size and speed as well as voltage
levels. Often these design goals lead to differently characterized (and sized) n-channel and p-
channel FETs.
Example 16.5
Determine the range of input voltages at which the midpoint of a logic transition occurs for a
two-input CMOS NAND gate that uses FETs described by:
jVT j D 1 V and Kn =Kp D 2;
and a 5 V power supply.

Solution:
e midpoint of the logic transition is found by the simultaneous solution of Equa-
tions (16.53) through (16.55). ere are actually three input voltages at which the midpoint of
the transition occurs: each depends on which input is in transition. Simultaneous solution of sev-
eral non-linear equations is best accomplished numerically. A MathCAD solution for two cases
(input A only and both A and B) is shown at the right. e simultaneous change is described by
noting that both p-channel FETs have the same terminal voltages applied.
Two-input CMOS NAND gate transition solutiom

Vdd := 5 Vt := 1
Kn := 2 Kp := 1
Guess Values
Vin := 2 Vds := .1
Given (Solve Block)

(Vin − Vds1 − Vt)2 = 2 ∙ (Vdd − Vt) ∙ Vds1 − Vds12
Kn ∙ (Vin − Vds1 − Vt)2 = N ∙ Kp ∙ (Vin − Vdd + Vt)2
“N” indicated the number of p-channel FETs in saturation
Ans (N) := find (Vin, Vds1)
N := 1 ..2
Ans (N)0 Ans (N)1
2.345 0.175
2.622 0.245
16.5. BISTABLE LOGIC CIRCUITS 1145
e lowest single input transition midpoint occurs at an input voltage of 2.345 V while
the simultaneous double transition occurs at an input voltage of 2.622 V. Slight alteration of the
program to model a single transition of input B (Equations (16.54) and (16.55) need slight mod-
ification) results in an input transition voltage of 2.388 V.
Transmission Gates
A transmission gate has an output signal that duplicates its input signal when a third signal, the
ENABLE signal, is present. When the ENABLE signal is in its other state (often called the IN-
HIBIT state) the transmission gate is opened. A very simple CMOS realization of a transmission
gate is shown in Figure 16.26. e transmission path is A to C, and the ENABLE/INHIBIT
signal is applied with opposite polarity to the two MOSFET gate terminals. Digital transmission
gates are very similar the parallel CMOS analog switch discussed in Section 4.5 (Book 1), but
optimized for single-direction transmission.
Transmission gates are often used with a clock signal entering the ENABLEterminal. As
such, the transmission gate serves to gate signal on or off. ese gates are commonly found in
multiplexers and other digital devices requiring signal switching.
−
B B A C
A ◦• ◦• ◦• C 0 1 0 open
0 1 1 open
1 0 0 0
−
B ◦• ◦• B 1 0 1 1
(a) (b)
Figure 16.26: CMOS digital transmission gate: (a) Simplified circuit diagram; (b) Truth table.
16.5 BISTABLE LOGIC CIRCUITS

Electronic circuits constructed in such a manner so that two distinct, stable output states exist
are commonly identified with the term bistable. Bistable logic circuits perform many important
functions in digital circuitry. Level latches, counters, shift registers, and memories all depend on
bistable circuitry. e most significant property of a bistable circuit is its ability to maintain a
given stable output until an external input is applied. Application of an appropriate external input
will cause a bistable circuit to change state in a predictable manner: the bistable circuit then holds
the new output state until another appropriate input is applied. e most significant examples of
bistable circuits are:
• Latches
• Flip-flops
• Schmitt Triggers
A latch is the simplest form of bistable circuit. is circuit “latches” its output to be the same
logic level as its last valid input. e latch then holds the output at the logic level until another
valid input forces a change in the latch state. As such, the latch is a very simple form of memory
circuit. Latches are especially significant on shared data busses where values must be held while the
buss transmits other data. Flip-flops are typically derived from latches. Most significant among
the changes is the requirement that a clock pulse be present in order for a flip-flop to switch
states. While many latches have an indeterminate output state, the output of a flip-flop is always
determinate. e output of a flip-flop depends not only on the inputs but also on the current
state of its output: in that sense, it also is a form of memory circuit. e Schmitt trigger finds
greatest use in speeding the rise and fall times of digital signals that, for various reasons, have
level transitions that are too slow for accurate logical manipulations. It is characterized by an
input/output characteristic displaying hysteresis.
Detailed presentation of bistable circuitry is beyond the scope of this discussion. Only a
few common circuits are presented for demonstration of the principles.
e SR Latch
e set-reset (SR) latch is a very common form of single-bit retention circuit. e SR latch is
formed by cross-coupling the outputs of a pair of NOR gates into the inputs of the opposite
member of the pair as shown in Figure 16.27. e output, Q, of the latch transitions to match
the S input when only one input is HIGH. When both inputs are LOWthe latch retains its last
value of Q and holds it until at least one input transitions to HIGH. e terms set and reset refer
to the action of the output, Q. Q sets (transitions to HIGH) when the set input, S , is HIGH:
Q resets (transitions to LOW) when the reset input, R, is HIGH. Unfortunately the simple SR
latch has a state that must be avoided: when both inputs are HIGH the output is indeterminate.
A common realization of an SR latch using two NOR gates is shown in CMOS form is
Figure 16.28.
Other IC gate families may use a different realization of the latch. In particular, it is more
efficient in I2 L gate realizations to use a NAND form of the SR latch (Figure 16.29). is NAND
realization produces the same logic characteristic as the NOR realization.
e JK Flip-Flop
Flip-flops are an augmentation of a basic latch¹⁶ that removes the indeterminate state present
when both inputs are HIGH. One common flip-flop is the JK flip-flop, logically realized in
¹⁶Terminology has not been effectively standardized for bistable circuitry. Many sources prefer to consider the SR latch a prim-
itive form of flip-flop, however IC terminology usually reserves the term for the more complex circuitry.
R◦•
NOR ◦• ◦• Q
S R Q
0 0 Q
0 1 0
−
NOR ◦• ◦• Q 1 0 1
S ◦• 1 1 −
(a) (b)
Figure 16.27: Basic SR latch: (a) Logic diagram; (b) Characteristic table.
V DD
◦•
◦•
Q Q
◦• ◦•
◦• ◦• ◦• ◦•
◦• ◦•
S ◦• ◦• ◦• ◦• ◦• ◦• R
Figure 16.28: CMOS SR latch (NOR realization).
Figure 16.30a. e addition of two three-input AND gates and an addition feedback path removes
the ambiguity in the logic table so that if both inputs are HIGH the output, Q, inverts. e
addition of a clock signal avoids many of the problems associated with noisy input signals.
A JK flip-flop will only transition between states during the presence of a clock pulse. Dur-
ing that clock pulse the inputs and outputs are combined to form the logic table of Figure 16.30b.
is table is the same as for a SR latch with the single exception that two HIGH inputs toggle
the output to its complement in a JK flip-flop where that state resulted in an indeterminate state
in the SR latch.
V• cc V
◦ ◦• cc
Io Io ◦• Q
S ◦• ◦• Q1 ◦• ◦• Q1
◦•Vcc ◦• Vcc
Io Io
◦• ◦• Q
R ◦• ◦• Q1 ◦• Q1
Figure 16.29: I2 L SR latch (NAND realization).
A characteristic of all JK flip-flops is that the output will toggle (change to the opposite
state) when clocked in the presence of a HIGH signal at both inputs. Operated in that mode the
circuit becomes a T flip-flop and is particularly useful in digital counters.
J ◦•
AND S Q ◦• ◦•
Clock ◦• ◦•
J K Q
0 0 Q
AND R Q ◦• ◦• 0 1 0
K ◦• 1 0 1
1 1 Q
(a) (b)
Figure 16.30: Basic JK flip-flop: (a) Logic diagram; (b) Characteristic table.
Since latches and flip-flops have standard logic gates as basic functional components, they
are subject to many of the same speed restrictions: gates with short delay times lead to fast latches
or flip-flops. Typically, the speed of a latch or flip-flop is specified through the maximum clock
frequency. e maximum clock frequency is simply the highest rate at which the clock input of a
bistable circuit can be driven while maintaining proper operation. Other significant operational
parameters for these circuits are:
• Setup and Hold times: It is necessary that the input data arrive a short time before the trig-
gering edge of the clock pulse and remain a short time after: these times are the setup time
and hold time, respectively.
• Clock HIGH and LOW pulse widths: e minimum time that the clock must remain in its
HIGH and LOW states for proper gate operation.
e Schmitt Trigger
e output of a Schmitt trigger is bistable and has very steep transition regions. e characterizing
feature of the Schmitt trigger transfer function is the presence two separate transition regions, one
for positive slope and one for negative slope signals, separated by a deadband region. e resultant
transfer relationship exhibits hysteresis as shown in Figure 16.31. Any input signal below the
negative slope transition voltage, VT , results in a LOW output, VL . If the output state is LOW,
it will not transition to the HIGH state unless the input is greater than the positive slope transition
voltage, VTC . Similarly, any input above VTC results in a HIGH output, VH , that will not transition
to the LOW state unless the input falls below VT . us, signals, after crossing a threshold, do
not respond to input signal changes unless the variation is large enough to cross the deadband.
e Schmitt trigger is especially useful in converting slowly varying or a noisy signal into a
clean digital form with sharp transitions. Another common usage is converting sine-wave input
into a pulse-train output.¹⁷ e dependence of the output on both level and level derivative is
unique.
VH
O
u
t deadband
p
u
t VL
VT− VT+ Input
Figure 16.31: Schmitt trigger transfer characteristic hysteresis.
¹⁷Analog Schmitt trigger applications are presented in Section 13.1.

As with all bistable circuits, realizations of Schmitt triggers are possible using both FETs
and BJTs. Two common realizations are shown in Figure 16.32. Similar circuits are available in
most transistor gate families.
Vdd
◦•
V
◦• cc
P1
◦•
◦• P3
R1 R2
◦• P2
◦• ◦• ◦•Vout
Vin◦• ◦• ◦• ◦• ◦• Vout
Vin◦• Q1 Q2 ◦• N1
◦• ◦• N3 ◦• Vdd
Rc N2
(a) (b)
Figure 16.32: Typical Schmitt trigger circuits: (a) Bipolar; (b) CMOS.
Example 16.6
e Bipolar Schmitt Trigger Circuit of Figure 16.32a is constructed with BJTs described by ˇF D
50 and component values:
VCC D 5 V R1 D 3:5 k R2 D 2:6 k Re D 1 k:
Determine the Trigger voltages for positive and negative slope signals, VTC and VT .
Solution
When Vin is LOW, Q1 is cut-off and Q2 is in saturation. Two loop equations can be written:
5 3:5 k Ib2 0:8 1 k .Ib2 C Ic2 / D 0;
and
5 2:6 k Ic2 0:2 1 k .Ib2 C Ic2 / D 0:
e solution to this pair of equations is
Ib2 D 679 A and Ic2 D 1:145 mA:
16.6. SEMICONDUCTOR MEMORIES 1151
Which implies
Vout D 2:024 V and Ve2 D 1:824 V:
e change of state will begin when Q1 begins to turn on
VTC Ve2 C V 1 D 1:824 C 0:5 D 2:33 V:
When Vin is HIGH, Q1 is in saturation and Q2 is cut-off: Vout D 5 V. e low threshold voltage
can be found by determining when Q2 begins to turn on. For this to happen, Q1 must enter the
forward-active region and have a collector-emitter voltage equal to the cut-in voltage of Q2 D
V 2 . e collector-emitter voltage of Q1 (with Q2 OFF) is given by:
ˇF
5 3:5 k Ie1 1 k Ie1 D V D 0:5:
ˇF C 1
e solution to this equation is
Ie1 D 1:015 mA VT D Vin D 1 k Ie1 C 0:7 D 1:72 V:
16.6 SEMICONDUCTOR MEMORIES

Memories are devices that are capable of the storage and retrieval of large amounts of digital data
often required in modern digital systems. A wide variety of memory systems are available:
• Semiconductor memories
• Magnetic core memories
• Magnetic bubble memories
• Moving surface memories (magnetic tape, disc, etc.)
Discussion here will be focused on the first of these possibilities: semiconductor memories. In
addition, the discussion will be restricted to random-access memory (RAM) and exclude read-only
memory (ROM).
Semiconductor RAM is typically composed of large arrays of identical, single-bit mem-
ory cells that are accessed through row and column decoding electronics. e general topology
for such an array is shown in Figure 16.33. Each cell must be capable of reading data from an
external source, storing the data until needed, and then writing the data to an external element.
Consequently, the memory array includes both address/command lines as well as data lines. Since
memory addressing is based on binary codes, the number of rows and columns are integral powers
of 2.
1
2
1
◦•
2
◦• Memory Cell Array
Row
Decoder single cell
Circuitry
N
◦•
2N
1 2 2M
◦• Data Out
Read/Write ◦•
Circuitry ◦•
Data In
1 2 M
◦• ◦• ◦•
Figure 16.33: Semiconductor RAM array topology.
e topology of the individual memory cells distinguishes the various types of semicon-
ductor RAM. A RAM cell typically stores information in either a digital latching circuit or in
the charge on a capacitor. Latches can hold their state indefinitely (assuming no loss of electrical
power), while the charge in a capacitor-based storage cell gradually dissipates and must be pe-
riodically refreshed by external circuitry. e term static random access memory (SRAM) applies
to latch-based cells, while the term dynamic random access memory (DRAM) applies to cells that
must be refreshed.
Static Random Access Memory

Typical static memories are based upon the simple digital latches discussed in Section 16.5. While
any of the bipolar or MOS latch realizations discussed can be used to form static memories, the
MOS realizations are currently the dominant technology. MOS SRAM memory cells are char-
acterized by high speed, low power consumption, and high reliability. A six FET (6-T) CMOS
memory cell based on a CMOS SR latch is shown in Figure 16.34. In this cell, input data, DI ,
enters the latch through the FET switch formed by Q5 and exits the latch through Q6 as out-
put data, DO . A HIGH signal on the Read/Write line activates the two FET switches, enabling
the entrance or exit of data. A LOW signal on the Read/Write line disconnects the latch from
external circuitry: without any external stimulation, the latch holds its current state. As with all
CMOS circuitry, the current flow in this cell is extremely low except when the cell is in transition
16.6. SEMICONDUCTOR MEMORIES 1153
between memory states. e resultant low power consumption is extremely attractive for memory
systems dependent on limited capacity power sources such as batteries.
V• DD
◦
◦•
Q3 Q4
◦•
DI ◦• Q5 ◦• ◦• Q6 ◦• DO
Q1 Q2
◦•
◦• ◦•
Figure 16.34: 6-T SRAM CMOS memory cell.
An NMOS version of the 6-T cell is also available. In the NMOS cell, Q3 and Q4 are
replaced by active loads, typically enhancement-mode FETs. e NMOS realization of the 6-
FET memory cell draws a more-consistent, albeit higher, current from the power supply. e
price of less electrical noise than the CMOS realization is increased power consumption.
Another variation of this cell is the four FET (4-T) SRAM cell. is variation is essentially
the same circuit as the NMOS realization. Here the active load FETs are replaced by polysilicon
resistors. e variation allows for smaller cell size, but increases power consumption and decreases
reliability somewhat over the other two realizations.
Dynamic Random Access Memory

In many situations, the packing density of memory cells can be an important factor in memory
design. e dependence of static RAM on latches prohibits a size reduction beyond the 4-T
size. In addition, the control lines to a single SRAM cell can be as many a six. Dynamic RAM
can break these barriers by basing data memory on capacitor charge storage. e disadvantage
of DRAM lies in the need to refresh the capacitor charge before leakage can degrade the data
storage process. e need to keep the memory-storage capacitors small in size results in a refresh
process cycling every 2 to 4 ms. Even though this seems frequent, for very large memory arrays,
DRAM can have a distinct advantage over SRAM.
Two basic memory cells dominate DRAM design: a three FET (3-T) and a single FET
(1-T) design. e 3-T design is shown in Figure 16.35: it is basically a capacitor, two switches,
and an output buffer. Incoming data, DI , enters through switch Q1 and in stored in the capacitor.
Q2 acts as an inverting buffer so that the capacitor is not significantly discharged when the output
switch, Q3 , is activated to write the output, DO . e inversion of the output signal due to the
buffer is usually compensated in either the read or write path with a single inverter. e 3-T cell
requires separate read and write lines, but the data lines may be combined at the expense of more
complex data encoding/decoding electronics.
◦• Read ◦• Write
Q3 ◦•
DI ◦• Q1 ◦• Q2
C
◦•
Figure 16.35: Typical 3-T DRAM memory cell.
e simplest of all DRAM cells is the 1-T cell shown in Figure 16.36. Here the data
storage capacitor is connected to a single data line through a single switch. Incoming data charges
the capacitor through the switch. When the data is to be read, the same switch connects the
capacitor to the data line. is connection completely discharges the capacitor: it is then necessary
to immediately refresh that data by imposing an amplified duplicate back onto the data line. Of
course this immediate-refresh-after-read is in addition to the normal refresh process necessary in
all DRAM. e cell size reduction possible in the 1-T warrants, in many situations, the added
complexity of the drive electronics.
16.7 GALLIUM ARSENIDE LOGIC

Gallium Arsenide (GaAs) integrated circuits have a distinct speed advantage over similarly sized
Silicon ICs. Gate operating speeds in excess of 1 Gigabit per second are currently available and
the speed limit appears not to have been reached. In addition, GaAs circuits typically dissipate
less power than Silicon circuits. Unfortunately, only two logic functions, an inverter or a NOR
gate, can currently be constructed as a single logic stage: all more complex functions must be
created from arrays of gates. In addition, the processing technology of GaAs circuits is not at the
same stage of maturity as Silicon IC processing. Currently, GaAs wafers are significantly smaller
than Silicon wafers. It is also currently difficult to produce transistors within a chip with uniform
electrical properties compared to Silicon MOS device variation. is parameter variation, coupled
16.7. GALLIUM ARSENIDE LOGIC 1155
Read/Write line
◦•
◦• Data line
C
cell
Figure 16.36: Simplified 1-T DRAM memory cell.
with a relatively high thermal coefficient for GaAs and relatively high power dissipation, places
severe restrictions on noise margins and the reliability of logical operations. Still, it appears that
GaAs circuits have a significant future.
Since a native oxide of GaAs does not exist, MOS-like structures are not possible in GaAs
ICs. erefore, other transistor structures have been developed. ree basic transistor structures
have currently been shown to be useful in GaAs circuits:
• Metal-Semiconductor Field Effect Transistors (MESFETs),
• Heterojunction Field Effect Transistors (HFETs), and
• Heterojunction Bipolar Transistors (HBTs).
MESFETs are the current dominant GaAs transistor structure. Operation of a MESFET is sim-
ilar to a JFET where a metal-semiconductor junction takes the place of the p-n junction of the
JFET. As seen in Section 16.2, appropriate metal-semiconductor junctions form Schottky barrier
diodes. Interestingly, MESFETs can be fabricated as either depletion-mode or enhancement-
mode FETs. Voltage current relationships for GaAs MESFETs are essentially the same as for
Silicon JFETs with parameters in the ranges:
2:5 V < VP < 0:2 V or 0:1 V < VT < 0:3 V:
Typical GaAs MESFET Schottky barrier voltage is in the range of 0.8 V. HFETs are charac-
terized by voltage-current relationships similar to MESFETs and are therefore not specifically
discussed. HBTs are functionally similar to bipolar junction transistors. e discussion here is
limited to MESFET gate structures.
ere are two basic families of GaAs MESFET logic circuits:
• Enhancement-Depletion Logic, and
• Source-Coupled Logic.
e enhancement-depletion family bears considerable similarity to NMOS logic, and source-
coupled logic is similar to the bipolar ECL. Because of these similarities, discussion here will be
descriptive, rather than quantitative, in scope. Dominance among the GaAs logic families is not
yet firmly established.
Enhancement-Depletion Logic
GaAs Enhancement-depletion (ED) logic circuits share the same topology with NMOS logic
circuits. As an example, the topology of the GaAs NOR gate shown in Figure 16.37 is essentially
the same as the NMOS NOR gate shown in Figure 16.22b. In this realization, Q1 and Q2 are
enhancement-mode FETs and Q3 is a depletion-mode FET used as an active load.¹⁸ However,
the functional differences between a GaAs MESFET and a Silicon MOSFET restricts direct
comparisons. In particular, the Schottky barrier diode inherent to the gate of a GaAs device allows
gate current to flow when gate-source voltages exceed the Schottky barrier voltage. Consequently,
voltage swing must be kept small in order to avoid this detrimental gate current condition.
V
◦• DD
A◦• Q3
◦• ◦• ◦• C = A + B
B◦• Q1 Q2
◦•
Figure 16.37: Simple GaAs enhancement-depletion NOR gate.
e principle differences between GaAs ED logic and NMOS logic are:
• For a HIGH output, any slave gate attached to the output will clamp the output voltage
to the Schottky barrier voltage ( 0:8 V). e output voltage in NMOS is limited to the
much larger value, VDD VT .
• For a HIGH output, the current in the active load is not zero: power is dissipated for both
HIGH and LOW output levels. NMOS dissipates essentially zero power for a HIGH
output.
¹⁸e NMOS gate in Figure 16.22b uses an enhancement-mode FET as an active load rather than a depletion-mode FET.
While GaAs requires a depletion-mode active load, NMOS can be fabricated in either form: operation of the gate is the
same.
• When the input is HIGH, the output is LOW unless the input voltage exceeds the Schot-
tky barrier voltage. Further increases in the input voltage increase the output voltage. If
sufficiently high input voltage is applied, logical errors will occur. NMOS does not have
this potential problem.
• Voltage swings are limited to the Schottky barrier voltage ( 0:8 V). NMOS swings can be
much larger.
• e power supply voltage for GaAs ED logic needs to be only slightly larger than the Schot-
tky barrier voltage. is supply voltage can therefore be significantly smaller than that of
NMOS logic.
• e threshold voltage for GaAs enhancement FETs must be less than the turn-on voltage
of the Schottky diode. NMOS FETs do not have this restriction.
While it is possible to construct a GaAs NAND gate using the same topology as a NMOS NAND
gate, the very small differences in voltage levels between a logic HIGH and LOW reduce the noise
margin to unacceptable levels. e “stacking” of enhancement FETs to create the logic NAND
function increases the logic LOW and is responsible for this reduction in noise margins. GaAs
NAND gates are not commercially available.
Source-Coupled Logic
GaAs source-coupled (SC) logic is based upon a FET differential amplifier¹⁹ in the same manner
as Emitter-coupled logic is based on a BJT differential amplifier. A simple two-input OR gate is
shown in Figure 16.38. If either input, A or B, is a logic HIGH, Q3 will enter cut-off and the
output, C, will become a logic HIGH. Conversely, only if both inputs are a logic LOW will Q3
enter saturation and the output goes to a logic LOW. e logic voltage levels for an unloaded
gate are:
VoH VDD VT and VoL VT :
is logic swing is significantly larger than other forms of GaAs logic. Noise margins are also
significantly improved.
One particularly attractive feature of SC logic is its insensitivity to transistor parameter
variation. Unfortunately, SC logic consumes significantly more power than other forms of GaAs
logic. A simple SC OR gate is roughly twice the size of the same gate in GaAs ED logic. Gate
speed is essentially equivalent in the two logic families.

e essential aspects of the electronic operation of the major digital circuits commonly in use have
been presented in this chapter. Discussion has been limited to the basic building blocks of each
¹⁹Source-coupled differential amplifiers are discussed in Section 6.3 (Book 2).
V
◦• DD
◦•
A◦• Q5 Q6
◦• ◦• ◦• C ◦• ◦• ◦• C = A + B
B◦• Q1 Q2 Q3 ◦• Vref
◦• ◦•
Q4
◦•
Figure 16.38: Simple GaAs source-coupled OR/NOR gate.
of the major logic families commonly in use. A short comparison of a four commercial logic gate
families is shown in Table 16.1.

An existing TTL (LS) digital circuit is to be interfaced to a new system using CMOS (HC)
digital gates. Both systems are to be operated from a 5 V power source. e nominal input and
output specifications of the two logic families for 5 V operation are shown in Table 16.2.
e small difference in propagation delay presents no significant problems in design of an
interface between the two circuits. ere is, however a mismatch in acceptable logic levels. e
CMOS output logic levels are compatible with the TTL input levels, but the TTL HIGH output
(VOH.min/ D 2:7 V) is not compatible with the CMOS HIGH input requirements (VIH.min/ D
3:15 V). Interface circuitry to alleviate this incompatibility is to be designed.
Solution:
e output level of LS TTL gates is determined by the active pull-up circuitry: the voltage
drop across this circuitry, even with minimal load current, does not allow the output voltage to
consistently rise above the levels necessary for HCMOS circuitry. A variety of possible interfaces
can be considered:
• Buffer the TTL output with a TTL gate that has passive pull-up.
• Buffer the TTL output with an HCT gate (these are HCMOS gates specifically modified
to accept TTL levels at the input.
• Operate the CMOS portion of the circuit at a lower voltage level, i.e., 3 V.
Table 16.1: Comparison of commercial logic gate properties
Logic Family TTL ECL CMOS

Series H LS 100K HC
Basic Gate NAND NAND OR/NOR NOR OR NAND
Fan-out 10 20 25 >50
Power Dissipation 22.5 mW 2 mW 40 mW 1.75 nW @1MHz
Noise Margin-Low 0.4 V 0.3 V 0.14 V 1.25 V
Noise Margin-High 0.4 V 0.7 V 0.14 V 1.25 V
6 ns 9.5 ns 0.75 ns 8 ns
Propagation Delay
(CL = 25 pF (CL = 15 pF (CL = 50 pF (CL = 50 pF)
Maximum
Clock Frequency 50 MHz 33 MHz 350 MHz 50 MHz
(D-flip-flop)
Table 16.2: Nominal input and output specifications of the two logic families for 5 V operations
LS TTL HC CMOS
VOH (min) 2.7 V 4.4 V

VIH(min) 2.0 V 3.15 V
VOL(max) 0.5 V 0.1 V
VIL(max) 0.8 V 0.9 V
IOL(max) 8 mA 4 mA
IIL(max) –0.4 mA –1 µA
IOH(max) –0.4 mA –4 µA
IIH(max) 20 µA 1 µA
Propagation Delay 9 ns 8 ns
• Shunt the TTL active pull-up with an external, passive pull-up.
Buffering can provide a good solution. e only significant drawbacks are an addition of compo-
nents and the additional propagation delay induced by the buffer. TTL gates with passive pull-up
may introduce a large additional propagation delay and are, therefore discarded as an alternative.
If the new CMOS system can be implemented with HCT gates as the input gates, this is proba-
bly the best solution. Operation of the CMOS portion of the circuit at 3 V will lower the required
HIGH input voltage requirement below the TTL output HIGH. Unfortunately this also reduces
noise margins and violates the constraints in the design requirements. If HCT input gates are not
possible, shunting the TTL active pullup with an external, passive pull-up seems a viable design
alternative.
5• V
◦
◦• ◦• ◦• ◦•
HCMOS
Input Gate
Rp Passive
◦•
Pull-up
◦•
◦• ◦•
◦•
◦• ◦• ◦•
◦• ◦•
LS TTL
Output Gate
◦• ◦•
An external resistor that shunts the output of the LS TTL gate will force the HIGH level
at the interface near 5 V. e minimum value of the pull-up resistor, Rp , is determined by the
current sinking capability of the TTL gate: the LOW voltage must remain within specifications.
For a LOW, the maximum current through the resistor is given by the sum of the maximum TTL
output current and N CMOS input currents. is LOW voltage requirement restricts Rp to:
TTL
VCC VOL. max/
Rp > 563 :
TTL
IOL. max/ NI HC
IL
e maximum value of Rp is determined by the output voltage rise time. is voltage rise is a
complex process. It rises to VOH.min/ very quickly ( 9 ns) due to the active pull-up. ereafter,
the rise will be exponential due to the RC time constant formed by the input capacitance of the
16.9. PROBLEMS 1161
CMOS gates and Rp . e time period for the voltage to exceed the CMOS VIH.min/ is given by
the solution to:
t
TTL HC
v .t/ D VCC VCC VOH. min/ e
Rp C
D VIH. min/
t
v .t/ D 5 2:3 e Rp C
D 3:15 ) t D 0:22Rp C:
If a design using a shunt, passive pull-up resistor is to be better than a design using a buffer gate,
the additional rise time must be shorter than the propagation delay due to a buffer. at is:
.9 ns/ 40:9 ns
t < 9 ns ) Rp < D :
.0:22/ C C
e total capacitance, C , is given by the input capacitance of the total number of CMOS gates
being driven by the TTL gate. A typical value is: C 10 pF. is capacitive assumption leads to:
Rp < 4:09 k:
us,
563 < Rp < 4:09 k:
A reasonable, standard-value choice is
Rp D 1:5 k:
16.9 PROBLEMS
16.1. e BJT in the simple inverter shown is described by:
ˇF D 75 fT D 200 MHz ˇR D 2:
If the input voltage, Vin , has logic levels, 0 V and 5 V, determine the following:
(a) e rise time

(b) e delay time
(c) e fall time
(d) e storage time
(e) e average propagation delay
5V
◦•
2.2 kΩ
◦• ◦• Vout
5.6 kΩ
◦•
+
Vin − 15 kΩ
◦• ◦•
16.2. Assume the power supply for the simple inverter of Problem 16-1 is reduced to 3.3 V and
the input logic levels become 0 V and 3.3 V. e transistor parameters are unchanged.
Determine the following:
(a) e rise time

(b) e delay time
(c) e fall time
16.3. In an attempt to decrease the propagation delay of the simple inverter described in Prob-
lem 16-1, the collector resistor is reduced to 1.5 k. Comment quantitatively on the
advisability of this design change.
16.4. e BJTs in the inverter with active pull-up shown are described by:
(a) e rise time

(b) e delay time
(c) e fall time
16.9. PROBLEMS 1163
5V
◦• ◦•
56 kΩ
750 kΩ
◦•
◦•
3.9 kΩ
◦• ◦• Vout
5.6 kΩ
◦•
+
Vin − 15 kΩ
◦• ◦•
16.5. For the simple bipolar inverter shown:

(a) Use SPICE to determine the gate speed. Assume the BJT has the same properties
as a 2N2222 NPN bipolar transistor.
(b) Model a Schottky inverter by shunting the base-collector junction of the given BJT
with a diode. Repeat the SPICE gate speed determination of part a). Assume the
diode has properties
Is D 2 nA D 2:1:
(c) Comment on any gate speed differences.
5V
◦•
2.2 kΩ
◦• ◦• Vout
5.6 kΩ
◦•
+
Vin − 15 kΩ
◦• ◦•
16.6. e BJTs in the inverter with active pull-up shown are described by:
(a) e rise time

(b) e delay time
(c) e fall time
5 V ◦• ◦•
1.5 kΩ 330 Ω
◦• ◦• Vout
5.6 kΩ
◦•
+
Vin − 15 kΩ
◦• ◦•
16.7. e BJTs in the inverter with active pull-up and pull-down as shown are described by:
(a) e rise time

(b) e delay time
(c) e fall time
16.9. PROBLEMS 1165
◦• ◦• 5 V
56 Ω
750 Ω
◦•
◦•
3.9 kΩ
◦• ◦• Vout
5.6 kΩ
◦• ◦• ◦•
+ 510 Ω 240 Ω
Vin − 15 kΩ
◦• ◦• ◦•
16.8. e circuit shown is a form of simplified TTL gate.
(a) Determine the logical operation the gate performs on the four inputs: A, B, C and
D.
(b) What are the logic voltage levels at the output, Vout ?
5 V◦• ◦• ◦• ◦•
130 Ω
3.9 kΩ 1.6 kΩ 3.9 kΩ
◦•
A ◦• ◦• C
B ◦• ◦• D
◦• ◦• ◦• Vout
◦•
1 kΩ
◦•
16.9. Compare the average power consumption of the simple ECL OR gate of Fig-
ure 3.12 (Book 1) to that of a 10 K OR gate (Figure 16.13) with the following parameters:
RC 2 D 218 RC 3 D 246 REP D 777
R1 D 909 R2 D 6:12 k R3 D 4:99 k RIN1 D RIN2 D 51 k.
Assume a pull-down resistor at the output of 1.5 k and BJTs with ˇF D 100.
16.10. A CMOS inverter is fabricated using a 3.3 V supply and MOSFETs with the following
properties:
KN D 0:1 mA=V2 KP D 0:25 mA=V2 and jVT j D 1:
(a) Determine the average propagation delay time if it is driving a capacitive load of
5 pF.
(b) Compare the results of part a to those found in Example 16.2.
16.11. A CMOS inverter is fabricated using a 5 V supply and MOSFETs with the following
properties:
KN D 0:4 mA=V2 KP D 0:8 mA=V2 and jVT j D 1:2:
Determine the average propagation delay time if the gate is driving a capacitive load of
5 pF.
16.12. A CMOS inverter is fabricated using a 3 V supply and MOSFETs with the following
properties:
KN D 0:06 mA=V2 KP D 0:15 mA=V2 and jVT j D 0:6 V:
Determine the average propagation delay time if the gate is driving a capacitive load of
15 pF.
16.13. A CMOS inverter is fabricated using transistors with the following properties:
KN D KP D 0:1 mA=V2 jVT j D 1:5 V:
Use SPICE to determine the voltage transfer characteristic for the following power sup-
ply conditions:
(a) VDD < VT

(b) VDD D VT
(c) VDD D 2VT
(d) VDD D 3VT
Comment on the results.

16.9. PROBLEMS 1167
16.14. Given a 5 V power supply. Design a three-input NMOS NOR gate to have the following
output logic levels when driven by a gate of the same design:
What are the values of VoL for one, two and three inputs HIGH?
16.15. Given a 3.3 V power supply. Design a three-input NMOS NOR gate to have the fol-
lowing output logic levels when driven by a gate of the same design:
What are the values of VoL for one, two and three inputs HIGH?
16.16. Given a 5 V power supply. Design a three-input NMOS NAND gate to have the fol-
16.17. Given a 3.3 V power supply. Design a three-input NMOS NAND gate to have the fol-
16.18. Determine a logical expression for the output, Y, of the CMOS circuit shown as a func-
tion of the three inputs, A, B, and C.
Use SPICE to verify the logical expression. Assume the MOSFETs are described by:
jVT j D 1 V K D 0:4 mA=V2 :
VCC
◦•
A◦• ◦• B ◦• ◦• C◦• ◦•
◦• ◦• Y
◦• ◦•
◦•
16.19. Given a 3 V power supply. Design a three-input NMOS NAND gate to have the fol-
16.20. Determine the range of input voltages at which the midpoint of a logic transition occurs
for a two-input CMOS NAND gate that uses FETs described by:
jVT j D 0:5 V and Kn =Kp D 2;
and a 3 V power supply.

16.21. Determine the range of input voltages at which the midpoint of a logic transition occurs
for a two-input CMOS NAND gate that uses FETs described by:
jVT j D 1:0 V and Kn =Kp D 4;
and a 5 V power supply. Compare this voltage range to that found in Example 16.5.
16.22. It is possible to form bipolar gates that operate similarly to MOS gates. One such circuit
is shown. Determine the logic function implemented by this circuit.
VCC
◦•
◦• ◦• Vout
A ◦•
B ◦•
16.23. Use SPICE to implement the CMOS SR Latch of Figure 16.28. Assume a 5 V power
supply and MOSFETs described by:
KN D 0:1 mA=V2 KP D 0:25 mA=V2 and jVT j D 0:6 V:
Verify correct operation of the latch.

16.24. Design a bipolar Schmitt trigger using BJTs characterized by ˇF D 75 and a 5 V power
supply to meet the following design criteria.
16.9. PROBLEMS 1169
reshold voltages:
VTC D 2:2 V and VT D 1:5 V:
Power consumption:
Power supplied by the 5 V source must not exceed 5 mW in any stable state.
Any current entering the input terminal of the Schmitt trigger is excluded from
this calculation.
16.25. Design a bipolar Schmitt trigger using BJTs characterized by ˇF D 100 and a 3.3 V
power supply to meet the following design criteria.
reshold voltages:
VTC D 2:0 V and VT D 1:2 V:
Power consumption:
Power supplied by the 3.3 V source must not exceed 3 mW in any stable state.
Any current entering the input terminal of the Schmitt trigger is excluded from
this calculation.
16.26. Use SPICE to determine the transfer characteristic for the given Silicon bipolar Schmitt
trigger. e BJTs are characterized by ˇF D 50. Compare SPICE results to those ob-
tained by the simple hand analysis of Example 16.6. Over what range of input voltages
are the two transition regions?
Hint: In transient analysis SPICE may have difficulty converging for switching circuits:
this can usually be eliminated by setting ITL4 D 40 in a .OPTIONS statement.
◦• 5 V
◦•
3.5 kΩ 2.6 kΩ
◦• ◦• ◦• Vout
Vin◦• Q1 Q2
◦•
1 kΩ
16.27. In the Schmitt trigger circuit shown, the BJTs are characterized by ˇF D 50.
(a) Using simple hand analysis, determine the positive and negative slope trigger volt-
ages, VTC and VT .
(b) Use SPICE to validate results obtained by the simple hand analysis.
Hint: In transient analysis SPICE may have difficulty converging for switching circuits:
this can usually be eliminated by setting ITL4 D 40 in a .OPTIONS statement.
◦• 3.3 V
◦•
3.3 kΩ 2.2 kΩ
◦• ◦• ◦• Vout
Vin◦• Q1 Q2
◦•
910 Ω
16.28. Use SPICE to determine the voltage transfer characteristic for the given MOSFET
Schmitt trigger. e MOSFETs are characterized by:
VT D 1 V K D 0:2 mA=V2 :
◦• 5V
P1
◦• P3
◦• P2
Vin◦• ◦• ◦• ◦• ◦•Vout
◦• N2
◦• N3 ◦• 5V
N1
16.9. PROBLEMS 1171
16.29. An existing TTL (LS) digital system is to be interfaced to a new ECL digital system.
e interface is unidirectional with the TTL system driving the ECL system. It has been
suggested that the interface can be realized using a common-base amplifier. e nominal
input and output specifications of the two logic families are known to be:
LS TTL 10K ECL
VOH (min) 2.7 V –0.98

VIH(min) 2.0 V –1.105
VOL(max) 0.5 V –1.85
VIL(max) 0.8 V –1.475
IOL(max) 8 mA 22.3 mA
IIL(max) –0.4 mA 65 µA
IOH(max) –0.4 mA 5.4 mA
IIH(max) 20 µA 130.5 µA
Propagation Delay 9 ns 2.5 ns
Complete the interface design and verify proper operation using SPICE.
16.30. It has been suggested that the TTL-CMOS interface described in the Summary Design
Example could be improve upon using an active logic-level interface circuit. One such
interface circuit is shown.
Choose appropriate resistor values and compare the operation of this interface circuit to
that of the Summary Design Example. Assume BJTs described by:
ˇF D 50:
◦• VCC
◦•
◦•
◦• ◦• vout
vin◦•
◦•
REFERENCES
[1] ——-, High-Speed CMOS Logic Data Book, Texas Instruments Inc., Dallas, 1988.
[2] Buchanan, James, CMOS/TTL Digital Systems Design, McGraw-Hill Book Company,
New York, 1990.
[3] Glasford, Glenn, Digital Electronic Circuits, Prentice Hall, Inc., Englewood Cliffs, 1988.
[4] Haznedar, Haldun, Digital Microelectronics, e Benjamin/Cummings Publishing Com-
pany, Inc., 1991.
[5] Hodges, David and Jackson, Horace, Analysis and Design of Digital Integrated Circuits, 2nd
Ed., McGraw-Hill Book Company, New York, 1988.
[6] Shoji, Masakazu, CMOS Digital Circuit Technology, Prentice Hall, Inc., Englewood Cliffs,
1988.
[7] Taub, Herbert and Schilling, Donald, Digital Integrated Electronics, McGraw-Hill Book
Company, New York, 1977.
[8] Wing, Omar, Gallium Arsenide Digital Circuits, Kluwer Academic Publishers, Boston,
1990.
1173
Authors’ Biographies
omas F. Schubert, Jr., and Ernest M. Kim are colleagues in the Electrical Engineering
Department of the Shiley-Marcos School of Engineering at the University of San Diego.
THOMAS F. SCHUBERT, JR.

omas Schubert received BS, MS, and PhD degrees in Elec-
trical Engineering from the University of California at Irvine
(UCI). He was a member of the first engineering graduating
class and the first triple-degree recipient in engineering at UCI.
His doctoral work discussed the propagation of polarized light
in anisotropic media.
Dr. Schubert arrived at the University of San Diego in
August, 1987 as one of the two founding faculty of its new En-
gineering Program. From 1997–2003, he led the Department as
Chairman, a position that became Director of Engineering Pro-
grams during his leadership tenure. Prior to coming to USD, he
was at the Space and Communications Division of Hughes Air-
craft Company, the University of Portland, and Portland State
University. He is a Registered Professional Engineer in the State of Oregon.
In 2012, Dr. Schubert was awarded the Robert G. Quinn Award by the American So-
ciety of Engineering Education “in recognition of outstanding contributions in providing and
promoting excellence in engineering experimentation and laboratory instruction.”
1174 AUTHORS’ BIOGRAPHIES
ERNEST M. KIM
Ernest Kim received his B.S.E.E. from the University of
Hawaii at Manoa in Honolulu, Hawaii in 1977, an M.S.E.E.
in 1980 and Ph.D. in Electrical Engineering in 1987 from New
Mexico State University in Las Cruces, New Mexico. His dis-
sertation was on precision near-field exit radiation measure-
ments from optical fibers.
Dr. Kim worked as an Electrical Engineer for the Uni-
versity of Hawaii at the Naval Ocean Systems Center, Hawaii
Labs at Kaneohe Marine Corps Air Station after graduating
with his B.S.E.E. Upon completing his M.S.E.E., he was an
electrical engineer with the National Bureau of Standards in
Boulder, Colorado designing hardware for precision fiber optic
measurements. He then entered the commercial sector as a staff
engineer with Burroughs Corporation in San Diego, California developing fiber optic LAN sys-
tems. He left Burroughs for Tacan/IPITEK Corporation as Manager of Electro-Optic Systems
developing fiber optic CATV hardware and systems. In 1990 he joined the faculty of the Univer-
sity of San Diego. He remains an active consultant in radio frequency and analog circuit design,
and teaches review courses for the engineering Fundamentals Examination.
Dr. Kim is a member of the IEEE, ASEE, and CSPE. He is a Licensed Professional
Electrical Engineer in California.

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Series ISSN: 1932-3166

SCHUBERT, JR. • KIM

Fundamentals of Electronics: Book 4

FUNDAMENTALS OF ELECTRONICS: BOOK 4

MORGAN & CLAYPOOL

Fundamentals of Electronics: Book 4 Oscillators and Advanced Electronics Topics

Fundamentals of Electronics: Book 3 Active Filters and Ampliﬁer Frequency

Fundamentals of Electronics: Book 2 Ampliﬁers: Analysis and Design

Fundamentals of Electronics: Book 1 Electronic Devices and Circuit Applications

Applications of Zero-Suppressed Decision Diagrams

Arduino Microcontroller Processing for Everyone! ird Edition

Boolean Diﬀerential Equations

Introduction to Noise-Resilient Computing

Atmel AVR Microcontroller Primer: Programming and Interfacing, Second Edition

Representation of Multiple-Valued Logic Functions

Arduino Microcontroller: Processing for Everyone! Second Edition

Advanced Circuit Simulation Using Multisim Workbench

Circuit Analysis with Multisim

Microcontroller Programming and Interfacing Texas Instruments MSP430, Part I

Microcontroller Programming and Interfacing Texas Instruments MSP430, Part II

Pragmatic Electrical Engineering: Fundamentals

Introduction to Embedded Systems: Using ANSI C and the Arduino Development

Arduino Microcontroller: Processing for Everyone! Part II

Arduino Microcontroller Processing for Everyone! Part I

Digital System Veriﬁcation: A Combined Formal Methods and Simulation Framework

Progress in Applications of Boolean Functions

Embedded Systems Design with the Atmel AVR Microcontroller: Part II

Embedded Systems Design with the Atmel AVR Microcontroller: Part I

Designing Asynchronous Circuits using NULL Convention Logic (NCL)

Developing Embedded Software using DaVinci & OMAP Technology

Mismatch and Noise in Modern IC Processes

Asynchronous Sequential Machine Design and Analysis: A Comprehensive Development

An Introduction to Logic Circuit Testing

Multiple Valued Logic: Concepts and Representations

Finite State Machine Datapath Design, Optimization, and Implementation

Atmel AVR Microcontroller Primer: Programming and Interfacing

PSpice for Filters and Transmission Lines

PSpice for Analog Communications Engineering

PSpice for Digital Communications Engineering

PSpice for Circuit eory and Electronic Devices

Pragmatic Circuits: DC and Time Domain

Pragmatic Circuits: Frequency Domain

Pragmatic Circuits: Signals and Filters

High-Speed Digital System Design

Introduction to Logic Synthesis using Verilog HDL

Microcontrollers Fundamentals for Engineers and Scientists

Fundamentals of Electronics: Book 4 Oscillators and Advanced Electronics Topics

ISBN: 9781627055680 paperback

A Publication in the Morgan & Claypool Publishers series

omas F. Schubert, Jr. and Ernest M. Kim

SYNTHESIS LECTURES ON DIGITAL CIRCUITS AND SYSTEMS #50

12 Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925

13 Waveform Generation and Waveshaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969

14 Power Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011

15 Communication Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051

16 Digital Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105

Authors’ Biographies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173

• Oscillator discussions focus on both linear and non-linear oscillators.

• Power circuit discussions focus on DC power.

• Communication circuit discussions focus on high-frequency operation and the frequency

Rf D .Avo R/ D Œ 34:8 .6:49 k/ D 225:9 k 226 k:

Figure 12.6: Depletion NMOSFET-based phase-shift oscillator; bias resistor RG R.

ZL D Œ.Z1 ==Ri / C Z3 ==Z2 : (12.42)

D 1:03 H 1:0 H:

Ci D C C C .1 C gm R/ D C C C f 1 C gm ŒRB1 ==RB2 ==RC == .rb C r /g

C1 D C10 C Ci D 0:051 F C 147:8 pF D 51:15 nF:

f D 2RC and that the gain must exceed 3.

ˇF D 200; VA D 150 V; rb D 30 ; Cibo D 8 pF at VEB D 0:5 V;