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How Computers Work

Lecture 7

Under the Hood of Synchronous Finite State Machines

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What do these have in common?

D Q

CLK

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The Selector
Truth Table
A 0
Q S Q

B 1 0 A
1 B

S No bubble, so positive logic

(H = 1 , L = 0)

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The Selectors K-Map

B
Truth Table AB
S 00 01 11 10
S Q 0 00 11 11 00

0 A
1 B 1 00 00 11 11 S

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Selectors K-Map
B
AB
S 00 01 11 10
A 0
P2
0 0 0 1 1

B 1 1 0 1 1 0 S

S P1 A

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Review: The Selectors Minimum

SOP Implementation
A
P2

S
P1
B

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The Trouble with Transitions

Suppose: A = B = 1 (H)

S:

P1

P2

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Hazards
Static Hazards:
Output Enters Forbidden Zone
Unnecessarily
1-Hazards
0-Hazards
Dynamic Hazards:
Output Enters Same Valid Zone Again after
Entering Opposite Valid Zone
0-1 Hazards
1-0 Hazards

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What You Should Expect

H
Q
H
S

S TTpd
pdmax
max

TTcd
cd==t tpd
pdmin
min

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What Hazard-Free Means

H
Q
H
S

S
Q

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Fundamental Mode
SIC (Single Input Change) rule
Only 1 Input Bit Can Change At a
Time

> Tw
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Fixing the Selectors 1-Hazard

with a redundant product term

B
AB A
S 00 01 11 10
0 0 0 1 1

1 0 1 1 0 S

S
A B

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Rules for Fixing Hazards

in SIC SOP situations
Avoid using X and X in a single product term
This insures product terms have no SIC hazards
prevents all dynamic hazards and static 0-hazards
Cover all adjacent 1 cells in K-map with at least
1 product term
This insures at least 1 product term remains steadily
high during SIC
prevents static 1-hazards
Remember - This Only Applies for SIC !!!

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A First Taste of Asynchronous Yea!

(Fundamental Mode)
State Machines

MUX Implementation
of the Transparent Latch

D
0
Q G
D 1
Q
G

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State Diagram
of D-Latch
GD

G+D 0 1 G +D

GD

D Q

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Definition:
Fundamental Mode
Finite State Machine (FSM)
Finite # of States
Output = f(State, Input)
May just be f(State)
State Transitions occur asynchronously
due to asynchronous (no clock) input
level changes.

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Architecture of
Fundamental Mode FSM

IN OUT
C.L.

STATE

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Fundamental Mode
SIC (Single Input Change) rule
Only 1 Input Bit Can Change At a
Time

> Tw
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SIC Conditions for the

Transparent Latch

Hold time
Th = ________________
Hold time

Setup time
Ts = ____________________
Setup time

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The Set-Reset (SR) Flip-Flop

S R
SR
Q 00 01 11 10
Q
0H 0H 0H 1L 1L
R 1L 1L 0H 1L 1L Q

S S

S 0 1 S+R

R S
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Dual Forms of SR Flops

S S
Q Q

Q R Q
R

Note : Q is true inverse of Q only when S R = 0

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Simple Rules for 2-State

Fundamental Mode State
Machines
SIC Assumption
No Free-Running Oscillators
Logic Is Hazard-Free
Set

Set 0 1 Reset

Reset

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More Complex Fundamental

Mode FSMs
> 2 States possible, with somewhat more complex
rules
Good behavior for non-SIC also possible, with
somewhat more complex rules
Only Certain Hazards are Important
For More Information, read:

The Essence of Logic Circuits, by Stephen H.

Unger, Prentice-Hall, 1989.

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Building a Latch
from an SR Flop

R
__
Q
_____
Q

D S QQ
_____
G

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The Edge-Triggered Flip-Flop

(also called D-FF or Register)

CLK
D Q

CLK
Q

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Building an Edge Triggered FF

out of 2 Latches

D D Q D Q Q
G G

CLK

H
CLK=_________
H

L
CLK=_________
L

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Edge-Triggered F-F Timing

CLK

Hold Time
Th = ________________
Hold Time

Setup Time
Ts = ____________________
Setup Time

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A Pneumatic Flip-Flop

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A Mechanical Flip-Flop

Clock Escapement

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Another Example
of a Flip-Flop

1 Sear - lets hammer fall when trigger is pulled.

2 Hammer hits firing pin, pin dents primer, ignites gunpowder, propels bullet.
3 Gas from burning gunpowder opens bolt, ejects case, pulls hammer back
4 Disconnector - holds hammer back
Semi-Automatic : until trigger is released
Fully-Automatic : until bolt fully closes

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