MATHA COLLEGE OF TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

LESSON PLAN
Subject Name: EC010 404 Digital Eelctronics Class: S4 A - BATCH
Name of the Teacher: Krishnachandran R. Total Expected: - 47 hrs.

Module Topics Date Hours Remarks

Positional Number System: Binary, Octal,

Decimal, Hexadecimal number system, 18-01-12 2
Number base conversions,

complements - signed magnitude binary

numbers - Binary Arithmetic- addition, 19-01-12,
2
subtraction , Binary codes- Weighted, BCD, 20-01-12
8421, Gray code,

Excess 3 codes, ASCII, Error detecting and

20-01-12 1
correcting code, parity, and hamming code.
Module I
Boolean postulates and laws with proof, De-
Morgans Theorems, Principle of Duality, 25-01-12 1
Minimization of Boolean expressions

Sum of Products (SOP), Product of Sums

25-01-12 1
(POS), Canonical forms

Karnaugh map Minimization, Dont care 27-01-12,

2
conditions 01-02-12

Class Test 03-02-12 1

Module II Digital Circuits: Positive and Negative

logic, Transistor transistor logic, TTL with 01-02-12,
2
totem pole, open collector and tri state 02-02-12
output, characteristics of TTL
Emitter coupled logic basic ECL inverter, 03-02-12 ,
2
NMOS NOR gate 08-02-12

CMOS inverter, NAND and NOR, 08-02-12,

2
characteristics of CMOS 09-02-12

Gate performance parameters fan in, fan 10/02/12 2

out, propagation delay, noise margin, power
 dissipation for each logic, subfamilies of
TTL and CMOS

Module II Class Test 16-01-12 1

Introduction to Combinational Circuits:

Basic logic gates, Universal gates,
Realization of Boolean functions using 17/02/12 2
universal gates, Realization of
combinational functions:
addition half and full adder n bit adder 22-02-12 2
carry look ahead adder, subtraction,
Comparison, code conversion, and decoder,
encoder, multiplexer, demultiplexer, parity 29-02-12,
Module III 3
checkers, and parity generator. 01-03-12

Introduction to Sequential Circuits: latches,

timing, Flip Flops, types, characteristic
02-03-12,
equations, excitation tables, Realization of 3
07-03-12
one flip flop using other flip flops.

Class Test 14-03-12 1

Application of flip flops as bounce 07-03-12,

elimination switch, register, counter and 2
14-03-12
RAM, Binary ripple counter,
Synchronous binary counter, Design of
modulo n synchronous counter, up/down 16-03-12,
3
counters, 21-03-12
Module IV
Shift registers SISO, SIPO, PISO, PIPO, 21-03-12,
bidirectional shift register and universal 2
22-03-12
register
Counters based on shift registers 23-03-12 1

Class Test 29-03-12 1

Hazards in combinational circuits: Static

hazard, dynamic hazard, essential hazards, 23-03-12 1
Module V hazard free combinational circuits.
Introduction to programmable logic devices: 30-03-12 1
PLA- block diagram,
PAL block diagram, registered PAL, 30-03-12,
2
Configurable PAL, GAL - architecture, 04-04-12
 CPLD classification internal architecture 04-04-12 1

Module V FPGA - architecture 12-04-12 1

ASIC categories, full custom and semi

custom. 13-04-12 1

Class Test 13-04-12 1

 MATHA COLLEGE OF TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

LESSON PLAN
Subject Name: EC010 404 Digital Eelctronics Class: S4 B - BATCH
Name of the Teacher: Krishnachandran R. Total Expected: - 48 hrs.

Module Topics Date Hours Remarks

Positional Number System: Binary, Octal,

18-01-12,
Decimal, Hexadecimal number system, 2
19-01-12
Number base conversions,

complements - signed magnitude binary

numbers - Binary Arithmetic- addition, 21-01-12,
2
subtraction , Binary codes- Weighted, BCD, 23-01-12
8421, Gray code,

Excess 3 codes, ASCII, Error detecting and

24-01-12 1
correcting code, parity, and hamming code.
Module I
Boolean postulates and laws with proof, De-
Morgans Theorems, Principle of Duality, 25-01-12 1
Minimization of Boolean expressions

Sum of Products (SOP), Product of Sums

28-01-12 1
(POS), Canonical forms

Karnaugh map Minimization, Dont care 30-01-12,

2
conditions 31-01-12

Class Test 04-02-12 1

Module II Digital Circuits: Positive and Negative

logic, Transistor transistor logic, TTL with 01-02-12,
2
totem pole, open collector and tri state 02-02-12
output, characteristics of TTL
Emitter coupled logic basic ECL inverter, 06-02-12 ,
2
NMOS NOR gate 07-02-12

CMOS inverter, NAND and NOR, 08-02-12,

2
characteristics of CMOS 09-02-12

Gate performance parameters fan in, fan 16-02-12, 2

out, propagation delay, noise margin, power 17-02-12
dissipation for each logic, subfamilies of
 TTL and CMOS

Module II Class Test 17-01-12 1

Introduction to Combinational Circuits:

Basic logic gates, Universal gates, 18-02-12,
Realization of Boolean functions using 2
21-02-12
universal gates, Realization of
combinational functions:
addition half and full adder n bit adder 22-02-12,
2
carry look ahead adder, subtraction, 25-02-12

Comparison, code conversion, and decoder,

Module III encoder, multiplexer, demultiplexer, parity 27-02-12,
3
checkers, and parity generator. 29-03-12

Introduction to Sequential Circuits: latches,

timing, Flip Flops, types, characteristic
01-03-12,
equations, excitation tables, Realization of 3
05-03-12
one flip flop using other flip flops.

Class Test 07-03-12 1

Application of flip flops as bounce 06-03-12,

elimination switch, register, counter and 2
12-03-12
RAM, Binary ripple counter,
Synchronous binary counter, Design of
modulo n synchronous counter, up/down 13-03-12,
3
counters, 17-03-12
Module IV
Shift registers SISO, SIPO, PISO, PIPO, 19-03-12,
bidirectional shift register and universal 2
20-03-12
register
Counters based on shift registers 21-03-12 1

Class Test 24-03-12 1

Hazards in combinational circuits: Static

hazard, dynamic hazard, essential hazards, 22-03-12 1
Module V hazard free combinational circuits.
Introduction to programmable logic devices: 29-03-12 1
PLA- block diagram,
PAL block diagram, registered PAL, 30-04-12,
3
Configurable PAL, GAL - architecture, 02-04-12
 CPLD classification internal architecture 03-04-12 1

Module V FPGA - architecture 04-04-12 1

ASIC categories, full custom and semi

custom. 10-04-12 1

Class Test 12-04-12 1