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PLL Discussion Incomplete

The document discusses using phase-locked loops (PLLs) to analyze signals where rapid phase or frequency changes occur over short time periods. PLLs can effectively track these fast changes by using an oscillator to phase lock to the input signal. The document describes implementing PLLs using analog hardware components or digitally through software after analog-to-digital conversion. It provides examples of designing loop filters, both analog and digital, which are important for determining the PLL's lock range and noise characteristics.

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56 views5 pages

PLL Discussion Incomplete

The document discusses using phase-locked loops (PLLs) to analyze signals where rapid phase or frequency changes occur over short time periods. PLLs can effectively track these fast changes by using an oscillator to phase lock to the input signal. The document describes implementing PLLs using analog hardware components or digitally through software after analog-to-digital conversion. It provides examples of designing loop filters, both analog and digital, which are important for determining the PLL's lock range and noise characteristics.

Uploaded by

JHelf
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as ODT, PDF, TXT or read online on Scribd
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Phase Locked Loops in Audio

Sometimes in research in acoustics, one comes across a problem that requires


a different approach to solve. Such a problem arises when trying to examine
rapid frequency or phase changes in a signal that occur in a time short
compared to the amount of frequency shift: df*dt<1, or dphi<2pi. In these
scenarios, the FT decomposition of the signal does not provide enough detail
to tell what is going on. Although there are tricks one can use (sich as the
reassigned spectrogram, or wavelet analysis), they do not provide simple
answers to the question of what is the phase as a function of time?
One solution to this problem comes from the world of electrical engineering,
where in communications applications the phase of a signal is often used to
convey information, and the efficient detection of phase is a necessity. From
that realm comes the notion of the phase-locked loop detector. The phaselocked loop is a hardware or software construct that takes the input signal and
tries to phase lock an onboard oscillator to it. It turns out that this process is
surprisingly effective at discarding noise if an initial estimate of the signal
frequency is known. Here is a block diagram of the process:

In the diagram, the input signal is multiplied by the VCO output (a sine wave of
variable frequency), resulting in a beat frequency. If the signals are close in
frequency, the output is a low-frequency sine and the low-pass filter (LPF)
passes it and lets it control the VCO frequency, thus bringing it back closer to

the input signal frequency. If the frequencies are far apart (in comparison to
the cutoff frequency of the low-pass filter) then the VCO receives no signal and
does not try to move closer to the input signal frequency. The LPF thus
determines the lock range of the PLL, and not surprisingly also determines the
noise in the PLL, so that tailoring it to your application is important. For
frequency estimation applications it is fairly common to include an integrator in
the LPF, so as to drive the steady-state error in the frequency of the VCO to
zero. Alternatively, one can emphasize the transient response of the LPF to
follow a time-varying signal for the purpose of e.g. decoding the phase
information in it.
PLL's were initially defined in hardware, using mixers, filters and real voltagecontrolled oscillators, and then later implemented entirely on an integrated
circuit. Nowadays it is very common to find them implemented in software
following an analog-to-digital conversion of the input signal. This is an especially
effective way to go if real-time operation is not required, or if the signal is
already being digitized for archival use. They are computationally simple to
implement, although they can be difficult to tame. Some simple pseudo-code
for one is given below:

There are several well-known options for designing the first-order low-pass
filter Fa(s) . In particular we are interested in getting the denominator of Ha(s) to
the standard form
s2+2ns+2n

where n is the natural frequency of the filter and is the damping factor. This
simplifies analysis of the overall transfer function and allows the parameters
of Fa(s) to ensure stability. We are now free to choose the low pass filter Fa(s) .
There are several possibilities, but for this example we will use the active
"proportional plus integration" (PI) which has a loop filter
Fa(s)=1+2s1s

where 1 and 2 are also parameters relating to the damping factor and natural
frequency. This yields a closed-loop phase-locked loop transfer function:
2

Ha(s)=Ka*(1+s2)/[s +sKa2/1+Ka/(1+2)]/1

Converting the denominator of [eqn:loop_filter_Ha] into standard form in


[eqn:pll_denominator_standard_form] yields the following equations for 1 and 2 :
n=Ka1=n221=Ka2n2=2n

We are left with a loop filter that simply has three parameters:
n : the bandwidth of the loop filter
: the loop filter's damping factor (typically =1/20.707 )
Ka : the loop filter's gain (typically Ka is very large, on the order of 1,000)
The values 1 and 2 are derived from n , , and Ka .

Loop Filter: Converting to Digital


Now that we have a design for the analog filter Ha(s) in [eqn:loop_filter_Ha] , we
need to convert it to a digital equivalent Hd(z)so that we may simulate the PLL
using discrete signal processing. To accomplish this we will use the bilinear z transform which replaces s with 121z11+z1 (follow this link for a detailed
description). Consequently, because Ha(s) is a second-order analog
filter, Hd(z) will be a second-order digital filter of the form
Hd(z)=^(z)(z)=b0+b1z1+b2z21+a1z1+a2z2

where b0 , b1 , and b2 are known as the feed-forward coefficients


and a1 and a2 are known as the feedback coefficients (note that typically the

coefficients in Hd(z) are normalized such that a0=1 ). Figure [iirfilt_sos_diagram]


below provides a general block diagram for a basic 2nd -order filter.

Figure [iirfilt_sos_diagram]. scale:0.7 Direct form II realization for a 2nd order recursive (infinite
impulse response) filter

where the z1 blocks represent a single sample delay and the v0 , v1 ,


and v2 nodes represent memory registers.
Taking the bilinear z -transform of Ha(s) in [eqn:loop_filter_Ha] gives the digital filter
Hd(z)=Ha(s)s=121z11+z1=2Ka(1+2/2)+2z1+(12/2)z21/21z1+(1/2)z2

Putting Hd(z) in systematic form (scaling both the numerator an denominator


by 1/2 ) gives:
Hd(z)=4Ka1[(1+2/2)+2z1+(12/2)z212z1+z2]

This provides the set of digital filter coefficients:


b0b1b2===4Ka1(1+2/2),8Ka1,4Ka1(12/2),a0a1a2==121

We can verify the stability of the filter by ensuring that the filter poles (the
complex roots of the polynomial in the denominator with respect to z1 ) are
within the unit circle. A careful inspection of the polynomial in the denominator
of [eqn:loop_filter_Hd] reveals that the two conjugate roots pd and pd are not

only on the unit circle, but they are also both real-valued:
12z1+z2pdpd===(1pdz1)(1pdz1)11

The full digital phase-locked loop can be found in [digital_pll_diagram] , below.


Figure [digital_pll_diagram]. Full digital phase-locked loop

filter Fa(s) , a first-order integr

Designing the Loop Filter (Analog Domain)


The loop filter consists of three components: a first-order low-pass filter Fa(s) , a
first-order integrator Ga(s) , and a constant loop gain Ka (the
subscript a denotes "analog"). We can derive the analog transfer
function Ha(s)=^(s)/(s) considering that (s) is the input and ^(s) is the
output:
^(s)=(s)Fa(s)Ga(s)Ka
=[(s)^(s)]Fa(s)Ga(s)Ka

^(s)[1+Fa(s)Ga(s)Ka]=(s)Fa(s)Ga(s)Ka
Ha(s)=^(s)/(s) = Fa(s)Ga(s)Ka/[1+Fa(s)Ga(s)Ka]

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