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High-Throughput Interpolator Architecture For Low-Complexity Chase Decoding of Rs Codes

This paper proposes a high-throughput interpolator architecture for low-complexity Chase decoding of Reed-Solomon codes. The proposed algorithm modifies Nielson's interpolation algorithm to share common interpolation points and limit polynomial growth, reducing latency. Based on this, a low-latency architecture is derived that reduces the overall decoder latency by at least 39% compared to previous designs, for an RS(255,239) code.

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50 views

High-Throughput Interpolator Architecture For Low-Complexity Chase Decoding of Rs Codes

This paper proposes a high-throughput interpolator architecture for low-complexity Chase decoding of Reed-Solomon codes. The proposed algorithm modifies Nielson's interpolation algorithm to share common interpolation points and limit polynomial growth, reducing latency. Based on this, a low-latency architecture is derived that reduces the overall decoder latency by at least 39% compared to previous designs, for an RS(255,239) code.

Uploaded by

VigneshInfotech
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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HIGH-THROUGHPUT INTERPOLATOR

ARCHITECTURE FOR LOW-COMPLEXITY CHASE


DECODING OF RS CODES
ABSTRACT:

In this paper, high-throughput interpolator architecture for soft-decision decoding of


ReedSolomon (RS) codes based on low-complexity chase (LCC) decoding is presented. We
have formulated a modified form of the Nielsons interpolation algorithm, using some typical
features of LCC decoding. The proposed algorithm works with a different scheduling, takes care
of the limited growth of the polynomials, and shares the common interpolation points, for
reducing the latency of interpolation. Based on the proposed modified Nielsons algorithm we
have derived low-latency architecture to reduce the overall latency of the whole LCC decoder.
An efficiency of at least 39%, in terms of area-delay product, has been achieved by an LCC
decoder, by using the proposed interpolator architecture, over the best of the previously reported
architectures for an RS(255,239) code with eight test vectors.

EXISTING SYSTEM:
In each iteration, the number of coefficients of the minimum degree polynomial is
increased only by one, until it reaches a maximum of coefficients in the last iteration. So the
required number of cycles changes from

the coefficients are covered in each iteration, if the

growth of the order of polynomial is considered.

EXISTING SYSTEM ALGORITHM:


Algorithm 1 has two stages:
Stage-1 (A1) performs the polynomial evaluation (PE) or discrepancy computation.

Stage-2 (A2 and A3) performs the polynomial update (PU). There are two ways to update a
polynomial.

If the polynomial has minimum order and discrepancy is different from zero, then the
degree of the polynomial is increased by one, while the y-degree remains unchanged, (step

A3);
Otherwise, a linear combination of the two polynomials and their respective discrepancies,
and , are computed (step A2). This last updating mode doesnt modify the degree of the
polynomial. When re-encoding is applied and the maximum multiplicity is taken to be
one, the number of iterations needed in the interpolation algorithm.

EXISTING SYSTEM DRAWBACKS:

Poor latency
Less throughput

PROPOSED SYSTEM BLOCK DIAGRAM:

PROPOSED SYSTEM TECHNIQUE (ALGORITHM):


The PU and PE stages are written in serial processing style as they will be used in the
proposed architecture depicted in the next section. Coefficients of order j of the bivariate
polynomials g0(x,y) and g1(x,y). PU steps are described in A2 and A3 and the computation of
the partial values of PE is stored in AC0 and AC1. During the j-th iteration only the coefficients
of order j are updated and evaluated, so that the proposed algorithm will avoid accessing the
memory twice to obtain the coefficients for evaluating the discrepancies and updating the
polynomials. If the re-encoded points are arranged in descending order of reliability, the first 2t-n
points are the same in all the 2n test vectors. This implies that during the first 2t-n iterations
Algorithm 2 is applied to the common points.

PROPOSED SYSTEM ADVANTAGES:

High Throughput.
Low Complexity.

HARDWARE REQUIREMENT:

FPGA Spartan 3(xc3s400 pq 208)

SOFTWARE REQUIREMENTS:

ModelSim 6.4c
Xilinx ISE 13.2

REAL TIME EXAMPLE:

It can be used in wireless communication


Data storage method

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