Features

16-bit Fixed-point Digital Signal Processing (DSP) Core

Low-power Consumption:

1 mW/MIPS on 0.25-micron CMOS, 2.5V

0.6 mW/MIPS on 0.20-micron CMOS, 1.8V
High Performance:
80 MIPS at 160 MHz (Typical) on 0.25-micron CMOS, 2.5V
100 MIPS at 200 MHz (Typical) on 0.20-micron CMOS, 1.8V
Small Die Size:
2.5 mm2 on 0.25-micron CMOS
1.3 mm2 on 0.20-micron CMOS
Slow Mode and Stop Mode allow Further Power Reduction
Wide Range of Operating Voltage: 1.8V - 3.6V
High Level of Modularity:
Expandable Data and Program RAM and/or ROM
User-definable Registers
64K x 16-bit Data Address Space, 64K x 16-bit Program Address Space
Three Parallel Execution Units
Wait States are Supported to Link with Slow External Devices
Advanced Windows-based Development Tools: Macro Assembler, Linker,
C Compiler, Debugger (emulator, simulator)
Optional On-core Emulator Allows the On-core Debugger, Embedded in
the ASIC, to be Run
Optional JTAG Serial Interface for On-chip Debug (JCI Interface)

Embedded
Digital Signal
Processing
Core
OakDSPCore

Description
Atmels embedded OakDSPCore is a 16-bit general-purpose low-power, low-voltage
and high-speed digital signal processor (DSP). It is designed for mid-to-high-end telecommunications and consumer electronics applications, where low power and
portability are major requirements. Among the applications supported are digital cellular telephones, fast modems, advanced facsimile machines and hard disk drives.
OakDSPCore is available as a DSP core in Atmels standard cell library, to be utilized
as an engine for DSP-based ASICs. It is specified with several levels of modularity in
RAM, ROM and I/O blocks, allowing efficient DSP-based ASIC development.
OakDSPCore is aimed at achieving the best cost-performance factor for a given
(small) silicon area. As a key element of a system-on-chip, it takes into account such
requirements as program size, data memory size, glue logic, power management, etc.
The OakDSPCore consists of three main execution units operating in parallel: the
Computation/Bit Manipulation Unit (CBU), the Data Address Arithmetic Unit (DAAU)
and the Program Control Unit (PCU). The core also contains ROM and RAM addressing units, and Program Control Logic (PCL). All other peripheral blocks, which are
application specific, are defined as a part of the user-specific logic, implemented
around the DSP core on the same silicon die.
OakDSPCore has an enhanced set of DSP and general microprocessor functions to
meet the application requirements. The OakDSPCore programming model and
instruction set are aimed at straightforward generation of efficient and compact code.

Rev. 0876F03/01

Figure 1. OakDSPCore Symbol

RXSP<15:0>
OMEMSZ4P
RYDP<15:0>
GIXDBP<15:0>

OakDSPCore
On-core Memory

GEXDBP<15:0>

Off-core Memory

BEXTPP
GIP<15:0>

Program Memory

PESCRN<5:0>
PEDSTN<5:0>
DXAP<15:0>
PEDWP
PEDRP

PEXTIP
PPAP<15:0>
PPRP
PPWP

BFLOATDP
BFLOATPP

DMA

PRWEXTP
DOFCTRP

BIUSER0P
BIUSER1P

User I/O

CUSERO0P
CUSERO1P

LINT0P
LINT1P
LINT2P
LNMIP

PIACKN

Interrupts

BTRAPREQP

OCEM

PHI1
PHI2
LRSTP
BWAITP
BBOOTP

DOCXAP<10:0>
DOCXA10N
DRXRM1P
DWXRM1P
DOEXRM1P
DRXRM2P
DWXRM2P
DOEXRM2P
DYAN<10:0>
DYA10N
DRYRM1P
DWYRM1P
DOEYRM1P
DRYRM2P
DWYRM2P
DOEYRM2P
PMEMENP

PSTATUSP<3:0>
PTRAPAP
PBKENDP
DDTVMP
PSFTP
PDUMMYP

System

OakDSPCore
0876F03/01

OakDSPCore
Signal Description
Table 1. Pin Configuration
Signal Name

Size

Type

Description

RXSP <15:0>

16

XRAM data bus

OMEMSZ4P

Memory size 4K

RYDP <15:0>

16

YRAM data bus

GIXDBP <15:0>

16

I/O

Internal data bus

DOCXAP <10:0>

11

On-core XRAM address

DOCXA10N

On-core XRAM address - bit 10

DRXRM1P

On-core XRAM read (lower 1K)

DWXRM1P

On-core XRAM write (lower 1K)

DOEXRM1P

On-core XRAM output enable (lower 1K)

DRXRM2P

On-core XRAM read (upper 1K)

DWXRM2P

On-core XRAM write (upper 1K)

DOEXRM2P

On-core XRAM output enable (upper 1K)

DYAN <10:0>

11

On-core YRAM address

DYA10N

On-core YRAM address - bit 10

DRYRM1P

On-core YRAM read (lower 1K)

DWYRM1P

On-core YRAM write (lower 1K)

DOEYRM1P

On-core YRAM output enable (lower 1K)

DRYRM2P

On-core YRAM read (upper 1K)

DWYRM2P

On-core YRAM write (upper 1K)

DOEYRM2P

On-core YRAM output enable (upper 1K)

PMEMENP

Data memory enable

GEXDBP <15:0>

16

I/O

External data bus

PESRCN <5:0>

Source bus

PEDSTN <5:0>

Destination bus

DXAP <15:0>

16

Off-core XRAM address

PEDWP

Data write

PEDRP

Data read

BEXTPP

External program indication

GIP <15:0>

16

I/O

Instruction data

PEXTIP

MOVP instruction indication

PPAP <15:0>

16

Program address

On-core Memory

Off-core Memory

Program Memory

3
0876F03/01

Table 1. Pin Configuration (Continued)

Signal Name

Size

Type

Description

PPRP

Program read

PPWP

Program write

BFLOATDP

Float DXAP bus control

BFLOATPP

Float PPAP bus control

PRWEXTP

Read or write to/from external registers

DOFCTRP

Off core data transaction

BIUSER0P

User input 0

BIUSER1P

User input 1

CUSERO0P

User output 0

CUSERO1P

User output 1

LINT0P

Interrupt 0

LINT1P

Interrupt 1

LINT2P

Interrupt 2

LNMIP

Non-maskable Interrupt

PIACKN

Interrupt acknowledge

BTRAPREQP

TRAP interrupt

PSTATUSP <3:0>

Internal status (used by the OCEM module)

PTRAPAP

Trap active indication

PBKENDP

Block repeat end

DDTVMP

Data value match

PSFTP

Software trap indication

PDUMMYP

Dummy fetch (used by the OCEM module)

PHI1

Phase1 Clock

PHI2

Phase2 Clock

LRSTP

Reset

BWAITP

Wait state indication

BBOOTP

BOOT indication

DMA

User I/O

Interrupts

OCEM

System

OakDSPCore
0876F03/01

OakDSPCore
OakDSPCore
Architecture

As shown in Figure 2, the OakDSPCore consists of three main execution units operating
in parallel:

The Computation/Bit Manipulation Unit (CBU)

The Data Address Arithmetic Unit (DAAU)

The Program Control Unit (PCU)

The OakDSPCore also supports four user-definable registers, enabling future expansion of the core residing in off-core glue logic. The user defined registers are part of the
core register set, meaning that they can be accessed by most OAK instructions.
Figure 2. OakDSPCore Block Diagram
Y-Address Bus

X-Address Bus

On-Core Memory

DAAU

X-RAM

Y-RAM

User
Defined
Register

Stack-Pointer

X-Data Bus
Y-Data Bus

CBU
RESET

BMU

CU

Barrel Shifter

Multiplier

Status
Registers

BPI
INT0

BFO

ALU

PCU
INT1
INT2

B-Accumulator 0
B-Accumulator 1

Accumulator 0
Accumulator 1

NMI
Program Address Bus
Program Data Bus

5
0876F03/01

Computation/Bit
Manipulation Unit

The Computation/Bit Manipulation Unit (CBU) contains three main elements:

The Computation Unit (CU)

The Bit Manipulation Unit (BMU).

The Saturation Unit, which is shared by the CU and the BMU units.

Figure 3. Computation and Bit Manipulation Unit Block Diagram

X Data Bus

Y Data Bus

Computation Unit

Bit Manipulation Unit

Multiplier
P

Scaling Shifter

EXP

SV

Barrel
Shifter

Bit Field
Operation

ALU

MUX

Accumulator B0
Accumulator B1

Swap

Accumulator A0
Accumulator A1

Saturation Unit

The CU consists of a 16- by 16-bit parallel 2s complement multiplier, supporting single

and double precision multiplication, a 36-bit Arithmetical and Logical Unit (ALU) and two
36-bit A-accumulators with access to the two additional B-accumulators of the BMU.
The OakDSPCore can perform a single-cycle Multiply-Accumulate (MAC) instruction,
and has support for double precision multiplication. A single-cycle division step is
supported.
The Arithmetic Logic Unit (ALU) performs all arithmetic and logical operations on data
operands. It is a 36-bit, single-cycle, non-pipelined unit. A maximum or minimum operation is available.
The BMU consists of a full 36-bit barrel shifter, a Bit-Field Operation (BFO) unit, a special hardware (EXP) for exponent calculation, and two 36-bit B-accumulators with
access to the two A-accumulators of the CU. Extension nibbles of the B-accumulators
offer protection against 32-bit overflows. The Shift Value (SV) register is a 16-bit register
used for shifting operation and exponent calculation.
Context switching (swapping) between the two sets of accumulators is supported.

OakDSPCore
0876F03/01

OakDSPCore
Saturation arithmetic is provided to selectively limit overflow from the high portion of an
accumulator to the extension bits. When necessary the saturation logic substitutes a
limited data value having maximum magnitude and the same sign as the source
accumulator.

Data Address
Arithmetic Unit

The Data Address Arithmetic Unit (DAAU) performs all address storage and effective
address calculations necessary to address data operands in data and program memories. It also supports the software stack pointer. This unit operates in parallel with other
core resources to minimize address generation overhead. The DAAU contains six 16-bit
address registers for indirect addressing, two 16-bit configuration registers for modulo
and increment or decrement step control, and a base register for supporting index
addressing. In addition, it contains a 16-bit stack pointer register and four alternative
bank registers that are supported by an individual bank exchange. A 16-bit minimum
and maximum pointer latching register also is contained.
The DAAU can generate two 16-bit addresses every instruction cycle. These can be
post-modified by two modifiers: linear and modulo modifier. The address modifiers allow
the creation of data structures in memory for circular buffers, delay lines, FIFOs, another
pointer to the software stack, etc.

Program Control Unit

The Program Control Unit (PCU) performs instruction fetch, instruction decoding, exception handling, hardware loop control, wait state support and on-chip emulation support.
In addition, it controls the internal program memory protection.
The PCU contains the Repeat and Block-Repeat unit, and two 16-bit directly accessible
registers: the Program Counter and the Loop Counter of the block-repeat unit.

Instruction Set

The OAK instruction set is balanced between DSP and control functions, thus permitting
both DSP and high-speed control activities.
There are a total of 89 instructions. All have been carefully designed to produce compact code. The OakDSPCore has an internal four-stage pipeline which continually
performs concurrent instruction fetch, decode fetch, operand fetch and instruction execution. This allows instruction execution to overlap, thus the effective execution time for
most instructions is one cycle. Of particular significance are the repeat and block repeat
(four nested levels) capabilities.
This instruction set optimizes the OakDSPCore for algorithms such as Viterbi decoding,
adaptive filtering, and cellular phone applications.

7
0876F03/01

On-Chip Emulation

The OakDSPCore has the capability to be combined with an On-Chip Emulation Module
(OCEM). The OCEM provides hardware emulation and program flow trace buffering.
Hardware emulation allows breakpoints due to a pre-defined condition such as program
or data address match, single stepping, etc.
Program flow buffer records, during run time, those instruction addresses that cause a
non-continuity in the program flow. These addresses are kept in a FIFO within the
OCEM block and used afterwards to re-construct the complete program flow graph.

Development Tools

Development tools are a critical element in core-based ASIC design as they affect the
design cycle and the time-to-market. For ease of development of DSP-based applications, the OakDSPCore is supplied with a comprehensive set of hardware and software
tools, and a development platform for rapid prototyping. These feature a familiar design
technology, full-speed and real-time emulation/simulation, easy of use and interactivity.

Hardware Development
Tools

The OakDSPCore hardware tools include the ODKit stand-alone board, ODKit Accelerator, and the Combo Debug Interface (CDI). The ODKit/CDI is a unified line of
development tools which provides the user the ability to develop and debug an application-specific Oak-based system in the same software environment.
The ODKit also has a reduced version called the Accelerator. The Accelerator provides
the user the ability of very fast turn-key development of firmware (and application specific software) as well as a hardware acceleration engine for heavy simulations. The
Accelerator doesnt provide a prototyping ability. The stand-alone ODKit provides the
user an ability of fast prototyping of application specific hardware. So three different
products are established in the product line: the Accelerator, the stand-alone ODKit and
the CDI. The last two devices use an ISA Extender card for the PC host link, while the
Accelerator must be plugged into an ISA bus connector of the host PC.
The ODKit is designed for prototyping during COMBO (Oak based ASIC) development
stage, whereas the CDI is designed for COMBO debug and/or re-targeting stages. Both
devices support a stand-alone (demo mode) operation. Both the stand-alone ODkit and
ODkit accelerator card include an Oak development chip, program and data memory,
boot logic, EPROM socket, dual-ported monitor MAILBOX memory, and CODEC with
audio input and output connectors.
The CDI contains the PC ISA host interface, dual-ported monitor MAILBOX memory,
program memory, EPROM socket, boot logic, C-bus interface and target connector
interface. It does not include the Oak development chip or Oak socket like the Odkit
boards. The CDI would be used for hardware verification/debug of an Oak based ASIC
or ASSP that has a different package than the Oak development chip.

OakDSPCore
0876F03/01

OakDSPCore
Software Development
Tools

The OakDSPCore command line software tools include a COFF macro assembler and
linker, and ANSI C compiler. The GUI based tools include the COFF symbolic debugger
and ASSYST simulator. The ASSYST simulator is used to simulate external hardware in
simulation mode before actual target hardware is available.
The debugger can operate in either emulation or simulation modes on a PC, depending
upon whether Oak-based target hardware is attached. The debugger supports source
level debugging in assembly, C/C++, or mixed assembly and C/C++ modes. It also
includes a disassembler, an in-line assembler, and an application profiler. In simulation
mode the application profiler indicates memory usage, program flow, instruction usage,
real time consumption and more. The software tools are available for Windows 3.1, Windows 95, and Windows NT operating systems. As a UNIX/Motif compatible
application, it can run on Sun SPARC workstations in simulation mode only.
Figure 4. Windows User Interface of the OAK Development Kit

9
0876F03/01

Atmel Headquarters

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International:
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http://www.atmel.com

Web Site
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1-(408) 436-4309

Atmel Corporation 2001.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Companys standard warranty
which is detailed in Atmels Terms and Conditions located on the Companys web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmels products are not authorized for use as critical
components in life support devices or systems.
Marks bearing

and/or

are registered trademarks and trademarks of Atmel Corporation.

OakDSPCore, TeakDSPCore, PalmDSPCore and OCEM are registered trademarks of DSP Group Inc.
Other terms and product names in this document may be trademarks of others.

Printed on recycled paper.

0876F03/01/0M