MEMORY AND I/O DEVICES

INTRODUCTION
Memory-mapped I/O (MMIO) and port-mapped I/O (PMIO) (which is also called
isolated I/O) are two complementary methods of performing input/output (I/O) between the
CPU and peripheral devices in a computer. An alternative approach is using dedicated I/O
processors, commonly known as channels on mainframe computers, which execute their own
instructions.
Memory-mapped I/O (not to be confused with memory-mapped file I/O) uses the
same address space to address both memory and I/O devices. The memory and registers of
the I/O devices are mapped to (associated with) address values. So when an address is
accessed by the CPU, it may refer to a portion of physical RAM, but it can also refer to
memory of the I/O device. Thus, the CPU instructions used to access the memory can also be
used for accessing devices. Each I/O device monitors the CPU's address bus and responds to
any CPU access of an address assigned to that device, connecting the data bus to the desired
device's hardware register. To accommodate the I/O devices, areas of the addresses used by
the CPU must be reserved for I/O and must not be available for normal physical memory. The
reservation may be permanent or temporary. An example of the latter is found in the
Commodore 64, which uses a form of memory mapping to cause RAM or I/O hardware to
appear in the $D000-$DFFF range.
Port-mapped I/O often uses a special class of CPU instructions designed specifically
for performing I/O, such as the in and out instructions found on microprocessors based on the
x86 and x86-64 architectures. Different forms of these two instructions can copy one, two or
four bytes (outb, outw and outl, respectively) between the EAX register or one of that
register's subdivisions on the CPU and a specified I/O port which is assigned to an I/O
device. I/O devices have a separate address space from general memory, either accomplished
by an extra "I/O" pin on the CPU's physical interface, or an entire bus dedicated to I/O.
Because the address space for I/O is isolated from that for main memory, this is sometimes
referred to as isolated I/O.

OVERVIEW
Different CPU-to-device communication methods, such as memory mapping, do not
affect the direct memory access (DMA) for a device, because, by definition, DMA is a
memory-to-device communication method that bypasses the CPU.
Hardware interrupts are another communication method between the CPU and
peripheral devices, however, for a number of reasons, interrupts are always treated separately.
An interrupt is device-initiated, as opposed to the methods mentioned above, which are CPUinitiated. It is also unidirectional, as information flows only from device to CPU. Lastly, each
interrupt line carries only one bit of information with a fixed meaning, namely "an event that
requires attention has occurred in a device on this interrupt line".
Memory-mapped I/O is preferred in x86-based architectures because the instructions
that perform port-based I/O are limited to one register: EAX, AX, and AL are the only
registers that data can be moved into or out of, and either a byte-sized immediate value in the
instruction or a value in register DX determines which port is the source or destination port of
the transfer.Since any general-purpose register can send or receive data to or from memory
and memory-mapped I/O, memory-mapped I/O uses fewer instructions and can run faster
than port I/O. AMD did not extend the port I/O instructions when defining the x86-64
architecture to support 64-bit ports, so 64-bit transfers cannot be performed using port I/O.
MEMORY BARRIERS
Since the caches intermediate accesses to memory addresses, data written to different
addresses may reach the peripherals' memory or registers out of the program order, i.e. if
software writes data to an address and then writes data to another address, the cache write
buffer does not guarantee that the data will reach the peripherals in that order. It is the
responsibility[clarification needed] of the software to include memory barrier instructions
after the first write, to ensure that the cache buffer is drained before the second write is
executed.Memory-mapped I/O is the cause of memory barriers in older generations of
computers, which are unrelated to memory barrier instructions. The 640 KB barrier is due to
the IBM PC placing the Upper Memory Area in the 6401024 KB range within its 20-bit
memory addressing.

INTRODUCTION TO MEMORY TYPES

Many types of memory devices are available for use in modern computer systems. As
an embedded software engineer, you must be aware of the differences between them and
understand how to use each type effectively. In our discussion, we will approach these
devices from the software developer's perspective. Keep in mind that the development of
these devices took several decades and that their underlying hardware differs significantly.
The names of the memory types frequently reflect the historical nature of the development
process and are often more confusing than insightful. Figure 1 classifies the memory devices
we'll discuss as RAM, ROM, or a hybrid of the two.

TYPES OF RAM
The RAM family includes two important memory devices: static RAM (SRAM) and
dynamic RAM (DRAM). The primary difference between them is the lifetime of the data
they store. SRAM retains its contents as long as electrical power is applied to the chip. If the
power is turned off or lost temporarily, its contents will be lost forever. DRAM, on the other
hand, has an extremely short data lifetime-typically about four milliseconds. This is true even
when power is applied constantly.
In short, SRAM has all the properties of the memory you think of when you hear the
word RAM. Compared to that, DRAM seems kind of useless. By itself, it is. However, a
simple piece of hardware called a DRAM controller can be used to make DRAM behave
more like SRAM. The job of the DRAM controller is to periodically refresh the data stored in
the DRAM. By refreshing the data before it expires, the contents of memory can be kept alive
for as long as they are needed. So DRAM is as useful as SRAM after all.
When deciding which type of RAM to use, a system designer must consider access
time and cost. SRAM devices offer extremely fast access times (approximately four times
faster than DRAM) but are much more expensive to produce. Generally, SRAM is used only
where access speed is extremely important. A lower cost-per-byte makes DRAM attractive
whenever large amounts of RAM are required.
TYPES OF ROM
3

Memories in the ROM family are distinguished by the methods used to write new data
to them (usually called programming), and the number of times they can be rewritten. This
classification reflects the evolution of ROM devices from hardwired to programmable to
erasable-and-programmable. A common feature of all these devices is their ability to retain
data and programs forever, even during a power failure.
INPUT/OUTPUT DEVICES
MEMORY MAPPED I/O
I/O Port addressing is not the only way the processor can communicate with external
devices however. Another commonly used technique is called memory mapped I/O. In this
case, instead of asserting the I/O pin and addressing a data port, the processor just accesses a
memory address directly. The external device can have a small amount of RAM or ROM that
the processor just reads or writes as needed.
This technique has been used for years with many devices that require large amounts
of data, such as video adapters. Instead of feeding data a byte at a time through a couple of
data I/O ports, now the processor has the ability to handle large amounts of data quickly by
just access special RAM. Many times dual-ported RAM is used when two processors must be
both be able to access the memory simultaneously.
DIRECT MEMORY ACCESS
One technique that has been used for years to speed transfer of data from main
memory to an external device's memory is the direct memory access feature (DMA). The
processor on the external device executes DMA transfers, without any assistance from the
main processor. The processors must cooperate for this to work obviously. While the DMA
transfer is in progress, the main processor is free to tend to other tasks, but should not attempt
to modify the information in the buffer being transfer, until the transfer is complete.
The setup for this is fairly straightforward. The main processor generally initiates the
DMA transfer by sending one or more instructions to a data port monitored by the external
processor.

CONCLUSION

The instructions must include a direction (to or from main memory), a memory
address, and a length at a minimum. Keep in mind that many DMA enabled systems have a
limit on the maximum size transfer allowed (often 64K).Once the transfer is stared, the main
processor is free to tend to other tasks. The external processor will take over the address and
data lines periodically and execute the DMA transfer. Once the transfer is complete, the
external device usually notifies the main processor of this by raising an interrupt request.
DMA's main advantage is that the main processor does not have to transfer data into one of
its register, then save that to a memory address for each and every byte of data. Another
advantage is the fact that while the DMA transfer is in progress, the CPU is free to work on
other tasks. This leads to an apparently overall increase in speed.

REFERENCES

https://en.wikipedia.org/wiki/Memory-mapped_I/O
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corner/4023326/Introduction-to-Memory-Types
http://www.dauniv.ac.in/downloads/EmbsysRevEd_PPTs/Chap_3Lesson01EmsysNe

w.pdf
http://www.bamafolks.com/randy/students/embedded/io_devices.html
https://www.pantechsolutions.net/microcontroller-boards/implementation-of-trafficlight-controller-using-8086?virtuemart_category_id=1