Section 7.1: ADC Characteristics This section will explore ADC generally. First, we describe some general aspects of the ADC itself, then focus on the functionality of some important pins in ADC. ADC devices Analog-to-digital converters are among the most widely used devices for data acquisition. Digital computers use binary (discrete) values, but in the Physical world everything is analog (continuous). Temperature, pressure (wind or liquid), humidity, and velocity are a few examples of physical quantities that we deal with every day. A physical quantity is converted to electrical (voltage, current) signals using a device called a transducer. Transducers used to generate electrical outputs are also referred to as sensors. Sensors for temperature, velocity, pressure, light, and many other natural physical Quantities produce an output that is voltage (or current). Therefore, we need an analog-to-digital converter to translate the analog signals to digital numbers so that the microcontroller can read and process the numbers. See Figures 7-1 and 7-2. i Physical sigh Signal ‘0 Figure 7-1: Microcontroller Connection to Sensor via ADC Veet Figure 7-2: An &-bit ADC Block Diagram Some of the major characteristics of the ADC ResolutionThe ADC has r-bit resolution, where n can be 8, 10, 12, 16, or even 24 bits. Higher-resolution ADCs provide a smaller step size, where step size is the smallest change that can be discerned by an ADC. Some widely used resolutions for ADCs are shown in Table 7-1. Although the resolution of an ADC chip is decided at the time of its design and cannot be changed, we can control the step size with the help of what is called V;.. This is discussed below. (tinea Bors SV /256 = 19.53 mV 5V /1024 = 4.88 mV 2mv_| 5V /65,536 = 0.076 mV Table 7-1: Resolution versus Step Size for ADC (Vref = 5V) Vref Vref is an input voltage used for the reference voltage. The voltage connected to this pin, along with the resolution of the ADC chip, determine the step size. For an 8-bit ADC, the step size is Vref / 256 because it is an 8-bit ADC, and 2 to the power of 8 gives us 256 steps. See Table 7-1. For example, if the analog input range needs to be 0 to 4 volts, Vref is connected to 4 volts. That gives 4 V / 256 = 15.62 mV for the step size of an 8-bit ADC. In another case, if we need a step size of 10 mV for an 8-bit ADC, then Vier = 2.56 V, because 2.56 V / 256 = 10 mV. For the 10-bit ADC, if the Vier = 5V, then the step size is 4.88 mV as shown in Table 7-1. Tables 7-2 and 7-3 show the relationship between the V,ey and step size for the 8 and 10-bit ADCs, respectively. In some applications, we need the differential reference voltage where Vier = Vrer (4) ~ Vref (-): Often the Vier.) pin is connected to ground and the Vier (4) Pin is used as the Vie. Vrer (V) in Range (V) Step Size (mV) 5.00 Oto5 5/256 = 19.53 4.00 Oto4 a = 3.00 Oto3 2.56 Oto 2.56 2.56 / 256 = 10 2.00 Oto2 2/256 =7.81 1.28 Oto 1.28 1.28/256=51.00 Oto1 1/256 = 3.90 In an 8-bit ADG, step si res 256 Pest ie ME S E Table 7-2: Vref Relation to Vin Range foran &-bit ADC Vref (V) fro) Step Size (mV) Otos 5/1024 = 4.88 Oto 4.096 4.096 / 1024 = 4 __0to3 3/1024 =2.93 Oto 2.56 2.56 /1024 = 2.5 Oto2 (i tore eats | Oto 1.024 1.024 / 102 Note: In a 10-bit ADC, step size is V;.y/1024 |Table 7-3: Vref Relation to Vin Range for an 10-bRADC Conversion time In addition to resolution, conversion time is another major factor in selecting an ADC. Conversion time is defined as the time it takes the ADC to convert the analog input to a digital number. The conversion time is dictated by the clock source connected to the ADC in addition to the method_used for data conversion and technology used in the fabrication of the ADC. Digital data output In an 8-bit ADC we have an 8-bit digital data output of DO-D7, while in the 10-bit ADC the data output is D0-D9. To calculate the output voltage, we use the following formula: Dour = Vin / StepSize where Dou: = digital data output (in decimal), Vj, = analog input voltage, and step size (resolution) is the smallest change, which is V,.4/256 for an 8-bit ADC. Figure 7-3 shows a simple 2-bit ADC. In the circuit, the voltage between Vref(+) and Vref) is divided into 4 since resistors have the same values. As a result, the step size is (Viet) - Veg.) / 4. yeVin. Powr " — 0 o oti, sy, Vreres (a) The Relationship, (©) The internal block clagram of between Ve and Dae ‘a simple 2-8 ADC Figure 7-3: A Simultaneous 2-bit ADC If Vin is below step size all the comparators send out zeros. When Vin is between step size and step size x 2, the lowest comparator sends out 1 and the encoder gives 01, If Vin is between step size * 2 and step size x 3, the second comparator and the first comparator sends out 1. Since the encoder is hierarchical priority, it sends out the highest value in cases that more than 1 input is high. As a result, 2 (10 in binary) will be sent out. When Vin is bigger than step size x 3, the third comparator becomes high and 3 will be sent out. See Example 7-1. This data is brought out of the ADC chip either one bit at a time (serially), or in one chunk, using a parallel line of outputs. This is discussed next. VX ———————— Example 7-1 For a given 8-bit ADC (e.g. ADC0848), we have Vier = 2.56 V. Calculate the DO- D7 output if the analog input is: (a)1.7 V, and (b) 2.1 V.Solution: Since the step size is 2.56/256 = 10 mV, we have the following. (a)Dour = 1.7V/10 mv = 170 in decimal, which gives us 10101011 in binary for 07-0. (b)Doyy = 2.1V/10 mv = 210 in decimal, which gives us 11010010 in binary for D7-Do. The ADC chips are either parallel or serial. In parallel ADC, we have 8 or more pins dedicated to bringing out the binary data, but in serial ADC we have only one pin for data out. The DO-D7 data pins of the 8-bit ADC provide an 8-bit parallel data path between the ADC chip and the CPU. In the case of the 16-bit parallel ADC chip, we need 16 pins for the data path. In order to save pins, many 12- and 16-bit ADCs use pins DO-D7 to send out the upper and lower bytes of the binary data. In recent years, for many applications where space is a critical issue, using such a large number of pins for data is not feasible. For this reason, serial devices such as the serial ADC are becoming widely used. While the serial ADCs use fewer pins and their smaller packages take much less space on the printed circuit board, more CPU time is needed to get the converted data from the ADC because the CPU must get data one bit at a time, instead of in one single read operation a¢ with the Parallel ADC. ADCO848 is an example of a parallel ADC with 8 pins for the data Output, while the MAX1112 is an example of a serial ADC with a single pin for Pour Figures 7-4 and 7-5 show the block diagram for ADCO848 and MAX1112.CHt ADCo84s CHE Figure 7-4: ADCO848 Parallel ADC Block Diagram CS SCLK Vo CHO MAX1112 cH7 Dour]-——> REFIN REFOUT Din SHON ssTRB Figure 7-5: MAX1112 Serial ADC Block Diagram Analog input channels Many data acquisition applications need more than one analog input for ADC. For this reason, we see ADC chips with 2, 4, 8, or even 16 channels on a single chip. Multiplexing of analog inputs is widely used as shown in the ADC848 and MAX1112. In these chips, we have 8 channels of analog inputs, allowing us to monitor multiple quantities such as temperature, pressure, flow, and so on. Nowadays, some ARM microcontroller chips come with 16. channel on-chip ADC. Start conversion and end-of-conversion signals For the conversion to be controlled by the CPU, there are needs for start conversion (SC) and end-of-conversion (EOC) signals. When SC is activated,the ADC starts converting the analog input value of V;, to a digital number. The amount of time it takes to convert varies depending on the conversion method. When the data conversion is complete, the end-of-conversion signal notifies the CPU that the converted data is ready to be picked up. Successive Approximation ADC Successive Approximation is a widely used method of converting an analog input to digital output. It has three main components: (a) successive approximation register (SAR), (b) comparator, and (c) control unit. See the figure below. | DAC (Digital-to-Analog | Your GSavertn ol Analog Input + : | Soe Comparator Vevey yyy Binary Output Figure 7-6: Successive Approximation ADC The successive approximation register is loaded with only the most significant bit set at the start. An internal digital-to-analog converter converts the value of SAR to an analog voltage which is used to compare to the input voltage. If the input voltage is higher, the bit is kept. If the voltage is lower, the bit is cleared. The next bit is tried and the DAC and compare are exercised. This process is repeated for all bits of the SAR. Assuming a step size of 10 mV, the &bit successive approximation ADC will go through the following steps to convert an input of 1 Volt: (1) It starts with binary number 10000000. Since 128 x 10 mV = 1.28 V is greater than the 1 V input, bit 7 is cleared (dropped). (2) 01000000 gives us 64 x 10 mV = 640 mV and bit 6 is kept since it is smaller than the 1 V input.(3) 01100000 gives us 96 x 10 mV = 960 mV and bit 5 is kept since it is smaller than the 1V input, (4) 01110000 gives us 112 * 10 mv = 1120 mV and bit 4 is dropped since it is greater than the 1 V input (5) 01101000 gives us 108 x 10 mV = 1080 mV and bit 3 is dropped since it is greater than the 1 V input. (6) 01100100 gives us 100 x 10 mV = 1000 mv = 1 V and bit 2 is kept since it is equal to input. Even though the answer is found it does not stop (7) 011000110 gives us 102 x 10 mv = 1020 mV and bit 1 is dropped since it is greater than the 1 V input. (8) 01100101 gives us 101 x 10 mV = 1010 mv and bit 0 is dropped since it is greater than the 1 V input. Notice that the Successive Approximation method goes through all the steps even if the answer is found in one of the earlier steps. The advantage of the Successive Approximation method is that the conversion time is fixed since it has to go through all the steps. . Review Questions 1. Give two factors that affect the step size calculation. 2. The ADCO848 is a(n) -bit converter. 3. True or false. While the ADCO848 has 8 pins for Dout, the MAX1112 has only one Dout pin. 4. Find the step size for an 8-bit ADC, if Vref = 1.28 V. 5. For question 4, calculate the output if the analog input is: (a) 0.7 V, and (b) 1V.Section 7,2: ADC Programming with the Tiva TM4C123G Because the ADC is widely used in data acquisition, in recent years an increasing number of microcontrollers have on-chip ADC modules. In this fection we discuss the ADC feature of the TI Tiva TM4C1236 and show how it is programmed. These ADC modules have 12-bit resolution. To Program them, we need to lk —— ADC RECERDES module ansols | aocemux Aint] rocssubsea / Figure 7-7: Simplified Block Diagram of a Tl ADC Module In this section, we examine some of these registers and show how to program the ADC. Enabling Clock to ADCFirst thing we need to do is to enable the clock to the ADCO or ADC1. Bit 0 and bit 1 of RCGCADC register are used to enable the clock to ADCO and ADC1 modules, respectively. The RCGCADC is part of the System Control register and is located at base address of Ox400FE000 with offset 0x638. That means, the RCGCADC is located at physical address of Ox400FE638 (Ox400FE000 + 0x638 = 0x400FE638) in memory map. See Figure 7-8. El rar <0: TT i [ro] ove oo a Figure 7-8: ADC Run Mode Clock Gating Control (RCGCADC) The Sample Sequencer The Sample Sequencer is a part of the ADC module that moves the conversion result of the ADC to one of the FIFOs. There are 4 Sample Sequencers. They are called SS3, SS2, SS1, and SSO. Each one of them is associated with a FIFO. The FIFOs have different sizes so the sample sequencers have different lengths of sequences. The longest sequence has 8 samples and the shortest has only one. Table 7-4 shows the relation between the sample sequencers and FIFO sizes. Sequencer eT alee) $so 8 8 SS1 4 4 ss2 4 at 4 S83 1 Te Table 7-4: Samples and FIFO Depth of Sequencers _ In this section, we will use the SS3 with a single sample. We use ADCACTSS (ADC Active Sample Sequencer) to enable the SS3. When bit 3 (ASEN3) is set to 1 the SS3 is enabled. We must disable the SS3 before configuring the sample sequencer so that no erroneous events occur during initialization. After the initialization is done, we must enable it to use it. eee pi ps oz moo Apcactss: Uy [se ea AS ena fsentfasen] 0x00 Type RO RO RO RO ro RW RW RW RWFigure 7-9: ADC Active Sample Sequencer (ADCACTSS) Start Conversion trigger options There are many start-conversion (trigger) options. Among them are using timer, PWM, analog comparator, external signal from GPIO, and cattware. The selection of trigger for SS3 is done via the bits 15-12 of ADCEMUX register. The default is software and that is what we use in this section. pat is p1 012 D12 ptt 019 Da OB 07 08 DS OF DP D2 D1 DO nex a ea a Type RO an OW RT RY RAT ROY WR EW WR LW LW RY eux bit select the tigger source for Sample Sequencer x. By default the fla is Ox0 which Heane me Peale vergion begins when the SSrn bit ofthe ADCPSSI register is sat by software, The following aoe cows the available choices for trigger. For more information see the datasneot Emxvalue | Trigger source 050 Processor (default) Ont ‘Analog Comparator 0 2 ‘Analog Comparator 1 Ce Ox External (GPIO Pins) OS Timer 0x6 Pw generator 0 Ont PWM generator 1 8 PWM generator 2 x8 ‘PWM ganerator 3 OF “Aways (continuously semple) Figure 7-10: ADC Event Multiplexer Select (ADCEMUX) after we select the software option bit (which is the default) bit in the ADCEMUX, we must use bit D3 of ADCPSSI register to start a conversion every time we want a new reading from the ADC input channel,6 ew 200r39: aT TN 7 [sr [ST [oer] ozo moe —_ SS SSx vi ‘Trigger source age Figure 7-11: ADC Processor Sample Sequence Initiate (ADCPSSI) Notice that we can trigger the SS3 option only if we have enabled the $83 in the ADCACTSS register. Choosing V,,, input channel The channel selection is done through the ADCSSMUXn (n=0,1,2,3) registers. For the $S3, the ADCSSMUX3 is used. Since $S3 only handles single conversion, bits 3 - 0 are used to specify the analog channel to be converted. The number of available channels in the TI Tiva TM4C123G varies among the family members. In the case of TI Tiva TM4C123GH6PM, there are 12 channels. They are designated as AINO (analog input 0) to AIN11 (analog input 11). Their designated pins are shown in Table 7-5. Pin = Pin Name _ Description Number _ ‘INO ADCinputO” PES 6 AIN1 —ADCinput1 _PE2 7 AIN2 WADCinput2 PEL 8 AIN3: ADC input 3 PEO 9 AINA ll) ADC input 4 /—llPD3 64 AINS ADC input 5 PD2 63 AING —ADCinputé PDI 62 AIN7 PDO 61 ‘AINE PES 60 AINS ADC input 9 PES 59 INO ADClinput 107" Pe4 58 AINI1 ADC input 11 PBS 57 “Table 7-5: Analog input pin assignment in Tl Tiva TMC123GH6PMp31 be os bz tbo cai ee (tie eee bec ea [os | wuxo | Samia input Suiect Figure 7-12: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3) Polling or interrupt The end-of-conversion is indicated by a flag bit in the ADCRIS (ADC Raw Interrupt) register. Upon the completion of conversion for the $$3, the D3 bit (INT3) flag goes high. By polling this flag, we know if the conversion is complete and we can read the value in ADCSSFIFO3 register. We can also use an interrupt to inform us that the conversion is complete but that will require us to set up the interrupt mask ADCIM. By default, the interrupts are not enabled. ‘na ] Ox008 '$S0 Raw interrupt Status ‘0: An interrupt has not occurred © | iro | 4:Asampie hae comploted corversion and the respective ADCSSCTLO len bit is sot, enabling a raw interrupt. "Noto: Tis bits cleared by writing 2 tothe INO bit inthe ADCISC register. 1 81 Raw Interrupt Status 2 $82 Raw Interrupt Status 3 [Tara] S89 Raw Interrupt status Digital Comparator Raw interrupt Status el wine bits in the register are clear 4; At least one bit in the ADCOCISG rogistor fe set, mesning that cial Figure 7-13; ADC Raw Interrupt Status (ADCRIS) ADC Data result Upon the completion of conversion, the binary result is placed in the ADCSSFIFOn register. Since we are using $S3, we need to read the result fromADCSSFIFO3 register. This is 32-bit register but only the lower 12 bits are used. a = - [78k [Name [Description [o-tt] pata [Conversion Result ata] Figure 7-14: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3) Clearing end-of-conversion flag After reading the data from the ADCSSFIFOx register, we must clear the INT3 flag bit in ADCRIS register so that we may detect another conversion complete. The raw interrupt flag in ADCRIS is cleared by writing to ADCISC (ADC Interrupt Status and Clear) register. By writing a 1 to bit 3 (IN3 bit) of ADCISC, the interrupt flag is cleared and we can do another conversion again. Sa ee too eitimtonsrcmccrcne temas anata noe ‘Note Tis bie an the Bt aso chars the INR bitin tho oar by mrtg a1. Caring te Bia eb ‘Digtat Comparator interupt Status on 88x "rN nr ha cero ah tra aa $ Seman i As nace Scone te ACL sepesse we itr Tob casey wting 9 Caring abt ace a tw NDC nt Figure 7-15: ADC Interrupt Status and Clear (ADCISC) Differential versus Single-Ended In some applications, our interest is in the differences between two analog signal voltages (the differential voltages). Rather than converting two channels and calculate the differences between them, the Tiva TM4C123G has the option of converting the differential voltages of two analog channels. The bit 0 of ADCSSCTL3 (ADC Sample sequence Control 3) register allows us to enable the differential option. Upon Reset, the default is the single-endedinput and we will leave it at that. The pairing of the analog inputs for differential is hardwired. Table 7-6 shows the pairing of the ADC input channels for differential option. Pcie eee | 0 ani e 1 2and3 = 2 __4and5 3 Gand7 _ 4 Bando | 5 10 and 11 ‘Table 7-6: ADC channel pairing for differential The other bits in ADCSSCTL3 register are bit 1 (ENDO), bit 2 (IEO), and bit 3 (TS) bits. On some of the ADC inputs, we have an internal temperature sensor embedded into the chip. Making bit 3 = 1, reads the temperature sensor value inside the chip itself. Since we are using one sample in the SSE3, we must enable the bit 1 (ENDO) to let ADC know that first sample is the only sample and there is no sample coming after that. Bit 2 (IEO) is the Interrupt enable. It causes the raw interrupt flag to set when this sample conversion is completed. However, in order to redirect the end-of-conversion to the NVIC interrupt controller, we must also enable the bit in ADCIM register, as we will see soon. It must be noted, even if we do not want to use interrupt, we must still set EO = 1, in order to post the raw interrupt flag for polling the conversion complete.ba bse ot Type RO nO RW RW CRW ox0A4 Description Sa rraret eerste "Ie analog inputs arena erential sampled {tre analea Wpurte cerry vonples. The conreeponding 0 | oo _ | abossuuhiple must bo et to no palrunser Ps war he pared Inputs ar hae 2 Noa: ascent the omparstressasor does ot havea different opton thie it moat not be st who th Tobit et End of Sequence: ‘This bit mst best befor nating a slog sample sequence. (Seong end eonverion contre {i Taste ond ot anqunce. ‘Sample Intertupt Enable ‘0: The raw Interrupt i not asserted tothe Intereupt controller 2 | ie |: Therawintorrupt signal NRO bit Is assert at the ond ofthis sample's ‘conversion. If the MASKO bit in the ADCIM rogistoris set the interrupt Is [promoted tothe interrupt controller. {ta legal to have multiple samples within a sequence generate interrupts, ‘1st Sample Temperature Sensor Select ©: The input pin spocifed by tho ADCSSMUXn rogistr Is ood during tho 3 | 150 | iret: the sample sequence. The temperature sensor Is reed during te first sample ofthe sample sequence, Figure 7-16: ADC Sample Sequence Control 3 (ADCSSCTL3) Masking interrupt for SS3 Since we are using polling for the end-of-conversion, we must mask the interrupt option for the SS3 to prevent it from interrupting us via us NVIC. This is done with bit 3 of ADCIM (ADC Interrupt Mask) register. Upon Reset, the default for the bit 3 (MASK3) is 0. With the MASK3 = 0, it disables the interrupt and we will leave it like that. However, if we like to handle end-of- conversion by interrupt, we need to set this bit to 1 and write an interrupt handler to read the conversion result. 414ssx °0: The status of Sample Sequencer x doos not affect the SSx Interrupt status, ‘1 The raw infarupt sgnal from Sample Sequencer x (ADCRIS registar INR bi) I ‘sent tothe interrupt controller. ssx does not affect the SSx interrupt status, ‘comparators (INROG bit in the ADCRIS Interrupt line. Figure 7-17: ADC Interrupt Mask (ADCIM) V,er in Tiva LunachPad In the TI ARM Tiva chip series, the pin for Vrer (+) is called VDDA (VDD analog) and Vier (-) pin is called GNDA (Ground Analog). In the TI Tiva LaunchPad, the VDDA pin is connected to 3.3V, the same supply voltage as the digital part of the chip. Even if we connect the VDDA to a separate power source other than the VDD of the chip, it cannot go beyond the VDD voltage. With Vref=3.3V, we have the step size of 3.3V / 4096= 0.8057 mV since the ADC resolution is 12 bits. See Example 7-2. Example 7-2 Give the digital converted output if the analog input voltage is 1.2V for the TI Tiva LaunchPad. Solution: Since the step size is 3.3V / 4096 = 0.8057 mV, we have 1.2V / 0.8057 mV = 1489 = Ox5D1 as ADC output. eee Configuring GPIO for ADC input In using ADC, we must also configure the GPIO pins to allow theconnection of an analog signal through the input pin. In this regard, it is the same as all other peripherals. The steps are as follow: ci 4 Enable the clock to GPIO pin by using RCGCGPIO. Set the GPIOAFSEL (GPIO alternate function) bit for ADC input pin to 1 Configure AINx signal to be used as analog input by clearing the bit 3. in the GPIODEN (GPIO Digital enable) register. 4. Disable the Analog isolation circuit for ADC input pins by writing a 1 to the GPIOAMSEL register. “ADC Channel Pin AINO PES AIN1 PE2 ‘AINZ PEL AIN3 PEO AINS PD3 AINS PD2 AING PDL AIN7 PDO AINS PES AINS Peq ‘Ain10 Pea _AINIL PBS Table 7-7: ADC Channel pin designation Configuring ADC and reading ADC channel After the GPIO configuration, we need to take the following steps to configure the ADC for Sample Sequencer 3 (SS3): 1. N » Enable the clock to ADCO or ADC1 modules using RCGCADC register of System Registers. The SYSCTL->RCGCADC |= 3 will enable the clock to both ADCO and ADC1 modules. For ADCO module use SYSCTL- >RCGCADC |= 1 Disable the Sample Sequencer using the ADCACTSS register before changing the configuration of the sequencer. ADCO->ACTSS &= ~8 disables the S53. Choose the software trigger using the ADCEMUX register, Use ADCO- >EMUX &= ~OxF000 for software trigger.4. Select the ADC input channel using the ADCSSMUXn register. In the case of $$3 we use the ADCSSMUX3. For example, The ADCO->SSMUX3 = 0 selects AINO channel on pin PE3. Select the single-ended option, one-conversion per sample, and raw interrupt bit for end-of-conversion using the ADCSSCTL3 register. Use ADCO->SSCTL3 |= 6 for single-ended, one-conversion, and raw interrupt. 6. _ Enable the Sample Sequencer SS3 using ADCACTSS register. ADCO- >ACTSS |= 8 enables the SS3. Use ADCPSSI register to start a new conversion. Use ADCO->PSSI |= 8 to start a conversion by Sample Sequencer 3. 8. Keep monitoring the end-of-conversion INT3 flag in ADCRIS register. 9. When the INT3 goes HIGH, read the ADC result from the ADCSSFIFO3 and save it. 10. After reading the ADC result in step 9, clear the INT3 flag in ADCRIS register to allow for the next conversion. To clear INT3 flag, write to ADCICS register with ADCO->ISC = 8. 11. Repeat steps 8 through 10 for the next conversion. w ~ Program 7-1 illustrates the steps for ADC conversion shown above. Figure 7-18 shows the hardware connection of Program 7-1. Reuras Ewe ke Reuters) verts the analog input from AINO (J3.9 of LaunchPad| neer 3 and software trigger continuously 7-7, AINO channel is on PE3 pin. */ volatile int result; 0x10; /* enable clock to GPIO (AINO is onSYSCTL->RCGCADC |= 1; /* enable clock to ADCO */ /* initialize PE3 for AINO input */ GPIOE->AFSEL | /* enable alternate function */ GPIOE->DEN 6= ~8 /* disable digital function */ GPIOE->AMSEL | /* enable analog function */ /* initialize ADCO */ ADCO->ACTSS &= ~8; /* disable $$3 during configuratio ADCO->EMUX &= ~OxFOO /* software trigger conversion */ ADCO->SSMUX3 /* get input from channel 0 */ ADCO->SSCTL3 /* take one sample at a time, set flag at sample */ ADCO->ACTS /* enable ADCO sequencer 3 */ le(1 ADCO->PSST |= 8; /* start a conversion sequence 3 */ while((ADCO->RIS & 8) == 0) ; /* wait for conversion c result = ADCO->SSFIFO3; /* read conversion result */ ADCO->ISC = By /* clear completion flag */ void SystemInit (void) /* Grant coprocessor access */ /* This is required since TN4C12 ng point coprocessor SCB->CPACR |= 0x00£00000; Tiva 43.3v __LaunchPad Yoon Vaere 43.3V INO AINA —ainz Vern GNDA