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VHDL LAB 10 FSM Code Solution and Test Bench

The document describes VHDL lab assignments 10.1, 10.2, and 10.3. It includes the names of students in the group, RTL schematics, VHDL code listings for entities and architectures, and VHDL testbench code for each lab assignment. The labs involve designing Mealy and Moore state machines using VHDL for counting and output functions.

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Hasan
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© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
362 views

VHDL LAB 10 FSM Code Solution and Test Bench

The document describes VHDL lab assignments 10.1, 10.2, and 10.3. It includes the names of students in the group, RTL schematics, VHDL code listings for entities and architectures, and VHDL testbench code for each lab assignment. The labs involve designing Mealy and Moore state machines using VHDL for counting and output functions.

Uploaded by

Hasan
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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VHDL Lab 10

Nama : Hasan
Anggota kelompok : Nardo Golan
Rizki Wahyu N.
Rivan Rerizki P.
Cesario Bima I.

Lab 10.1 (Mealy)

RTL Schematic

TestBench

Listing program vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Lab_10_1 is
Port ( reset, clk, input : in STD_LOGIC;
cnt15 : out STD_LOGIC_VECTOR (3 downto
0):= "0000";
yout : out STD_LOGIC);
end Lab_10_1;

architecture Behavioral of Lab_10_1 is


signal cnt03_current, cnt03_next : unsigned (1 downto
0);
signal cnt15_current, cnt15_next : unsigned (3 downto
0);
begin
NSL : process (input, cnt03_current, cnt15_current)
begin
cnt15_next <= cnt15_current;
cnt03_next <= cnt03_current;
if input = '1' then
cnt15_next <= cnt15_current+1;
cnt03_next <= cnt03_current + 1;
if cnt03_current = 3 then
cnt03_next <= "01";
end if;
if cnt15_current = 15 then
cnt03_next <= "00";
end if;
end if;
end process;
CSR : process (clk, reset)
begin
if falling_edge(clk) then
if (reset = '1') then
cnt03_current <=
cnt15_current <=
else
cnt03_current <=
cnt15_current <=
end if;
end if;
end process;

(others => '0');


(others => '0');
cnt03_next;
cnt15_next;

OUTPUT_DECODE : process (cnt03_current, input,


cnt15_current)
begin
yout <= '0';
cnt15 <= std_logic_vector(cnt15_current);
if cnt03_current = 3 or cnt03_current = 0 then
yout <= input;
end if;
end process;
end Behavioral;

Listing program testbench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Tb_Lab_10_1 IS
END Tb_Lab_10_1;
ARCHITECTURE behavior OF Tb_Lab_10_1 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Lab_10_1
PORT(
reset : IN std_logic;
clk : IN std_logic;
input : IN std_logic;
cnt15 : OUT std_logic_vector(3 downto 0);
yout : OUT std_logic
);
END COMPONENT;
--Inputs
signal reset : std_logic := '0';
signal clk : std_logic := '1';
signal input : std_logic := '0';
--Outputs
signal cnt15 : std_logic_vector(3 downto 0);
signal yout : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Lab_10_1 PORT MAP (
clk => clk,
reset => reset,
input => input,
cnt15 => cnt15,
yout => yout
);
-- Clock process definitions
clk_process :process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;

end process;
-- Stimulus process
stim_proc: process
begin
reset <='0';
wait for 5 ns;
reset <='1';
wait for 10 ns;
reset <='0';
wait for clk_period;
input <= '0';
wait for clk_period*4;
input <= '1';
wait for clk_period*4;
input <= '0';
wait for clk_period*2;
input <= '1';
wait for clk_period*6;
input <= '0';
wait for clk_period*2;
input <= '1';
wait for clk_period*12;
end process;
END;

Lab 10.2 (Moore)

RTL Schematic

TestBench

Listing program vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
entity Lab_10_2 is
Port ( clk, reset : in STD_LOGIC;
ain : in STD_LOGIC_VECTOR (1 downto 0);
yout : out STD_LOGIC);
end Lab_10_2;
architecture Behavioral of Lab_10_2 is
signal out_current, out_next : std_logic;
signal input_current, input_next : std_logic_vector
(1 downto 0);
begin
CSR : process (clk, reset)
begin
if rising_edge(clk) then
if reset = '1' then
out_current <= '0';
input_current <= "00";
else
out_current <= out_next;
input_current <= input_next;
end if;
end if;
end process;
NSL : process (ain, input_current, out_current)
begin
out_next <= out_current;
input_next <= ain;
if (ain = "00" and input_current = "10") then out_next
<= not out_next;
elsif (ain = "00" and input_current = "11") then
out_next <= '1';

elsif (ain = "00" and input_current = "01") then


out_next <= '0';
end if;
end process;
OUTPUT : process (out_current)
begin
yout <= out_current;
end process;
end Behavioral;

Listing program testbench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Tb_Lab_10_2 IS
END Tb_Lab_10_2;
ARCHITECTURE behavior OF Tb_Lab_10_2 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Lab_10_2
PORT(
clk : IN std_logic;
reset : IN std_logic;
ain : IN std_logic_vector(1 downto 0);
yout : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal ain : std_logic_vector(1 downto 0) := (others =>
'0');
--Outputs
signal yout : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)

uut: Lab_10_2 PORT MAP (


clk => clk,
reset => reset,
ain => ain,
yout => yout
);
-- Clock process definitions
clk_process :process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset<='1';
wait for clk_period;
reset<='0';
wait for clk_period;
ain <= "11";
wait for clk_period*4;
ain <= "00";
wait for clk_period*4;
ain <= "10";
wait for clk_period*4;
ain <= "00";
wait for clk_period*4;
ain <= "11";
wait for clk_period*4;
ain <= "00";
wait for clk_period*4;
ain <= "10";
wait for clk_period*4;
ain <= "00";
wait for clk_period*4;
ain <= "10";
wait for clk_period*4;
ain <= "00";
wait for clk_period*4;
ain <= "01";
wait for clk_period*4;
ain <= "10";
wait for clk_period*4;
ain <= "00";
wait for clk_period*4;
ain <= "10";
wait for clk_period*4;
ain <= "00";

wait for clk_period*4;


ain <= "00";
wait for clk_period*4;
ain <= "01";
wait for clk_period*2;
ain <= "11";
wait for clk_period*4;
ain <= "10";
wait for clk_period*4;
ain <= "00";
wait for clk_period*4;
end process;
END;

Lab 10.3 (Mealy dengan ROM)

RTL Schematic

TestBench

Listing program vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;

entity Lab_10_3 is
Port (clk, reset, input : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (2 downto 0));
end Lab_10_3;
architecture Behavioral of Lab_10_3 is
type state_type is (S0, S1, S2, S3, S4, S5);
signal state, next_state : state_type;
begin
CSR : process(clk, reset, next_state)
begin
if falling_edge(clk) then
if reset = '1' then
state <= S0;
else
state <= next_state;
end if;
end if;
end process;
NSOR : process(input, state)
begin
case state is
when S0 =>
if input = '1' then
next_state <= S1;
end if;
when S1 =>
if input = '1' then next_state
end if;
when S2 =>
if input = '1' then next_state
end if;
when S3 =>
if input = '1' then next_state
end if;
when S4 =>
if input = '1' then next_state
end if;
when S5 =>
if input = '1' then next_state
end if;
end case;
end process;
with state select
output <= "000" when S0,
"001" when
"011" when
"101" when
"111" when

S1,
S2,
S3,
S4,

<= S2;
<= S3;
<= S4;
<= S5;
<= S0;

"010" when S5,


"000" when others;
end Behavioral;

Listing program testbench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Tb_Lab_10_3 IS
END Tb_Lab_10_3;
ARCHITECTURE behavior OF Tb_Lab_10_3 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Lab_10_3
PORT(
input : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
output : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal input : std_logic := '0';
--Outputs
signal output : std_logic_vector(2 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Lab_10_3 PORT MAP (
clk => clk,
reset => reset,
input => input,
output => output
);
-- Clock process definitions

clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
wait for clk_period;
reset <= '0';
wait for clk_period;
input <= '1';
wait for clk_period*6;
input <= '0';
wait for clk_period;
input <= '1';
wait for clk_period;
input <= '0';
wait for clk_period;
input <= '1';
wait for clk_period;
input <= '0';
wait for clk_period;
input <= '1';
wait for clk_period;
input <= '0';
wait for clk_period;
input <= '1';
wait for clk_period;
end process;
END;

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