WWW Gatepaper in
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GATE
Practice Problems
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1992
1. In an 8085 microprocessor system with memory mapped I/O,
a. I/O devices have 16 bit addresses
b. I/O devices are accessed using IN and OUT instructions
c. There can be a maximum of 256 input devices and 256 output
devices
d. Arithmetic and logic operations can be directly performed with the
I/O data.
Answer: A
Solution: https://www.youtube.com/watch?v=CTMsgQiIcUs
& Subtra...
October (20)
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March (24)
At the completion of the execution of the program, the program counter of the
8085 contains _____________ and the stack pointer contains
_______________.
Answer: SP = 0FFC, PC = 200A
Solution: https://www.youtube.com/watch?v=jRwb6JQAC4I
1993
1. In a microprocessor, wait states are used to
a. Make the processor wait during a DMA operation
b. Make the processor wait during an interrupt processing
c. Make the processor wait during a power shutdown
d. Interface slow peripherals to the processor
Answer:D
2. A microprocessor has five address lines [A4 A0] and eight data lines [D7
D0]. An input device A, an output device B, a ROM and a RAM are memory
mapped to the microprocessor at the addresses as shown in figure. Devices A
and B have four addressable registers each/ RAM has 8 bytes and ROM has 16
bytes.
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1995
1. When a CPU is interrupted, it
a. Stops executing of instructions
b. Acknowledges interrupt and branches of subroutine
c. Acknowledges interrupt and continues
d. Acknowledges interrupt and waits for the next instruction from the
interrupt device
Answer: B
4. A hypothetical CPU has a parallel address bus, a parallel data bus, a RD and
WR active LOW signals. Two ROMs of size 4K words each and two RAMs of
sizes 16K and 8K words, respectively, are to be connected to the CPU. The
memories are to be so connected that they fill the address space of the CU as per
the memory map shown in the figure. Assuming tat chip select signals are active
LOW.
the
1996
1. The total number of memory accesses involved (inclusive of the op-code
fetch), when an 8085 processor executes the instruction LDA 2003 is
a. 1
b. 2
c. 3
d. 4
Answer: D
Solution :
Solution :
1997
1. In 8085 P system, the RST instruction will cause an interrupt
a. Only if an interrupt service routine is not being executed
b. Only if a bit in the interrupt mask is made 0
c. Only if interrupts have been enabled by an EI instruction
d. None of the above
Answer: C
Solution :
2. The decoding circuit is shown in figure, has been used to generated the active
low chip select signal for a microprocessor peripheral (The address lines are
designated as A0 to A7 for I/O addresses).
a.
b.
c.
d.
60H 63H
A4 A7H
30 33H
70 73H
Answer: A
Solution :
https://www.youtube.com/watch?v=lMANeBdPfyg
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a.
b.
c.
d.
6019
6379
6979
None of the above
Answer: C
Solution :
4. A signed integer has been stored in a byte using the 2s complement format.
We wish to store the same integer in a 16 bit word. We should
Answer: C
Solution :
https://www.youtube.com/watch?v=KPDGRwll9LE
5. Match the following, while moving data between registers of the 8085 and the
stack
Answer: 1 - c, 2 - d
Solution :
6. An 8085 P uses a 2 MHz crystal. Find the time taken by it to execute the
following delay subroutine, inclusive of the call instruction in the calling program.
You are given that a CALL instruction takes 18 cycles of the system clock,
PUSH requires 12 cycles and conditional jump takes 10 cycles if the jump is
taken and 7 cycles if it is not. All other instructions used above take (3n + 1)
clock cycles, where n is the number of accesses to the memory, inclusive of the
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opcode fetch.
Answer: 1.842 mSec
Solution :
1998
1. An I/O processor control the flow of information between
a. Cache memory and I/O devices
b. Main memory and I/O devices
c. Two I/O devices
d. Cache and main memory
Answer: B
Solution :
https://www.youtube.com/watch?v=8SBet_bHUDA
Solution :
https://www.youtube.com/watch?v=TP3A9M09aho
Solution :
1999
1. If CS = A15A14A13 is used as the chip select logic of a 4K RAM in an 8085
system, then its memory range will be
a. 3000 3FFFFH
b. 7000 7FFFH
c. 5000 5FFFH and 6000 6FFFH
d. 6000 6FFFH and 7000 7FFFH
Answer: D
Solution : https://www.youtube.com/watch?v=5ZPEZCOhvd8
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Answer: (a) this program will found the highest number present in the given
memory location, finally that highest number will present in the accumulator.
(b) (i) A = 2B, B = 2B, C = 00, HL = 2002
(ii) CY = 1 and ZF = 1
(iii) [2000] = 18H, [2001] = 10H, [2002] = 2BH and [2100] = 2BH
Solution :
2000
1. In the 8085 microprocessor, the RST 6 instruction transfers the program
execution to the following location
a. 30H
b. 24H
c. 48H
d. 60H
Answer: A
Solution : https://www.youtube.com/watch?v=48roVRL_x1o
Solution : https://www.youtube.com/watch?v=Wt1abwe4das
3. The contents of register (B) and Accumulator (A) of 8085 microprocessor are
49H and 3AH respectively. The contents of A and the status of carry flag (CY)
and sign flag (S) after executing SUB B instruction are
a. A = F1 , CY = 1 , S = 1
b. A = 0F, CY = 1, S = 1
c. A = F0, CY = 0, S = 0
d. A = 1F, CY = 1, S = 1
Answer: A
Solution : https://www.youtube.com/watch?v=G08SPzuh2Lk
4. The program and machine code for an 8085 microprocessor are given by
The starting address of the above program is 7FFFH. What would happen if it is
executed from 8000H?
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Answer: (a) if the program executes from 8000H, it will find an infinite loop
with only one instruction "JMP 8000", an unconditional jump to memory
location 8000.
(b) Number of machine cycles required for CALL 2000H and LDA 2000H are 5
and 4 respectively.
(c) XRA A and SUB A
Solution :
2001
1. An 8085 microprocessor based system uses a 4K x8 bit RAM whose
starting address is AA00H. The address of the last byte in this RAM is
a. 0FFFH
b. 1000H
c. B9FFH
d. BA00H
Answer: C
Solution :
https://www.youtube.com/watch?v=psL4GimAjV8
Solution :
2002
1. Consider the following assembly language program.
MVI B, 87H
MOV A, B
START:
JMP NEXT
MVI B, 00H
XRA B
OUT PORT1
HLT
NEXT:
XRA B
JP START
OUT PORT2
HLT
The execution of the above program in an 8085 microprocessor will result in
a. An output of 87H at PORT1
b. An output of 87H at PORT2
c. Infinite looping of the program execution with accumulator data
remaining at 00H
d. Infinite looping of the program execution with accumulator data
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Solution :
https://www.youtube.com/watch?v=3Z_LU8RWke0
Solution :
2003
1. In an 8085 microprocessor, the instruction CMP B has been executed while
the content of the accumulator is less than that of register B. As a result,
a. Carry flag will be set but Zero flag will be reset
b. Carry flag will be reset but Zero flag will be set
c. Both Carry flag and Zero flag will be reset
d. Both Carry flag and Zero flag will be set
Answer: A
Solution : https://www.youtube.com/watch?v=kKwtMh2kzbc
2004
1. The 8255 programmable peripheral interface is used as described below.
(i)
An A/D converter is interfaced to a microprocessor through an
8255. The conversion is initiated by a signal from the 8255 on port C. A signal
on port C. A
signal on port C causes data to be strobed into port A.
(ii)
Two computers exchange data using a pair of 8255s. Port A
works as a bidirectional data port supported by appropriate handshaking
signals.
The appropriate modes of operation of the 8255 for (i) and (ii) would be
a. Mode 0 for (i) and Mode 1 for (ii)
b. Mode 1 for (i) and Mode 2 for (ii)
c. Mode 2 for (i) and Mode 0 for (ii)
d. Mode 2 for (i) and Mode 1 for (ii)
Answer: B
Solution :
Solution :
Solution : https://www.youtube.com/watch?v=Us-RGGYexA8
4. It is desired to multiply the numbers 0AH by 0BH and store the result in the
accumulator. The numbers are available in registers B and C respectively. A part
of the 8085 program for this purpose is given below:
MVI A, 00H
LOOP: ..............
..............
..............
HLT
END
The sequence of instructions to complete the program would be
a. JNZ LOOP,
ADD B,
DCR C
b. ADDB,
JNZ LOOP, DCR C
c. DCR C,
JNZ LOOP, ADD B
d. ADD B,
DCR C,
JNZ LOOP
Answer: D
Solution : https://www.youtube.com/watch?v=gdjv_EzqPB0
2005
Statement for linked Answer Questions 1 & 2 :
Consider an 8085 microprocessor system.
1. The following program starts at location 0100H.
LXI SP, 00FF
LXI H, 0701
MVI A, 20H
SUB M
THE Contents of accumulator when the program counter reaches 0109H is
a. 20H
b. 02H
c. 00H
d. FFH
Answer: C
2006
1. An I/O peripheral device shown n figure (b) below is to be interfaced to an
8085 microprocessor. To select the I/O device in the address range D4H D7H,
its chip-select (CS) should be connected to the output of the decoder shown in
the figure (a) below :
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a.
b.
c.
d.
Output 7
Output 5
Output 2
Output 0
Answer: B
Solution :
https://www.youtube.com/watch?v=pCzrjQ2zx44
Solution :
2007
1. An 8255 chip is interfaced to an 8085 microprocessor system as an I/O
mapped I/O as shown in the figure. The address lines A0 and A1 of the 8085 are
used by the 8255 chip to decode internally its three ports and the control register.
The address lines A0 to A7 as well as the IO/M signal are used for address
decoding. The range of addressees for which the 8255 chip would get selected is
a.
b.
c.
d.
F8H FBH
F8H FCH
F8H FFH
F0H F7H
Answer: C
Solution : https://www.youtube.com/watch?v=tWFKm8GgbEw
2
3
4
5
6
7
8
MVI B, 0EH
XRI 69H
ADD B
ANI 9BH
CPI 9FH
STA 3010H
HLT
2. The contents of the accumulator just after execution of the ADD instruction in
line 4 will be
a. C3H
b. EAH
c. DCH
d. 69H
Answer: B
3. After execution of line 7 of the program, the status of the CY and Z flags will
be .. respectively.
a. 0, 0
b. 0, 1
c. 1, 0
d. 1, 1
Answer: C
2008
1. An 8085 executes the following instructions
2710 LXI H, 30A0H
2713 DAD H
2714 PCHL
All addresses and constants are in Hexa decimal. Let PC be the contents of the
program counter and HL be the contents of HL register pair just after executing
PCHL.
Which of the following statements is correct?
a.
b.
c.
d.
Answer: C
Solution : https://www.youtube.com/watch?v=YS9fVY4bdn4
2009
1. In a microprocessor, the service routine for a certain interrupt starts from a
fixed location of memory which cannot be externally set, but the interrupt can be
delayed or rejected. Such an interrupt is
a. non-maskable and non-vectored
b. maskable and non-vectored
c. non-maskable and vectored
d. maskable and vectored
Answer: D
Solution : https://www.youtube.com/watch?v=pJ-6A_o5-LU
2010
1. For the 8085 assembly language program given below, the content of the
accumulator after the execution of the program is
3000 MVI A, 45H
3002 MOV B, A
3003 STC
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3004 CMC
3005 RAR
3006 XRA B
a.
b.
c.
d.
00H
45H
67H
E7H
Answer: C
Solution : https://www.youtube.com/watch?v=NSdbNs_Oiwk
2011
1. An 8085 assembly language program is given below. Assume that the carry
flag is initially unset. The contents of the accumulator after the execution of the
program is
MVI A, 07H
RLC
MOV B, A
RLC
RLC
ADD B
RRC
a.
b.
c.
d.
8CH
64H
23H
15H
Answer: C
Solution : https://www.youtube.com/watch?v=GlPuCxCnvws
2013
1. For 8085 microprocessor, the following program is executed.
MVI A,05H
MVI B, 05H
PTR: ADD B
DCR B
JNZ PTR
ADI 03H
HLT
At the end of the program, accumulator contains
a. 17H
b. 20H
c. 23H
d. 05H
Answer: A
Solution : https://www.youtube.com/watch?v=9YjXsP1wh-Y
2014
1. For the 8085 microprocessor, the interfacing circuit to input 8 bit digital
data (DI0 DI7) from an external device is shown in figure. The instruction for
correct data transfer is
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a.
b.
c.
d.
MVI A, F8H
IN F8H
OUT F8H
LDA F8F8H
Answer: D
Solution : https://www.youtube.com/watch?v=IH6ybT3DsAs
Answer: A
Solution : https://www.youtube.com/watch?v=RrlGPv7adtU
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