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GATE Previous Questions on Latches & Flip - Flops

with Solutions (1987 - Till Date)
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1987
1. Choose the correct statements relating to the circuit of figure shown
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2015 (34)
2014 (143)
December (14)
November (12)
GATE Analog Circuits Five Mark Questions
with Solu...
B&D
Solution : https://www.youtube.com/watch?v=zryK-Yl3-Dg
1988
1. The circuit given below is a
Previous GATE Questions on Analog to Digital

& Dig...
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and Mem...
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PLA and P...
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GATE Previous Questions on Latches & Flip Flops ...
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with ...
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(MUX) with...
Previous GATE Questions on Combinational
Circuits ...
a.
b.
c.
d.
JK flip flop
Johnson counter
RS latch
None of the above
Previous GATE Questions on K-Map, SOP and

POS expr...
Answer: C
Previous GATE Questions on Logic Gates (1987

to Ti...
v=vgY4u6Yqfqo
Solution : https://www.youtube.com/watch?
Previous GATE Questions on Number Sy stems

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October (20)
September (7)
August (8)
July (5)
June (6)
1991
1. An S-R flip flop can be converted into a T flip flop by connecting ____ to
Qbar and _____ to Q.
Answer: S to Qbar and R to Q
Solution : https://www.youtube.com/watch?v=sxSeKlxdxSc
May (20)
April (27)
March (24)
1992
1. A new clocked X-Y flip flop is defined with two inputs, X and Y is in addition to
the clock input. The flip flop functions as follows:
If XY = 00, the flip flop changes state with each clock pulse
If XY = 01, the flip flop state Q becomes 1 with the next clock pulse
If XY = 10, the flip flop state Q becomes 0 with the next clock pulse
If XY = 11, the change of state occurs with the clock pulse
a. Write the truth table for the XY flip flop
b. Write the excitation table for the XY flip flop
c. It is desirable to convert a J-K flip flop into X-Y flip flop by adding
some external gates, if necessary. Draw a circuit to show how you will
implement in X-Y flip flop using a J-K flip flop.
Solution : https://www.youtube.com/watch?v=c8PZBGHCGDQ
1994
1. For the digital circuit shown in the figure, explain what happens at nodes N1, N2,
F and F when
Solution : https://www.youtube.com/watch?v=yl2GD3Hetm8
1995
1. A switch-tail ring counter is made by using a single D flip flop. The resulting circuit
is a
a. SR flip flop
b. JK flip flop
c. D flip flop
d. T flip flop
Answer: D
Solution : https://www.youtube.com/watch?v=NgHdSqy1YKw
2. An SR latch is a
a. Combinational circuit
b. Synchronous sequential circuit
c. One bit memory element
d. One clock delay element
Answer: C
Solution : https://www.youtube.com/watch?v=C8x2OcVIKh8
1997
1. In a JK flip flop, we have J = Q and K = 1. Assume the flip flop was initially
cleared and then clocked for 6 pulses, the sequence at the Q output will be
a.
b.
c.
d.
010000
011001
010010
010101
Answer: D
Solution :
https://www.youtube.com/watch?
v=xLkAhzePI90
1998
1. In the figure shown is A = 1 and B = 1, the input B is now replaced with a
sequence 101010....., the output X and Y will be
a.
b.
c.
d.
Answer:
Fixed at 0 and 1 respectively

X = 1010... while Y = 0101....
X = 1010.... and Y = 1010....
Fixed at 1 and 0 respectively
A
v=DPWbOTGp_9I
2000
1. A sequential circuit using D flip flop and logic gates is shown in figure, where X
and Y are the inputs and Z is output. The circuit is
a.
b.
c.
d.
S-R flip flop with inputs X = R and Y = S

S-R flip flop with inputs X = S and Y = R
J-K flip flop with inputs X = J and Y = K
J-K flip flop with inputs X = K and Y = J
Answer: D
v=Z9naO48RJT8
2001
1. In the figure, the output of the oscillator, V1 has 10 volts peak amplitude with
zero DC value. The transfer characteristic of the Schmitt inverter is also shown in
the figure. Assume that the JK flip-flop is reset at time t=0.
a. What is the period and duty cycle of the waveform V2?

b. What is the period and duty cycle of the waveform V3?
c. Sketch V1, V2 and V3 for the duration 0 t 6 sec. Clearly
indicate the exact
timings when the waveforms V2 and V3 make high to low
and low to high transitions.
Solution :
v=Gr8CESH_ZJM
https://www.youtube.com/watch?
2004
1. A Master Slave flip flop has the characteristic that
a. Change in the input immediately reflected in the output.
b. Change in the output occurs when the state of the master is affected
c. Change in the output occurs when the state of the slave is affected
d. Both the master and the slave states are affected at the same time.
Answer: C
Solution : https://www.youtube.com/watch?v=oViyDQttV2E
2005
1. The present output Qn of an edge triggered JK flip-flop is logic 0. If j = 1,
then Qn+1 is
a. Cannot be determined
b. Will be logic 0
c. Will be logic 1
d. Will race around
Answer: C
v=3Txg02Wb8N0
2007
1. In the following circuit, binary values were applied to the inputs X and Y
inputs of the NAND latch shown in the figure in the sequence indicated below:
X = 0, Y = 1; X = 0, Y = 0; X = 1, Y = 1;
The corresponding stable P, Q outputs will be
Answer: C
v=PEBoEN_8dW8
2008
1. For the circuit shown in the figure, D has a transition from 0 to 1 after CLK
changes from 1 to 0. Assume gate delays to be negligible.
Which of the following statements is TRUE?

a. Q goes to 1 at the CLK transition and stays at 1
b. Q goes to 0 at the CLK transition and stays at 0
c. Q goes to 1 at the CLK transition and goes to 0 when D
goes to 1
d. Q goes to 0 at the CLK transition and goes to 1 when D goes
to 1
Answer: C
Solution : https://www.youtube.com/watch?v=FvPG9aLQcHg
2009
1. Refer to the NAND and NOR latches shown in the figure. The inputs (P1,
P2) for both the latches are first made (0, 1) and then, after a few seconds, made
(1, 1). The corresponding stable outputs (Q1, Q2) are
Answer: C
Solution : https://www.youtube.com/watch?v=CmdmJ9qQjdk
2012
1. Consider the given circuit. In the circuit, the race around
Answer: A
Solution : https://www.youtube.com/watch?v=VGgKVxbWrfw
Posted by GATE paper at 1 4:1 1

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Labels: Flip Flops & Latches, GATE Questions
6 comments
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Top comments
Sanduni Jayasinghe 7 months ago - Shared publicly

We learnt at school that if the two inputs of S-R flip flop are both 1s,
then there will be no stable output. Is this true sir? Can you please
explain this?
Reply
Raj Sekhar 1 year ago - Shared publicly

sir u have cleared lot of doubts ,,,,please upload remaining
subjects(EMT,COMMUNICATION and networks)
+2
3
2
Reply
bhirgu lal das 2 days ago - Shared publicly

The SR flip-flop can be converted to T flip-flop if
S is connected to Q
R is connected to Q
Both S and R are shorted
S and R are connected to Q and Q respectivel
Reply
Kirti Shukla 11 months ago - Shared publicly
Reply
Abinash Das 1 year ago - Shared publicly

Sir can you add the 2014 paper solutions of JK flip flop?
Reply
SONU KUMAR 1 year ago - Shared publicly

thanks
+1
2
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Home

GATE 2014 Keys

Yearwise GATE Questions

Topicwise GATE Questions

GATE Exam Notes

Friday, November 14, 2014

GATE Previous Questions on Latches & Flip - Flops

Be the first of your friends to like this

Previous GATE Questions on Analog to Digital

Previous GATE Questions on K-Map, SOP and

Previous GATE Questions on Logic Gates (1987

Previous GATE Questions on Number Sy stems

Fixed at 0 and 1 respectively

S-R flip flop with inputs X = R and Y = S

a. What is the period and duty cycle of the waveform V2?

The corresponding stable P, Q outputs will be

Which of the following statements is TRUE?

Posted by GATE paper at 1 4:1 1

Labels: Flip Flops & Latches, GATE Questions

Sanduni Jayasinghe 7 months ago - Shared publicly

Raj Sekhar 1 year ago - Shared publicly

bhirgu lal das 2 days ago - Shared publicly

Kirti Shukla 11 months ago - Shared publicly

Abinash Das 1 year ago - Shared publicly

SONU KUMAR 1 year ago - Shared publicly

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