How To Be A Good PHD Student: Elena Dubrova Ecs/Ict/Kth
How To Be A Good PHD Student: Elena Dubrova Ecs/Ict/Kth
Elena Dubrova
ECS/ICT/KTH
Theory vs practice
The theoretical part of the course will be
complemented by practical exercises
Each student will apply the techniques learned in
the course to write a conference paper in his/her
area of research, to present this paper in the
class, and to apply for a travel grant (e.g.
supporting a conference trip or a research visit)
Course structure
Length:
one academic year Sept 2016 June 2017
Lectures
Typically every other week, on Thursday 10-12, see
course web page for the schedule:
https://people.kth.se/~dubrova/coursePhD.html
Introductory part
Major phases of a PhD study are:
Background study
Literature survey
Detailed problem formulation
Execution
Publishing
Background study
The goal is to understand needs in your area in
order to focus your PhD research on an
important problem
This task is hardest of all
Important to know
An essential feature of a good paper, talk, or
proposal is:
The ratio information/noise is maximized
Quality
Target group (who?)
Place (where?)
Quantity (how much?)
Time (by when?)
Example I
White paper on Physical Synthesis for Power
Under Process Variation of J. Cong
Structure:
Motivation
Objectives
Technical approaches
Anticipated results
Motivation
The most significant progress in EDA in the past ten years is arguably the
development of physical synthesis technology and its wide adoption by the IC
design industry today. However, the existing physical synthesis technology has
several limitations:
(1) It was originally developed to address the timing closure problem, thus, did
not give sufficient consideration of power optimization. Although a number of
power optimization techniques have been added in many physical synthesis
flows (such as cell sizing, multiple Vt and Vdd selections), there is lack of
general and efficient algorithmic framework to consider and balance all
available power optimization opportunities, especially in connection with
placement.
(2) It did not consider increasing process variations in nanometer designs,
therefore, the results by existing physical optimization algorithms may not work
under all timing corners. A considerable safe margin is added to guard-band
the statistical variation, resulting in a sizable waste of power, area, and
performance.
p. 19 - FIL3001 The Art of Doctoral Research
Objectives
(a) Develop a unified and efficient mathematical foundation and algorithmic
framework for physical synthesis to support power optimization guided by both
physical locality and an evolving netlist structure. For example, the placement
engine should support multi-Vdd islands, clock gating and power gating, where
physical locality has a big impact on optimization quality. But it should also
support cell sizing, buffering, logic structuring, where an evolving netlist and
thus changing logic density need to be considered, during placement, for
correct power optimization.
(b) Develop efficient theory and algorithms to support statistical optimization under
process variation so that the physical synthesis results satisfy all timing
constraints under all timing corners or achieve the required timing-yield
constraints under given probability density functions (PDFs).
(c) Consider the efficient use of multi-core CPUs (as they become widely
available) to further improve the runtime efficiency for coping with the high
complexity of the proposed problem.
p. 20 - FIL3001 The Art of Doctoral Research
Anticipated results
Anticipated results of the proposed research include
technical reports, published papers in major EDA
conferences and journals, and a software prototype of a
novel physical synthesis flow for power optimization under
process variation. Our research group has a strong track
record in delivering the results and transferring the
technology to the SRC companies our latest SRC project
on placement (ending June06) promised a Moores law
generation reduction of wirelength (30%) and we already
exceeded that goal considerably [Chan05].
Example II
Home page at
http://www.itrs.net/
Design productivity
Power consumption
Manufacturability
Interference
Error tolerance
First assignment
The purpose is to persuade you that you will be
able to produce a good paper/talk/proposal with
a maxmum information/noise ratio only if:
1. You understand the core problem which you are
addressing, and
2. You are aware of the needs for solving this problem,
and
3. You have a clear picture of the goal, objectives, and
expected results of your research