SYLLABUS:

8085 ARCHITECTURE

Introduction-8085 Architecture-Block Diagram, Flag Register, Pin

Diagram, Timing and Control Signals, System Timing Diagram,

Instruction Set of 8085- Instruction & Data Formats- Addressing

Modes-Instructions.

Introduction:

The features of INTEL 8085 are:

It is an 8 bit processor.

It has multiplexed address and data bus. (AD0-AD7).

It is a single chip N-MOS device with 40 pins.

It works on 5 Volt dc power supply.

The maximum clock frequency is 3 MHz while minimum frequency is 500 kHz.
It provides 16 address lines so it can access 2^16 =64 Kbytes of memory.
It generates 8 bit I/O address so it can access 2^8=256 input ports.

8085 Architecture:

Fig: Architecture of 8085 microprocessor

The internal architecture of 8085 includes the ALU, timing and control unit, instruction register

and decoder, register array, interrupt control and serial I/O control. The ALU performs the arithmetic
and logical operations. The operations performed by ALU of 8085 are addition, subtraction, increment,
decrement, logical AND, OR, EXCL U8IVE -OR, compare, complement and left / right shift.

The accumulator and temporary register are used to hold the data during an arithmetic / logical

operation. After an operation the result is stored in the accumulator and the flags are set or reset
according to the result of the operation.
Registers:

The 8085includes six registers, one accumulator, and one flag register, as shown in Figure. In

addition, it has two 16-bit registers: the stack pointer and the program counter. The 8085 has six

general-purpose registers to store 8-bit data; these are identified as B, C, D, E, H, and L as shown in the
figure.

They can be combined as register pairs - BC, DE, and HL - to perform some 16-bit operations.

The programmer can use these registers to store or copy data into the registers by using data copy
instructions.

Accumulator

The 8085 microprocessor is an accumulator (A) based microprocessor, Accumulator register must

be the one of the operand in Arithmetic and logical operations. The accumulator is an 8-bit register that
is a part of arithmetic/logic unit (ALU). This register is used to store 8-bit data and to perform arithmetic

and logical operations. The result of an operation is stored in the accumulator. The accumulator is also
identified as register A.
Flag Register

D7
S

D6
Z

D5
X

D4

AC

D3
X

D2
P

Fig : Flag register of 8085 microprocessor

Flag register indicates the status of result.

Sign Flag:

Used for indicating the sign of the data in the accumulator.

The sign flag is reset if positive (0 positive).

The sign flag is set if negative (1 negative).

Zero Flag:

Is set if result obtained after an operation is 0.

Is set following an increment or decrement operation of that register.

Carry Flag:

Is set if there is a carry out of the 7th-bit (MSB).

Is set if there is carry out from 3rd-bit (lower nibble position).

Is set if the result contains even number of 1s.

Auxiliary Carry Flag:

Parity Flag:
X- Not used

D1
X

D0

CY

Program Counter (PC):

This 16-bit register deals with sequencing the execution of instructions. This register is a memory

pointer. The microprocessor uses this register to sequence the execution of the instructions. The function of

the program counter is to point to the memory address from which the next byte is to be fetched. When a

byte is being fetched, the program counter is automatically incremented by one to point to the next memory
location.

Stack Pointer (SP):

The stack pointer is also a 16-bit register, used as a memory pointer. It points to a memory location in

R/W memory, called stack. The beginning of the stack is defined by loading 16-bit address in the stack
pointer.

PIN DESCRPTION 0F 8085:

Fig: pin diagram of 8085

The 8085 microprocessor is available on a 40-pin Dual-in-Line package (DIP). The following

describes the function of each pin:

A16 A8 (Output 3 State): Address Bus

The most significant 8 bits of the memory address or the 8 bits of the I/0 addresses, 3 stated

during Hold and Halt modes.

AD0 - AD7 (Input/ Output 3state): Multiplexed Address/Data Bus

Lower 8 bits of the memory address (or I/0 address) appear on the bus during the first clock

cycle of a machine state. It then becomes the data bus during the second and third clock cycles. 3 stated
during Hold and Halt modes.

ALE (Output): Address Latch Enable

It occurs during the first clock cycle of a machine state and enables the address to get latched

into the on chip latch of peripherals. The falling edge of ALE is set to guarantee setup and hold times for
the address information. ALE can also be used to strobe the status information. ALE is never 3stated.
SO, S1 (Output): Data Bus Status
S1

Encoded status of the bus cycle:

S0

0
1

status

HALT

WRITE

FETCH

READ

S1 can be used as an advanced R/W status.

RD (Output 3state): READ

Indicates the selected memory or 1/0 device is to be read and that the Data Bus is available or the

data transfer.

WR (Output 3state): WRITE

Indicates the data on the Data Bus is to be written into the selected memory or 1/0 location.

READY (Input):

If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready

to send or receive data. If Ready is low, the CPU will wait for Ready to go high before completing the
read or write cycle.
HOLD (Input):

Indicates that another Master is requesting the use of the Address and Data Buses. The CPU,

upon receiving the Hold request. will relinquish the use of buses as soon as the completion of the current
machine cycle. Internal processing can continue. The processor can regain the buses only after the Hold
is removed. When the Hold is acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.

HLDA (Output): HOLD ACKNOWLEDGE

Indicates that the CPU has received the Hold request and that it will relinquish the buses in the

next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the buses one half
clock cycle after HLDA goes low.

INTR (Input): INTERRUPT REQUEST

It is used as a general purpose interrupt. It is sampled only during the next to the last clock cycle

of the instruction. If it is active, the Program Counter (PC) will be inhibited from incrementing and an

INTA will be issued. During this cycle a RESTART or CALL instruction can be inserted to jump to the

interrupt service routine. The INTR is enabled and disabled by software. It is disabled by Reset and
immediately after an interrupt is accepted.

INTA (Output): INTERRUPT ACKNOWLEDGE

It is used instead of (and has the same timing as) RD during the Instruction cycle after an INTR

is accepted. It can be used to activate the 8259 Interrupt chip or some other interrupt port.
RST 5.5, RST 6.5, RST 7.5 (Inputs): RESTART INTERRUPTS

These three inputs have the same timing as INTR except they cause an internal RESTART to be

automatically inserted.

RST 7.5 --------- Highest Priority

RST 6.5

RST 5.5--------Lowest Priority

The priority of these interrupts is ordered as shown above. These interrupts have a higher priority

than the INTR.

TRAP (Input):

Trap interrupt is a non-maskable restart interrupt. It is recognized at the same time as INTR. It is

unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt.
RESET IN (Input):

Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops.

None of the other flags or registers (except the instruction register) are affected The CPU is held in the
reset condition as long as Reset is applied.
RESET OUT (Output):

Indicates CPlJ is being reset. Can be used as a system RESET. The signal is synchronized to the

processor clock.

X1, X2 (Input):

Crystal or RC network connections to set the internal clock generator X1 can also be an external

clock input instead of a crystal. The input frequency is divided by 2 to give the internal operating
frequency.

CLK (Output):

Clock Output for use as a system clock when a crystal or R/ C network is used as an input to the

CPU. The period of CLK is twice the X1, X2 input period.

IO/M (Output):
and Halt modes.

IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold

SID (Input): Serial input data line

The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed.
SOD (output): Serial output data line

The output SOD is set or reset as specified by the SIM instruction.

Vcc:

Vss:

+5 volts supply.

Ground Reference.

ADDRESSING MODES OF 8085:

To perform any operation, we have to give the corresponding instructions to the microprocessor.

In each instruction, programmer has to specify 3 things:

Operation to be performed.
Address of source of data.

Address of destination of result.

The method by which the address of source of data or the address of destination of result is given

in the instruction is called Addressing Modes. The term addressing mode refers to the way in which the
operand of the instruction is specified. Intel 8085 uses the following addressing modes:

1. Direct Addressing Mode

2. Register Addressing Mode

3. Register Indirect Addressing Mode

4. Immediate Addressing Mode
5. Implicit Addressing Mode
1. Direct Addressing Mode

In this mode, the address of the operand is given in the instruction itself.
Ex: - LDA 2500H

Load the contents of memory location 2500H in Accumulator.

LDA is the operation.

Accumulator is the destination.

2500 H is the address of source.

2. Register Addressing Mode

In this mode, the operand is in general purpose register.

Ex: - MOV A, B

Move the contents of B register to A register.

MOV is the operation.

Accumulator is the destination.

B is the data source.

3. Register Indirect Addressing Mode

In this mode, the address of operand is specified by a register pair.

Ex: - MOV A, M

pair to A register.

Move the contents of Memory location which is pointed to by HL register

MOV is the operation.

Accumulator is the destination.

M is the memory location specified by H-L register pair.

4. Immediate Addressing Mode

In this mode, the operand is specified within the instruction itself.

Ex: - MVI A, 22H

Move the content 22H to A register.

MVI is the operation.

Accumulator is the destination.

22H is the immediate data.

5. Implicit Addressing Mode

If address of source of data as well as address of destination of result is fixed, then there is no

need to give any operand along with the instruction.

Ex: - CMA

complements the Accumulator contents and stored into Accumulator.

CMA is the operation.

A is the destination.

A is the source.

INSTRCTION SET OF 8085:

The instruction set of 8085 microprocessor is classified into the following types.

Data Transfer Instruction

Logical Instructions

Arithmetic Instructions

Branching Instructions

Control Instructions

Data Transfer Instruction

Copy from source to destination

MOV

Rd, Rs

M, Rs

Rd, M
Example: MOV B, C

This instruction copies the contents of the source register into the destination register; the contents of the

source register are not altered. If one of the operands is a memory location, its location is specified by the
contents of the HL registers.
MVI

M, data

Rd, data

Example: MVI B, 57H or MVI M, 57H

The 8-bit data is stored in the destination register or memory. If the operand is a memory location, its

location is specified by the contents of the HL registers.

Load accumulator
LDA 16-bit address

Example: LDA 2034H

The contents of a memory location, specified by a 16-bit address in the operand, are copied to the

accumulator. The contents of the source are not altered.

LDAX

B/D Reg. pair

Example: LDAX B

The contents of the designated register pair point to a memory location. This instruction copies the

contents of that memory location into the accumulator. The contents of either the register pair or the memory
location are not altered.

Load register pair immediate

LXI

Reg. pair, 16-bit data

Example: LXI H, 2034

The instruction loads 16-bit data in the register pair designated in the operand.

Load H and L registers direct

LHLD

16-bit address

Example: LHLD 2040

The instruction copies the contents of the memory location pointed out by the 16-bit address into

register L and copies the contents of the next memory location into register H. The contents of source memory
locations are not altered.

Store accumulator direct

STA

16-bit address
Example: STA 4350H

The contents of the accumulator are copied into the memory location specified by the operand. This

is a 3-byte instruction, the second byte specifies the low-order address and the third byte specifies the highorder address.

Store accumulator indirect

STAXReg. pair

Example: STAX B

The contents of the accumulator are copied into the memory location specified by the contents of the

operand (register pair). The contents of the accumulator are not altered.

Store H and L registers direct

SHLD

16-bit address
Example: SHLD 2470H

The contents of register L are stored into the memory location specified by the 16-bit address in the

operand and the contents of H register are stored into the next memory location by incrementing the

operand. The contents of registers HL are not altered. This is a 3-byte instruction, the second byte specifies
the low-order address and the third byte specifies the high-order address.
Exchange H and L with D and E
XCHG

none

Example: XCHG

The contents of register H are exchanged with the contents of register D, and the contents of register L

are exchanged with the contents of register E.

Copy H and L registers to the stack pointer
SPHL

none
Example: SPHL

The instruction loads the contents of the H and L registers into the stack pointer register, the

contents of the H register provide the high-order address and the contents of the L register provide the
low-order address. The contents of the H and L registers are not altered.
Exchange H and L with top of stack
XTHL

none
Example: XTHL

The contents of the L register are exchanged with the stack location pointed out by the contents of

the stack pointer register. The contents of the H register are exchanged with the next stack location (SP+1);
however, the contents of the stack pointer register are not altered.
Push register pair onto stack
PUSH

Reg. pair

Example: PUSH B or PUSH A

The contents of the register pair designated in the operand are copied onto the stack in the following

sequence. The stack pointer register is decremented and the contents of the high- order register (B, D, H, A)
are copied into that location. The stack pointer register is decremented again and the contents of the low-order
register (C, E, L, flags) are copied to that location.

Pop off stack to register pair

POP

Reg. pair

Example: POP H or POP A

The contents of the memory location pointed out by the stack pointer register are copied to the low-order

register (C, E, L, status flags) of the operand. The stack pointer is incremented by 1 and the contents of that

memory location are copied to the high-order register (B, D, H, A) of the operand. The stack pointer register is
again incremented by 1.

Output data from accumulator to a port with 8-bit address

OUT

8-bit port address

Example: OUT 87H

The contents of the accumulator are copied into the I/O port specified by the operand.
Input data to accumulator from a port with 8-bit address
IN

8-bit port address

Example: IN 82H
The contents of the input port designated in the operand are read and loaded into the accumulator.

ARITHMETIC INSTRUCTIONS
Add register or memory to accumulator
ADD

Example: ADD B or ADD M

The contents of the operand (register or memory) are added to the contents of the accumulator and the

result is stored in the accumulator. If the operand is a memory location, its location is specified by the
contents of the HL registers. All flags are modified to reflect the result of the addition.
Add register to accumulator with carry
ADC

Example: ADC B or ADC M

The contents of the operand (register or memory) and the Carry flag are added to the contents of the

accumulator and the result is stored in the accumulator. If the operand is a memory location, its location is
specified by the contents of the HL registers. All flags are modified to reflect the result of the addition.

Add immediate to accumulator

ADI

8-bit data

Example: ADI 45H

The 8-bit data (operand) is added to the contents of the accumulator and the result is stored in the

accumulator. All flags are modified to reflect the result of the addition.
Add immediate to accumulator with carry
ACI

8-bit data

Example: ACI 45H

The 8-bit data (operand) and the Carry flag are added to the contents of the accumulator and the

result is stored in the accumulator. All flags are modified to reflect the result of the addition.
Add register pair to H and L registers
DAD

Reg. pair

Example: DAD H
The 16-bit contents of the specified register pair are added to the contents of the HL register and the

sum is stored in the HL register. The contents of the source register pair are not altered. If the result is
larger than 16 bits, the CY flag is set. No other flags are affected.
Subtract register or memory from accumulator
SUB

Example: SUB B or SUB M

The contents of the operand (register or memory ) are subtracted from the contents of the accumulator,

and the result is stored in the accumulator. If the operand is a memory location, its location is specified by
the contents of the HL registers. All flags are modified to reflect the result of the subtraction.
Subtract source and borrow from accumulator
SBB

Example: SBB B or SBB M

The contents of the operand (register or memory ) and the Borrow flag are subtracted from the

contents of the accumulator and the result is placed in the accumulator. If the operand is a memory location,

its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the
subtraction.

Subtract immediate from accumulator

SUI

8-bit data

Example: SUI 45H

The 8-bit data (operand) is subtracted from the contents of the accumulator and the result is stored in the

accumulator. All flags are modified to reflect the result of the subtraction.
Subtract immediate from accumulator with borrow
SBI

8-bit data

Example: SBI 45H

The 8-bit data (operand) and the Borrow flag are subtracted from the contents of the accumulator and

the result is stored in the accumulator. All flags are modified to reflect the result of the subtraction.
Increment register or memory by 1
INR

Example: INR B or INR M

The contents of the designated register or memory) are incremented by 1 and the result is stored in the

same place. If the operand is a memory location, its location is specified by the contents of the HL registers.
Increment register pair by 1
INX

Example: INX H
place.

The contents of the designated register pair are incremented by 1 and the result is stored in the same

Decrement register or memory by 1

DCR

Example: DCR B or DCR M

The contents of the designated register or memory are decremented by 1 and the result is stored in the same

place. If the operand is a memory location, its location is specified by the contents of the HL registers.
Decrement register pair by 1
DCX

Example: DCX H
place.

The contents of the designated register pair are decremented by 1 and the result is stored in the same

Decimal adjust accumulator

DAA

none

Example: DAA
The contents of the accumulator are changed from a binary value to two 4-bit binary coded decimal

(BCD) digits. This is the only instruction that uses the auxiliary flag to perform the binary to BCD conversion,

and the conversion procedure is described below. S, Z, AC, P, CY flags are altered to reflect the results of the

operation. If the value of the low-order 4-bits in the accumulator is greater than 9 or if AC flag is set, the
instruction adds 6 to the low-order four bits. If the value of the high-order 4-bits in the accumulator is
greater than 9 or if the Carry flag is set, the instruction adds 6 to the high-order four bits.

BRANCHING INSTRUCTIONS
Jump unconditionally
JMP

16-bit address

Example: JMP 2034H or JMP XYZ

The program sequence is transferred to the memory location specified by the 16-bit address given in the

operand.

Jump conditionally
Operand: 16-bit address
Example: JZ 2034H
Opcode

Description

Flag Status

JC

Jump on Carry

CY = 1

JNC

Jump on no Carry

CY = 0

JP

Jump on positive

S=0

JM

Jump on minus

S=1

JZ

Jump on zero

Z=1

JNZ

Jump on no zero

Z=0

JPE

Jump on parity even

P=1

JPO

Jump on parity odd

P=0

Unconditional subroutine call

CALL

16-bit address

Example: CALL 2034H

The program sequence is transferred to the memory location specified by the 16-bit address given

in the operand. Before the transfer, the address of the next instruction after CALL (the contents of the
program counter) is pushed onto the stack.
Call conditionally
Operand: 16-bit address
Example: CZ 2034H

The program sequence is transferred to the memory location specified by the 16-bit address given in

the operand based on the specified flag of the PSW as described below. Before the transfer, the address of
the next instruction after the call (the contents of the program counter) is pushed onto the stack.
Opcode

Description

Flag Status

CC

Call on Carry

CY = 1

CNC

Call on no Carry

CY = 0

CP

Call on positive

S=0

CM

Call on minus

S=1

CZ

Call on zero

Z=1

CNZ

Call on no zero

Z=0

CPE

Call on parity even

P=1

CPO

Call on parity odd

P=0

Return from subroutine unconditionally

RET

none

Example: RET
The program sequence is transferred from the subroutine to the calling program. The two bytes

from the top of the stack are copied into the program counter, and program execution begins at the new
address.

Return from subroutine conditionally

Operand: none
Example: RZ
The program sequence is transferred from the subroutine to the calling program based on the specified

flag of the PSW as described below. The two bytes from the top of the stack are copied into the program
counter, and program execution begins at the new address.
Opcode

Description

Flag Status

RC

Return on Carry CY = 1

RNC

Return on no Carry

CY = 0

RP

Return on positive

S=0

RM

Return on minus S = 1

RZ

Return on zero

Z=1

RNZ

Return on no zero

Z=0

RPE

Return on parity even

P=1

RPO

Return on parity odd

P=0

Load program counter with HL contents

PCHL

none

Example: PCHL

The contents of registers H and L are copied into the program counter. The contents of H are placed as the

high-order byte and the contents of L as the low-order byte.

Restart
RST

0-7

The RST instruction is equivalent to a 1-byte call instruction to one of eight memory locations depending

upon the number. The instructions are generally used in conjunction with interrupts and inserted using external

hardware. However these can be used as software instructions in a program to transfer program execution to
one of the eight locations.
The addresses are:

Instruction

Restart Address

RST 0

0000H

RST 2

0010H

RST 1
RST 3
RST 4
RST 5
RST 6
RST 7

0008H
0018H
0020H
0028H
0030H
0038H

The 8085 has four additional interrupts and these interrupts generate RST instructions internally and

thus do not require any external hardware. These instructions and their Restart addresses are:
Interrupt

Restart Address

TRAP

0024H

RST 5.5

002CH

RST 6.5

0034H

RST 7.5

003CH

LOGICAL INSTRUCTIONS
Compare register or memory with accumulator
CMP

Example: CMP B or CMP M

The contents of the operand (register or memory) are compared with the contents of the accumulator. Both

contents are preserved. The result of the comparison is shown by setting the flags of the PSW as follows:
if (A) < (reg/mem): carry flag is set (CY=1)

if (A) = (reg/mem): zero flag is set (ZF=1)

if (A) > (reg/mem): carry and zero flags are reset (CY=0)

Compare immediate with accumulator

CPI

8-bit data

Example: CPI 89H

The second byte (8-bit data) is compared with the contents of the accumulator. The values being

compared remain unchanged. The result of the comparison is shown by setting the flags of the PSW as follows:
if (A) < data: carry flag is set
if (A) = data: zero flag is set

if (A) > data: carry and zero flags are reset

Logical AND register or memory with accumulator

ANA

Example: ANA B or ANA M

The contents of the accumulator are logically ANDed with the contents of the operand (register or

memory), and the result is placed in the accumulator. If the operand is a memory location, its address is
specified by the contents of HL registers. S, Z, P are modified to reflect the result of the operation. CY is
reset. AC is set.

Logical AND immediate with accumulator

ANI

8-bit data

Example: ANI 86H

The contents of the accumulator are logically ANDed with the 8-bit data (operand) and the result is

placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY is reset. AC is set.
Exclusive OR register or memory with accumulator
XRA

Example: XRA B or XRA M

The contents of the accumulator are Exclusive ORed with the contents of the operand (register or

memory), and the result is placed in the accumulator. If the operand is a memory location, its address is
specified by the contents of HL registers. S, Z, P are modified to reflect the result of the operation. CY and
AC are reset.

Exclusive OR immediate with accumulator

XRI

8-bit data

Example: XRI 86H

The contents of the accumulator are Exclusive ORed with the 8-bit data (operand) and the result is

placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY and AC are reset.
Logical OR register or memory with ccumulator
ORA

Example: ORA B or ORA M

The contents of the accumulator are logically ORed with the contents of the operand (register or

memory), and the result is placed in the accumulator.

If the operand is a memory location, its address is specified by the contents of HL registers. S, Z, P are

modified to reflect the result of the operation. CY and AC are reset.

Logical OR immediate with accumulator
ORI

8-bit data

Example: ORI 86H

The contents of the accumulator are logically ORed with the 8-bit data (operand) and the result is

placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY and AC are reset.
Rotate accumulator left
RLC

none

Example: RLC

Each binary bit of the accumulator is rotated left by one position. Bit D7 is placed in the position of

D0 as well as in the Carry flag. CY is modified according to bit D7. S, Z, P, AC are not affected.
Rotate accumulator right
RRC

none

Example: RRC

Each binary bit of the accumulator is rotated right by one position. Bit D0 is placed in the position of

D7 as well as in the Carry flag. CY is modified according to bit D0. S, Z, P, AC are not affected.
Rotate accumulator left through carry
RAL

none

Example: RAL

Each binary bit of the accumulator is rotated left by one position through the Carry flag. Bit D7 is

placed in the Carry flag, and the Carry flag is placed in the least significant position D0. CY is modified
according to bit D7. S, Z, P, AC are not affected.
Rotate accumulator right through carry
RAR

none

Example: RAR

Each binary bit of the accumulator is rotated right by one position through the Carry flag. Bit D0 is

placed in the Carry flag, and the Carry flag is placed in the most significant position D7. CY is modified
according to bit D0. S, Z, P, AC are not affected.
Complement accumulator
CMA

none

Example: CMA

The contents of the accumulator are complemented. No flags are affected.

Complement carry

CMC

none

Example: CMC

The Carry flag is complemented. No other flags are affected.

Set Carry
STC

none

Example: STC

The Carry flag is set to 1. No other flags are affected.

CONTROL INSTRUCTIONS
No operation
NOP

none

Example: NOP

No operation is performed. The instruction is fetched and decoded. However no operation is executed.

Halt and enter wait state

HLT

none

Example: HLT

The CPU finishes executing the current instruction and halts any further execution.

reset is necessary to exit from the halt state.

Disable interrupts
DI

none

Example: DI

An interrupt or

The interrupt enable flip-flop is reset and all the interrupts except the TRAP are disabled. No flags are

affected.

Enable interrupts
EI

none

Example: EI

The interrupt enable flip-flop is set and all interrupts are enabled. No flags are affected. After a system

reset or the acknowledgement of an interrupt, the interrupt enable flip- flop is reset, thus disabling the
interrupts. This instruction is necessary to re-enable the interrupts (except TRAP).
Read interrupt mask
RIM

none

Example: RIM

This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 and read serial data input

bit. The instruction loads eight bits in the accumulator with the following interpretations.

Set interrupt mask

SIM

none

Example: SIM

This is a multipurpose instruction and used to implement the 8085 interrupts 7.5, 6.5, 5.5, and serial data
output. The instruction interprets the accumulator contents as follows.

TIMING DIAGRAM:

Timing Diagram is a graphical representation. It represents the execution time taken by each instruction in a

graphical format. The execution time is represented in T-states.

Instruction Cycle

The time required to execute an instruction is called instruction cycle.

Machine Cycle

The time required to access the memory or input/output devices is called machine cycle.
T-State

The machine cycle and instruction cycle takes multiple clock periods.

A portion of an operation carried out in one system clock period is called as T-state.

Machine cycles of 8085

The 8085 microprocessor has 5 basic machine cycles. They are

1. Opcode fetch cycle (4T)

2. Memory read cycle (3 T)

3. Memory write cycle (3 T)

4. I/O read cycle (3 T)

5. I/O write cycle (3 T)

Opcode fetch machine cycle of 8085 :

Fig: Clock signal

Each instruction of the processor has one byte opcode.

The opcodes are stored in memory. So, the processor executes the opcode fetch machine cycle to fetch
the opcode from memory.

Hence, every instruction starts with opcode fetch machine cycle.

The time taken by the processor to execute the opcode fetch cycle is 4T.

In this time, the first, 3 T-states are used for fetching the opcode from memory and the remaining Tstates are used for internal operations by the processor.

Fig: Opcode fetch machine cycle

Memory Read Machine Cycle of 8085:

The memory read machine cycle is executed by the processor to read a data byte from memory.
The processor takes 3T states to execute this cycle.

The instructions which have more than one byte word size will use the machine cycle after the

opcode fetch machine cycle.

Fig: Memory Read Machine Cycle

Memory Write Machine Cycle of 8085

The memory write machine cycle is executed by the processor to write a data byte in a memory location.
The processor takes, 3T states to execute this machine cycle.

Fig: Memory Write Machine Cycle

I/O Read Cycle of 8085

The I/O Read cycle is executed by the processor to read a data byte from I/O port or from the
peripheral, which is I/O, mapped in the system.

The processor takes 3T states to execute this machine cycle.

The IN instruction uses this machine cycle during the execution.

Fig: I/O Read machine cycle