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Cadence Lab 8

This document provides instructions for setting up and using Cadence design software. It describes opening Cadence, navigating to the correct libraries, and exiting Cadence. Key steps include running Xming, logging in with a group name, navigating to the user's directory, sourcing the EE424 file to launch Cadence, and using the icfb command to open the software. The document also provides brief reminders about what to do each time Cadence is launched.

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Alamgir Khan
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75 views12 pages

Cadence Lab 8

This document provides instructions for setting up and using Cadence design software. It describes opening Cadence, navigating to the correct libraries, and exiting Cadence. Key steps include running Xming, logging in with a group name, navigating to the user's directory, sourcing the EE424 file to launch Cadence, and using the icfb command to open the software. The document also provides brief reminders about what to do each time Cadence is launched.

Uploaded by

Alamgir Khan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Department of Electrical Engineering

EE322: Computer Aided Design & Simulations


BEE-1ABC
Course Instructor: M. Ali

Lab-8: Behavioral Modeling in Verilog-A


Name

Reg. no.

Cadence Setup Guide: EE 424


A . cd userid
B . source .ee424
On the shell screen you should see done
C . icfb &
The icfb command will invoke the Cadence session. Two windows will open. The small
window is known as the Command Interpreter Window (CIW) and will be present
throughout your session. The other window is known as the Library Manager and it keeps
track of all design files you create. If the library manager doesnt open, then click
Tools => Library Manager
In the Library Manager window you should see the following libraries. If you do not, please
consult yourinstructor as soon as possible.
- NCSU_Analog_Parts
- NCSU_Digital_Parts
- cdsDefTechLib
- basic

Exiting Cadence

This completes the initial setup for Cadence. If you plan to continue using Cadence (e.g., to
do an assignment) skip this step. To exit Cadence, in t he Command Interpreter Window
(CIW) select
File->Exit
What to Do Each Ti me You Run Cadence
1.
a.
7.
8.
9.

Run Xming
Login as: type your group name
cd <userid>
source.ee424
icfb&

This will launch Cadence

Introduction
This tutorial will guide the readers through the basics of the Verilog-A modeling and Tools of the
Cadence Design framework to generate Verilog code.

Types of Libraries:
There are usually 3 types of libraries:
1. A set of common Cadence libraries- They come with the Cadence software and contain some
very basic components like such as C, R, L, Voltage and Current sources.
2. Libraries that come up with a certain design kit and that are related to a certain technology.
These are called as the Technology libraries. They can include different components that are
specifically being designed /modeled according to their manufacturers requirements. For
example, transistors with a certain model attached
3. User Designed libararies, where users can store their designs. They can include components
from both the cadence and technological libraries

Digital design
Digital design follows a top down methodology i.e. first code is written at a higher level of
abstraction in any HDL (hardware description language) and is transformed into hardware
using synthesizer.
Analog design
In Analog design bottom up approach is used i.e. designing has to be started from transistor
level.
Verilog- A
Verilog-A is hardware description language (HDL) for analog circuit and systems design.
The Verilog HDL was introduced in 1984 as a means for specifying digital systems at many
levels of abstraction, from behavioral to the structural.
The Verilog-A language allows the description of analog and/or mixed-signal systems with
varying amounts of detail. The analog behavioral capability allows the designer to span the
abstraction levels, allowing direct access to the underlying technology while maintaining
the capability of system-level modeling and simulation. As such, the analog and mixedsignal system can be described and simulated at a high-level of abstraction early in the
design cycle to facilitate full-chip architectural trade-offs. The resulting Verilog-A
description, as an executable specification, promotes communication and consistency
throughout the design process (from specification to implementation).

Structural descriptions are, in which a module is comprised of other child modules. Each
module in the structural definition of the system connects to one or more signals through
the modules ports or connection points.
Behavioral descriptions are, in a programmatic fashion with the Verilog-A language.
The behavior of a module is defined in terms of the values for each signal.
Mixed-level descriptions combine aspects of both structural and behavioral descriptions
at a variety of different abstraction levels.
Verilog modeling of a resistor.
module resistor(n 1 , n2);
inout n1 , n2;
electrical n1 , n2;
parameter real R = 1.0;
analog
I(n 1, n2) <+ V(n1, n2)/R;
Endmodule

The structure of the components in an analog system, and behavioral descriptions of


those components define the system of ordinary differential equations, or ODEs, that
govern the response of the analog system to an external stimulus. The process by
which the system of equations is derived is known as formulation.

Clicking on next will show up following window

Clicking on next will show up following window

After finishing following window will appear

Following window containing the symbol of the ADC will appear save this symbol.

Create a new cell view in which ADC will be tested.

Save this symbol

Import the ADC in the test schematic from your library and connect the Vpwl at Vin port
and Vpulse at clk port with the following properties.

Make an output bus (type 'W') from the "dout<3:0>" output of the ADC. Make four smaller
wires
(type w') attached to the bus and connect pins to them, named "dout<3>",
"dout<2>", "dout<1>", and "dout<0>". Name the bus "dout<3:0>" and the small wires the
same names that you gave their respective pins.

Vpwl
Time 1 = 0
Voltage 1 = 0 V
Time 2 = 100m s
Voltage 2 = 5 V

Vpulse
Voltage 1 = 0 V
Voltage 2 = 5 V
Delay time = 0 s
Rise time = 50n s
Fall time = 50n s
Pulse width = 500u s
Period = 1m s

Choose the simulator to be SpestreS

Following output should appear.

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