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Design Rule Checking

Design rule checking (DRC) determines if a chip layout satisfies recommended design rules. DRC checks for minimum widths, spacings, and enclosures between layers and identifies violations. DRC is crucial for improving chip yield by ensuring layouts can be manufactured reliably. DRC software takes the layout and design rules to check for issues and produces a report of violations. Major commercial DRC software includes products from Mentor Graphics, Cadence, and Synopsys.

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537 views3 pages

Design Rule Checking

Design rule checking (DRC) determines if a chip layout satisfies recommended design rules. DRC checks for minimum widths, spacings, and enclosures between layers and identifies violations. DRC is crucial for improving chip yield by ensuring layouts can be manufactured reliably. DRC software takes the layout and design rules to check for issues and produces a report of violations. Major commercial DRC software includes products from Mentor Graphics, Cadence, and Synopsys.

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Narendra Achari
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Design rule checking

Design Rule Checking or Check(s) (DRC) is the


area of Electronic Design Automation that determines
whether the physical layout of a particular chip layout
satises a series of recommended parameters called Design Rules. Design rule checking is a major step during Physical verication signo on the design, which
also involves LVS (Layout versus schematic) Check,
XOR Checks, ERC (Electrical Rule Check) and Antenna
Checks. For advanced processes some fabs also insist
upon the use of more restricted rules to improve yield.

(perhaps 400 nm as of 2007).


A two layer rule species a relationship that must exist
between two layers. For example, an enclosure rule might
specify that an object of one type, such as a contact or via,
must be covered, with some additional margin, by a metal
layer. A typical value as of 2007 might be about 10 nm.
There are many other rule types not illustrated here.
A minimum area rule is just what the name implies.
Antenna rules are complex rules that check ratios of areas of every layer of a net for congurations that can result
in problems when intermediate layers are etched. Many
other such rules exist and are explained in detail in the
documentation provided by the semiconductor manufacturer.

Design Rules

Academic design rules are often specied in terms of a


scalable parameter, , so that all geometric tolerances in
a design may be dened as integer multiples of . This
simplies the migration of existing chip layouts to newer
processes. Industrial rules are more highly optimized, and
only approximate uniform scaling. Design rule sets have
become increasingly more complex with each subsequent
generation of semiconductor process.

The three basic DRC checks


Width
Enclosure

2 Design Rule Checking software

Spacing

The main objective of design rule checking (DRC) is to


achieve a high overall yield and reliability for the design. If design rules are violated the design may not be
functional. To meet this goal of improving die yields,
DRC has evolved from simple measurement and Boolean
checks, to more involved rules that modify existing features, insert new features, and check the entire design for
process limitations such as layer density. A completed
layout consists not only of the geometric representation
of the design, but also data that provides support for the
manufacture of the design. While design rule checks do
not validate that the design will operate correctly, they are
constructed to verify that the structure meets the process
constraints for a given design type and process technology.

The basic DRC checks - width, spacing, and enclosure

Design Rules are a series of parameters provided by


semiconductor manufacturers that enable the designer to
verify the correctness of a mask set. Design rules are specic to a particular semiconductor manufacturing process. A design rule set species certain geometric and
connectivity restrictions to ensure sucient margins to
account for variability in semiconductor manufacturing
processes, so as to ensure that most of the parts work correctly.
The most basic design rules are shown in the diagram on
the right. The rst are single layer rules. A width rule
species the minimum width of any shape in the design.
A spacing rule species the minimum distance between
two adjacent objects. These rules will exist for each layer
of semiconductor manufacturing process, with the lowest layers having the smallest rules (typically 100 nm as
of 2007) and the highest metal layers having larger rules

DRC software usually takes as input a layout in the GDSII


standard format and a list of rules specic to the semiconductor process chosen for fabrication. From these it produces a report of design rule violations that the designer
may or may not choose to correct. Carefully stretching
or waiving certain design rules is often used to increase
performance and component density at the expense of
1

4 Free software

yield.
DRC products dene rules in a language to describe the
operations needed to be performed in DRC. For example,
Mentor Graphics uses Standard Verication Rule Format
(SVRF) language in their DRC rules les and Magma Design Automation is using Tcl-based language. A set of
rules for a particular process is referred to as a run-set,
rule deck, or just a deck.
DRC is a very computationally intense task. Usually
DRC checks will be run on each sub-section of the ASIC
to minimize the number of errors that are detected at the
top level. If run on a single CPU, customers may have to
wait up to a week to get the result of a Design Rule check
for modern designs. Most design companies require DRC
to run in less than a day to achieve reasonable cycle times
since the DRC will likely be run several times prior to
design completion. With todays processing power, fullchip DRCs may run in much shorter times as quick as
one hour depending on the chip complexity and size.
Some example of DRCs in IC design include:
Active to active spacing
Well to well spacing
Minimum channel length of the transistor
Minimum metal width
Metal to metal spacing
Metal ll density (for processes using CMP)
Poly density
ESD and I/O rules
Antenna eect

REFERENCES

Commercial DRC Software

Major products in the DRC area of EDA include:


Advanced Design System Design Rule Checker by
Agilent's EEsof EDA division
Calibre by Mentor Graphics
Diva, Dracula, Assura and PVS by Cadence Design
Systems
Hercules and IC Validator by Synopsys
PowerDRC/LVS by POLYTEDA LLC
Quartz by Magma Design Automation

Electric VLSI Design


staticfreesoft.com/

System

http://www.

5 References
Electronic Design Automation For Integrated Circuits
Handbook, by Lavagno, Martin, and Scheer, ISBN
0-8493-3096-3 A survey of the eld, from which
part of the above summary were derived, with permission.

Text and image sources, contributors, and licenses

6.1

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Design rule checking Source: https://en.wikipedia.org/wiki/Design_rule_checking?oldid=749630590 Contributors: Nixdorf, Ronz, Astronautics~enwiki, Altenmann, D6, Yurivict, Volfy, Gaius Cornelius, Smartyhall, SmackBot, LouScheer, ElementFire, A5b, Shantanudivekar, MarkGyver, Xoneca, Vanished user ty12kl89jq10, Ethan a dawe, Daisydaisy, Auntof6, Addbot, Materialscientist, XPEHOPE3,
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File:The_three_basic_DRC_checks.svg Source:
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checks.svg License: CC BY-SA 3.0 Contributors: Own work Based on w:File:BasicDRC.jpg Original artist: Xoneca (Based on work of
LouScheer)

6.3

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Creative Commons Attribution-Share Alike 3.0

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