VLSI DESIGN

UNIT-1
Introduction To IC Technology & Basic Electrical Properties
Introduction:
Till 1950s the electronic technology was vacuum tube based.
1947,transistor invention by William B Shockley et al revolutionised the field of electronics.
Integrated circuit era has began in 1960s.
Quest to integrated more devices per chip has resulted transition from SSI(Small Scale
Integration) to LSI (Large Scale Integration)to VLSI(Very Large Scale Integration) with 10
to 100 million devices per chip.
Measure of Progress- determined by number of transistors per chip,size of the chip, process
technology used within.
To produce smaller, faster, more reliable and less expensive systems which consume less
power.
Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by
combining thousands of transistors into a single chip. VLSI began in the 1970s when complex
semiconductor and communication technologies were being developed. The microprocessor is
a VLSI device. Before the introduction of VLSI technology most ICs had a limited set of
functions they could perform. An electronic circuit might consist of a CPU, ROM, RAM and
other glue logic. VLSI lets IC designers add all of these into one chip.
The first semiconductor chips held two transistors each. Subsequent advances added more
transistors, and as a consequence, more individual functions or systems were integrated over
time. The first integrated circuits held only a few devices, perhaps as many as ten diodes,
transistors, resistors and capacitors, making it possible to fabricate one or more logic gates on a
single device. Now known retrospectively as small-scale integration (SSI), improvements in
technique led to devices with hundreds of logic gates, known as medium-scale integration
(MSI). Further improvements led to large-scale integration (LSI), i.e. systems with at least a
thousand logic gates. Current technology has moved far past this mark and today's
microprocessors have many millions of gates and billions of individual transistors.
There was an effort to name and calibrate various levels of large-scale integration above VLSI.
Terms like ultra-large-scale integration (ULSI) were used. But the huge number of gates and
transistors available on common devices has rendered such fine distinctions moot. Terms
suggesting greater than VLSI levels of integration are no longer in widespread use.

Moores Law:
Intel co-founder Gordon Moore is a visionary published his paper Cramming more
components onto integrated circuits in Electronics, Volume 38, Number 8, April 19, 1965
His bold prediction, popularly known as Moore's Law, states that the number of transistors on a
chip will double approximately every two years.
Intel, which has maintained this pace for decades, uses this golden rule as both a guiding
principle and a springboard for technological advancement, driving the expansion of functions
on a chip at a lower cost per function and lower power per transistor, by shrinking feature sizes
while introducing new materials and transistor structures.
Technology Road Map

Transistor size and structure are at the very centre of delivering the
benefits of Moore's Law to the end user.

The smaller and more power efficient the transistor, the better.

Intel continues to predictably shrink its manufacturing technology in a

series of "world firsts": 45nm with high-k/metal gate in 2007; 32nm in
2009; and now 22nm with the world's first 3-D transistor in a high
volume logic process beginning in 2011.

With a smaller, 3-D transistor, Intel can design even more powerful processors with
incredible power efficiency. The new technology enables innovative micro
architectures, System on Chip (SoC) designs, and new productsfrom servers and
PCs to smart phones, and innovative consumer products.
Next generation is 14nm is expected to rule the product market by 2015.

System Integration Complexity:

Lowering the supply voltages and channel lengths together with increasing transistor per chip
ratios result in system with more efficient, smaller in size and can be packed at significantly
higher density.
Challenges are posed by smart appliances (eg Soc),complex imaging systems to silicon CMOS
technologies demanding low power high performance .
Major challenges due to constraints on power density(W/cm 2),high dynamic and static power
dissipation.

Successful designs are dependent on system design cycle and workable transistor
models. System design cycle flow chart of arithmetic processor(fundamental problem at hand to
physical layout with low power and min areas as important design criteria)

VLSI Design Cycle

Transistor models are characterized by figure of merit that depends on

1.
2.
3.
4.
5.
6.
7.
8.
9.

Performance
Level of integration and cost
Minimum future size
Number of gates
Power Dissipation
Gate delay
Die size
Testing
Reliability

Within the bound of MOS technology the possible circuit realization are based on
PMOS,NMOS,CMOS & Bi-CMOS

Comparison between CMOS and Bipolar Transistors

Speed Power Performance of available technologies:

Basic MOS Transistor:

MOS transistor is a majority carrier device in which current in a conducting channel between
the source and drain is controlled by the applied gate voltage. In NMOS the majority carriers
are electrons and in PMOS the majority carriers are holes. The top layer is called as Gate which
is nothing but Polysilicon which is a good conducting material for controlling the gate voltage.
Polysilicon has multicrystalline structure and it is made from silicon with many small crystals.
The middle layer is very thin layer which is called as thin oxide or silicon dioxide or gate oxide
which is used for isolating different layers. The bottom layer is doped silicon body.

nMOS enhancement mode Transistor

nMOS depletion mode Transistor

MOS Transistors when Vds=0v Source Vgs,Vsb=0V

Enhancement mode transistor (nMOS):

Source and drain regions are formed by doping desired n-impurity

concentration.

Source and drain are separated by two back to back connected diodes
hence electrons flows from source to drain. Depletion region surrounds
around source and drain junctions as they are reverse biased.

Gate oxide (Sio2) is grown above substrate between source and drain
while polysilicon/metal is deposited over it.

Channel is not formed when gate voltage is not applied(Vgs=0V)

There are two electric fields in the transistor ,vertical from gate to
substrate due to Vgs, horizontal from drain to source due to Vds.

nMOS depletion mode MOSFET:

Transistor is normally ON.The ntype impurities are buried in the channel area.
When Vgs=0V, Vd>0 V current flows in the transistor.
When Vgs<0V, the current decreases towards OFF state as the electrons repel
away from the surface creating depletion region. The channel disappers
gradually.
For Vg>0V the depletion MOSFET acts as enhancement MOSFET.

When positive gate voltage is applied the positive voltage on the gate plate attracts the minority
carriers (electrons) from the substrate.
This also uncovers the positive ions near the surface forming depletion region.
At a particular gate voltage the number of electrons near the surface
become equal to the doping concentration of the substrate. The surface inverts to n-type. This
voltage is known as Threshold Voltage (Vth). A uniform channel is formed near the surface
at threshold voltage(Vgs=Vth)

No current flows in transistor until Vds>0V)

Current flows from drain to source as electrons move through the channel under the
influence of the horizontal electric field as well as vertical electric field.
There is voltage drop in the channel due to VDS varying with distance, (more
near the drain end).
Effective gate voltage is Vg=Vgs-Vth.There will be no voltage available to invert
the channel at the drain end so long as Vgs-Vth>=Vds.
The limiting condition comes when Vgs-Vth=Vds

For all voltages Vds<Vgs-Vth the transistor is in non-saturated region of operation. As the
effective voltage is insufficient to invert the surface near the drain end the channel starts to
pinch off. As the Vds is further increased the pinch off point moves towards the source.

Eventhough there is no channel the constant electric field in the Depletion region makes charge
carriers to move with constant veltocity making Current constant.
nMOS Fabrication

Fabrication process of nMOS is relevant to pMOS ,CMOS and BiCMOS except a few
additional processing steps.
1.Wafer(substrate)

Processing is carried out on thin wafer from single crystal silicon into which p-type of
impurities are introduced during crystal growth.
75 to 150mm diameter, 0.4 mm thick doped with 1015 to 1016/cm3.
Resistivity range between 25ohm to 2 ohm-cm
2. A thick layer of field oxide of 1um is grown over the substrate.
This field oxide acts as barrier to dopants during processing.
Provides a general insulating layer over substrate over which other layers are deposited and
patterned. Wet oxidation is performed and used for isolation of devices.

3. A polymer known as photoresist is dropped over the surface & spun so that it is equally

distributed.
The wafer is now heated so that Photoresist sticks to the substrate for further processing

4. Photoresist layer is exposed to UV light through a mask which defines the active region of
the transistor in which source, drain implantations and channel region are defined.

5. UV lights weakens the bonds of photoresist and is removed and field oxide is etched in the
exposed areas

6. Thin oxide (dry) is grown over the Substrate which acts as the gate Oxide for the transistor.
Polysilicon is deposited using CVD over the thin oxide and patterned to form the gate.

7. Thin oxide is removed in the exposed areas .Source and drain diffusion is performed at high
temperatures.
By passing a gas containing dopants(eg Phosphine) over the substrate for Phosphorus
impurities.
Polysilicon gate and filed oxide acts as mask during diffusion process.

8. Thick oxide is grown over all again and is masked with photoresist and etched to expose
selected areas of Polysilicon gate, source and drain areas and contact holes are made.

9. The whole substrate is covered with metal and masked so that it is selectively etched to form
contact areas at the terminals of the transistor.

Summary of an NMOS Process:

1. Processing takes place on a p-doped silicon crystal wafer on which is grown a thick
layer of SiO2.
2. Mask-1---Pattern SiO2 to expose the silicon surface in areas where paths in the
diffusion layer or source drain or gate areas of transistors are required.Deposit thin
oxide overall. For this reason, this mask is often known as the thinox mask, but some
texts refer to it as the diffusion mask.
3. Mask-2--- Pattern the ion implantation within the thinox region where depletion mode
devices are to be produced ----self-aligning.
4. Mask-3---Deposit Polysilicon over all (1.5 micrometer thick typically), then pattern
using mask-3. Using the same mask, remove thin oxide layer where it is not covered by
Polysilicon.
5. Diffuse n+ regions into areas where thin oxide has been removed. Transistor drains and
sources are thus self aligning with respect to the gate structure.
6. Mask-4---Grow thin oxide over all and then etch for contact cuts.
7. Mask-5---Deposit metal and pattern with mask-5
8. Mask-6---Would be required for the over glassing process step.

CMOS Fabrication :
Cmos fabrication can be carried out:
P-well Process

N-well Process
Twin tub process

P-well Process:
1. A Thick field oxide is grown over the wafer. A P-well diffusion is carried out in the ntype substrate

During P-well diffusion , care should be taken the doping concentration and depth of well
should not affect the threshold voltage and breakdown voltages of the n-transistors. For
Low threshold voltage deep wells are required which increases spacing between NMOS
and PMOS transistors.
2. Active areas of nMOS and pMOS devices are defined through lithography and etching.
A thin layer of gate oxide is grown over the substrate.
A Layer of polysilicon is deposited over the surface and patterned to form gate for

both

nMOS and pMOS devices

3. The P-well is masked through P+ Mask during p type diffusion so that It doesnt affect
the characteristics of nMOS transistors in it.

4. The PMOS transistors are masked through P+ negative mask and N-type source and
Drain diffusions are carried out.

CMOS P-Well inverter showing VDD and VSS connections

Summary of Processing steps:

1. Mask 1- to form p-well the areas are defined by the mask at this level. nMOS transistors
are fabricated in p-well.
2. Mask 2- Thinox regions are defined using this mask. Thick oxide is removed and a thin
dry oxide (gate oxide) is grown and patterned.
3. Mask 3- Gate oxide is patterned in the previous step, now polysilicon is deposited over
the chip and patterned to form the gate areas in both pMOS and nMOS device active
areas.
4. Mask 4- using a P+ mask the nMOS active area(P-well) is covered and P type diffusion is
done in the remaining areas of the substrate to form source and drain regions of pMOS
transistors.
5. Mask 5- p- mask is used to cover the pMOS transistor active areas and n type diffusion is
performed through this mask to form source and drain areas of the nMOS transistors in P-

well.
6. Mask 6- Thick oxide is grown throughout the chip and contact cuts are opened through
this mask.
7. Mask 7- Metal is deposited in the contact cuts and patterned through this mask. Mask 8- A
overall passivation layer (over glass) is deposited and openings for
8. Bonding pads are patterned using this mask.
Remember thick field oxide is grown using wet oxidation while gate oxide is grown through
dry oxidation. Because it has to be pure and defect free. Field oxide is used to separate the
transistors, active areas and covering the chip after all processing steps are completed. It serves
as a protecting blanket layer

N-well Process:
N-well CMOS circuits are superior to p-well because of low substrate bias effects on threshold
voltage and lower parasitic capacitances associated with source and drain regions.

Berkely Nwell Fabrication Process:

Twin Tub Process:

1. This technology provides the basis for separate optimization of the nMOS and pMOS
transistors, thus making it possible for threshold voltage, body effect and the channel
transconductance of both types of transistors to be tuned independently.
2. The starting material is a n+ or p+ substrate, with a lightly doped epitaxial layer on top.
This epitaxial layer provides the actual substrate on which the n-well and the p-well are
formed.
3. Since two independent doping steps are performed for the creation of the well regions,
the dopant concentrations can be carefully optimized to produce the desired device
4.

characteristics.
In the conventional p & nwell CMOS process, the doping density of the well region is
typically about one order of magnitude higher than the sub-strate, which, among other
effects, results in unbalanced drain parasitic.The twin-tub process avoids this problem.

Twin tub based CMOS inverter

BiCMOS Technology:
The limitations of MOS transistors are limited load driving capabilities. Because of
limited current sourcing and sinking of PMOS and NMOS devices. Hence Bipolar transistors
near the outputs of the CMOS logic known as BiCMOS technology serve the purpose of low
power as well as high fanout.
BJTs provide high gain and better noise and high frequency characteristics than MOS
transistors. BiCMOS gates are used where speed as well as high driving capabilities are
required.(not always like ALU,ROM and a register file).
Fabrication of CMOS and bipolar transistors need not be carried out separately.

With few additional processing steps of CMOS processing npn transistors with good
performance characteristics can be achieved. Two additional layers needed are n+ subcollector
region and P+ base layer.The npn transistor is formed in a N-well and additional P+ base region
is located in the well to form the base region of the transistor.

The buried subcollector (BCCD)is added to reduce the N-well (collector) resistance and
improve the quality of the bipolar transistor.
Formation of two additional layers requires three additional processing steps and masks
a) p+ base region.
b) n+ collector region.
c) The buried sub-collector

Basic electrical properties of MOS &BICMOS:

Ids-Vds relationships:

We know that charge induced in a channel Qchannel = CV

Where C = Cg =EoxWL/tox = CoxWL
Cox=Eox/tox
Where Eox=3.9Eo
Eo = Permitivity, Er= Relative Permitivity
V=Vgc-Vt = (Vgs-Vds/2)-Vt
Qchannel = Cox WL (Vgs-Vds/2)-Vt

Time for carrier to cross channel:

t=L/ v
Now we know
How much charge Qchannel is in the channel
How much time t each carrier takes to cross

Drain to source current Ids vs Vds vs Speed

As we know that as the voltage is applied on the gate which causes the charge to induced in the
channel between source and drain, which may then be caused to move from source to drain
under the influence of electric field created by voltage Vds applied between drain and source.
Current Ids =Charge Induced in the channel (Qc)/Electron Transit time (Tsd from source to
drain)
Transit time (Tsd) = Length of the channel (L)/Velocity (v) ----------Eqn (1)
But Velocity = Eds ------------------------------Equation (2)

Where =Electron or hole mobility (surface)

Eds=Electric field (drain to source)
Now
Eds=Vds/L
From Equation (2)
Velocity =Vds/L
From Equation (1)

The above expression shows speed Vs Typical values of n=650cm2V sec (surface)
p=240cm2V sec (surface)
Similarly for PMOS it is mentioned below

The above figure shows how PMOS behaves in Linear, Saturation and Cut off mode and how
much voltage needs to be applied.
PMOS:
Things to do
1. Change the polarities of all the voltages and reverse the direction of current flow
2. Reverse the roll of electrons and holes
3. Change p type to n type
4. Change N type regions to P type regions

5. We need to make sure that PN junctions in Mosfet (either NMOS or PMOS do not become
forward bias).
6. In PMOS the current flow is due to the motion of positively charged holes and also
Gate should be sufficiently negative to attract minority charge carriers holes to the
silicon surface.
7. Current flow will be controlled by Vsgp and Vsdp and Idp flows out of the drain electrode.
8.Cut off occurs at Vsgp<Vtp or Vgsp>Vtp where Vgs=Vg-Vs which indicates that source to
gate voltage is not sufficient to support the formation of a hole inversion layer.
9. The equation for linear is Ids= - (Vgs-Vt) Vds-Vdssquare/2) and the condition is
Vdsp>Vgsp-Vtp and Vgsp<Vtp
10. The equation for Saturation is Ids= (Vgs-Vt) wholesquare/2 and the condition is
Vdsp<Vgsp-Vtp and Vgsp<Vtp
11. The condition to form a channel in PMOS is Vgsp<Vtp
12. Below are the diagrams for PMOS.

CMOS Latchup:
What is Latchup?
Latch up is a state where a semiconductor device undergoes a high-current state as a result of
interaction between a PNP and an NPN Bipolar transistor or It is a generation of low
impedance patch between Vdd and Vss rails due to the interaction of PNP and NPN transistors.
The PNP and NPN transistors can be natural to the technology, or parasitic devices. In CMOS
technology, these are typically parasitic devices. For each p-channel MOSFET (metal oxide
semiconductor field effect transistor) device, there is a corresponding parasitic PNP element
formed between the p-channel diffusion, the n-well and the substrate.
For each n-channel MOSFET (NMOS) device, there is a corresponding parasitic NPN element
formed between the n-channel diffusion, the p substrate and the n-well of the p-channel
MOSFET. For each inverter gate, there are corresponding PNP and NPN parasitic bipolar
elements.
When interaction occurs between a PNP and an NPN bipolar transistor, regenerative feedback
between the two transistors can lead to electrical instability. These BJTs form a siliconcontrolled Rectifier (SCR) with positive feedback and virtually short circuit the power rail to
ground, Thus causing excessive current flows and even permanent device damage.

The IV characteristic is an S-type IV characteristic with both a low-current/high-voltage state

and a high-current/low-voltage state (Figure 1.2 below ). In an S-type I V characteristic, there
are multiple current states for a given voltage level; the state it chooses is a function of the
circuit load line.
It is off in normal operation and can be triggered on in a high-current state. In this state, it
establishes a high current at a low-voltage, allowing a low impedance shunt.
When the two transistors are coupled, the combined device acts as a four-region device of
alternating p- and n-doped regions with three physical pn metallurgical junctions, forming a
pnpn structure. Why are we concerned about latchup? When these parasitic pnpn elements
undergo a high-current state, latchup can initiate thermal runaway and can be destructive.
Latchup events can lead to destruction of a semiconductor chip, package or system. The current
magnitude is such that typically the semiconductor silicon, aluminum and copper metallization
fails, and sometimes the package materials melt.
Note that another indicator of latchup is the package cracking, melting, delamination
,separation. Another clear indicator, on a system level, is smoke.

In these cases, it is difficult to provide chip-level failure analysis due to the magnitude of the
package and system damage.
When the card smoke is evident, the module package is melted and the silicon chip is molten,
this is a good indicator that latchup has occurred in your semiconductor chip.Back to the
semiconductor device level, conceptually the two transistors can be understood as acrosscoupled pnp and npn bipolar junction transistor (BJT) device, where the base of the pnp BJT
device is the collector of the npn BJT device and the base of the npn is the collector of the pnp
BJTdevice.
Application of a positive bias on the emitter of the pnp element and a ground potential on the
emitter of the npn element establishes a voltage across the pnpn.
The positive voltage provides forward biasing of the emitterbase junctions of the pnp and npn
transistors.The basecollector junction of the pnp (which is also the basecollector junction of
the npn) is in a reverse-biased state.
This prevents current flow from the anode of the pnpn to the cathode. As the voltage is
increased, the voltage across the basecollector junction increases.
This mode of operation is called the forward blocking state. In order for current to flow
efficiently from the pnpn anode to the cathode, the basecollector junction must allow current
to flow. For current continuity at the cross-coupled nodes, the collector current of the PNP
transistor must equal the base current of the NPN transistor, as well as the collector current of
the NPN transistor must equal the base current of the PNP transistor.

Mathematically, the coupling is established through solving Kirchhoffs current law at the
basecollector nodes.
In this form, the standard equations of bipolar transistors can be used to quantify the interaction
and current in the PNPN structure. Hence, the two nodal equations can be expressed as
Icp = Ibn;
Icn = Ibp;
Where Icp and Icn are the collector currents of the PNP and NPN bipolar junction transistors,
respectively,and likewise, Ibn and Ibp are the base currents of the NPN and PNP bipolar
junction transistors,respectively.

The total current through the PNPN structure is equal to the emitter current of the PNP or NPN
bipolar transistor, Iep and Ien, respectively. From Kirchoffs current law in the transistor, the
emitter current must equal the sum of the base and collector currents
I = Iep = Icp + Ibp
From the coupling relationships, the current can be expressed as
I =Iep = Icp + Icn = Ibp + Ibn = Icn + Ibn = Ien = I:
Solving for the current as a function of the two collector current relationships, the collector
current can be represented as a function of the emitter current:
Icp = Iep + Icp0;
Icn = Ien + Icn0;
Where the collector current is equal to the product of the collector-to-emitter transport factor
and theemitter current summedwith the basecollector leakage. Solving for the current through
the PNPN structure,
I = (Icp0 + Icn0)/ 1-(n+p)
From this analysis, it is clear that the current is infinite, when the denominator is equal to zero
or If n+ p =1 then the current goes to infinite and Latchup occurs.
Latchup also occurs when the products of current gains of both the transistors are greater than 1
(1x2>1) which means when one transistor goes ON then it drives the other transistor to be ON
which can be either due to the IR drop of two resistors or due to the noise or ground bounce
( small signal from the ground) and power bounce.
Prevention of Latchup
From fig (b), if we make a doping concentration in such a way that the Voltage drop across R
well should be less than the break down voltage of a PNP transistor and also the Voltage drop
across RSUB should be less than the break down voltage of NPN transistor Latchup can be
prevented.
Reducing both the resistances by connecting one more resistance in parallel so that Latchup can
be prevented.
By placing the Guard Rings we can prevent latchup
By putting Well taps in Diffusion and Vdd/Vss Rails we can prevent Latch up.
Avoid forward biasing of the source/drain junctions so as not to inject high currents , this
solution calls for the use of slightly doped epitaxial layer on top of the heanily doped substrate
and has the effect of shunting the lateral currents from the vertical transistor through the low
resistance substrate.
Carefully protect electrostatic protection devices associated with I/O pads with guard rings.
Electrostatic discharge can trigger latchup. ESD enters the circuit through an I/O pad, where it
is clamped to one of the rails by the ESD protection circuit. Devices in the protection circuit
can inject minority carriers in the substrate or well, potentially triggering latchup.
Sudden transients on the power or ground bus, which may occur if large numbers of transistors
switch simultaneously, can drive the circuit into latchup. Whether this is possible should be
checked through simulation

MOS TRANSISTOR THRESHOLD VOLTAGE:

The threshold voltage Vth for a nMOS transistor is the minimum amount of the gate-to-source
voltage VGS necessary to cause surface inversion so as to create the conducting channel
between the source and the drain. For VGS< Vth , no current can flow between the source and the
drain. For VGS> Vth , a larger number of minority carriers (electrons in case of an nMOS
transistor) are drawn to the surface, increasing the channel current. However, the surface
potential and the depletion region width remain almost unchanged as VGS is increased beyond
the threshold voltage.

The physical components determining the threshold voltage are the following.
work function difference between the gate and the substrate.
gate voltage portion spent to change the surface potential.
gate voltage part accounting for the depletion region charge.
gate voltage component to offset the fixed charges in the gate oxide and the silicon-oxide
boundary.

Although the following analysis pertains to an nMOS device, it can be simply modified to
reason for a p-channel device.
The work function difference
between the doped polysilicon gate and the p-type
substrate, which depends on the substrate doping, makes up the first component of the
threshold voltage. The externally applied gate voltage must also account for the strong
inversion at the surface, expressed in the form of surface potential 2

where denotes the distance between the intrinsic energy level EI and the Fermi level EF of
the p-type semiconductor substrate.
The factor 2 comes due to the fact that in the bulk, the semiconductor is p-type, where EI is
above EF by

, while at the inverted n-type region at the surface EI is below EF by

thus the amount of the band bending is 2

, and

. This is the second

component of the threshold voltage. The potential difference

between EI and EF is given as

Where k: Boltzmann constant, T: temperature, q : electron charge NA : acceptor concentration

in the p-substrate and n i : intrinsic carrier concentration. The expression kT/q is 0.02586 volt
at 300 K.
The applied gate voltage must also be large enough to create the depletion charge. Note that
the charge per unit area in the depletion region at strong inversion is given by

Where is the substrate permittivity. If the source is biased at a potential VSB with respect to
the substrate, then the depletion charge density is given by

The component of the threshold voltage that offsets the depletion charge is then given by
-Qd /Cox , where Cox is the gate oxide capacitance per unit area, or Cox
=
(ratio of the oxide permittivity and the oxide thickness).
A set of positive charges arises from the interface states at the Si-SiO2 interface. These
charges, denoted as Qi , occur from the abrupt termination of the semiconductor crystal lattice
at the oxide interface. The component of the gate voltage needed to offset this positive charge
(which induces an equivalent negative charge in the semiconductor) is -Qi /Cox. On combining
all the four voltage components, the threshold voltage VTO, for zero substrate bias, is
expressed as
For non-zero substrate bias, however, the depletion charge density needs to be modified to
include the effect of VSB on that charge, resulting in the following generalized expression for
the threshold voltage, namely

The generalized form of the threshold voltage can also be written as

Note that the threshold voltage differs from VTO by an additive term due to substrate bias. Thi
term, which depends on the material parameters and the source-to-substrate voltage VSB , is
give by
Thus, in its most general form, the threshold voltage is determined as

........................... (2.1)
in which the parameter
by

, known as the substrate-bias (or body-effect ) coefficient is given

.................................... (2.2)
BODY EFFECT OR BODY BIASING OR SUBSTRATE BIASING OR BACK
GATE EFFECT
It refers to the changes in the threshold voltage by the change in the Vsb
(Source to Bulk Voltage), Source to bulk voltage because the body influences
the threshold voltage when it is not tied to the source. It can also be called as a
back gate effect, Substrate bias effect, Bias effect or body bias effect. It can be
given by an equation as below.

where

is the threshold voltage when substrate bias is present,

is the source-to-body substrate bias,

is the surface potential,
is threshold voltage for zero substrate bias,
is the body effect parameter,
is oxide thickness,
is oxide permittivity,
is the permittivity of silicon,

is a doping concentration,
is the charge of an electron.
If Vsb=0 then we get Vth =Vth0 which is for the lower transistor where the
input is A and the substrate bias is 0
Threshold voltage depends upon Vsb, Process , Doping and temperature
Body effect can be explained with the below example in order to understand.

Consider that three NMOS transistors which are connected in series where the
inputs for each of these are A, B, C ,
The source to substrate voltage is grounded ( Vsb=0).
The minimum voltage which is required to make the X transistor ON is Vt1 ,
The minimum voltage required to make the Y transistor on is Vt1+Vt2,
The minimum voltage required to make the Z transistor ON is Vt1+Vt2+Vt3 so
from these we can say that the faster input is A rather than B and C because it
requires more threshold voltage to make the transistors Y and Z on due to body
effect.
We have seen that the effect of Body is more for the C transistor. It means upper
transistor experiences more effect.
The above example in logic design is same as NAND gate where A, B, C are the
inputs for the below NAND gate. C is faster than A and B

If by any means foundry would like to vary the threshold voltage then it is
possible and it is not in designers control.
Disadvantage: Due to the body effect the threshold voltage varies and the circuit
performance becomes low.
MOS Transistor Transconductance ( gm) and Output Conductance (gds)
Transconductance expresses the relationship between output current Ids and the
input voltage Vgs and is defined as
gm = delta Ids/delta Vgs where Vds is constant
To find an expression for gm in terms of circuit and transistor parameters,
consider the charge in the channel is Qc
We know that Qc/Ids =T where T is the transit time,Thus change in current
Delta Ids=delta Qc/Tds
2

We know that Tds=L /Vds

Thus delta Ids =delta Qc Vds /L
Delta Qc=Cg delta Vgs

Delta Ids=Cg delta Vgs x Vds/L

gm = delta Ids /delta Vgs=Cg Vds/L

Vds=Vgs-Vt in saturation or the point where it moves from linear to saturation

or pinch off point.
So gm = Cg(Vgs-Vt)/L

If we substitute Cg=EinsEoWL/Tox
Or gm= (Vgs-Vt) or CoxnW(Vgs-Vt)/L-----Eqn (3)

It is possible to increase the gm of a MOS device by increasing the width

however this will also increase the input capacitance and area occupied. Eqn 3
suggests that gm increases with the overdrive if W/L is constant whereas Eqn 5
implies that gm decreases with the overdrive if Id is constant and Eqn 4 implies
that gm increases in square law with Id if W/L is constant.
2
We know that Ids= 1/2CoxnW (Vgs-Vt) /L
Vgs-Vt=under root (2Id/nCoxW/L) -----------------Eqn (4)
So gm= 2Id/(Vgs-Vt)---------------------------Eqn (5)

When the mosfet is in linear region where Vds is small the conductance gd is
obtained by differentiating Ids w.r.t vgs at Vds constant
We get the value as
gm in linear =CoxnW(Vds)/L=Vds
Output conductance (gds)
It is also called as small signal conductance or output conductance and it is
given by the equation
gd=delta Ids/delta Vds at constant Vgs
As per the linear and saturation current equations we can get the values for gd in
Linear and saturation
gd = CoxWn ( Vgs-Vtn-Vds) and in Linear region Vds<<Vgs-Vt so the above
equation can be simplified to
gd = CoxWn ( Vgs-Vtn)--------------Equation (1 ) represents in Linear region
Present day VLSI circuits are Mosfet based as already discussed. The
performance of the circuit depends on switching speed which in turn depends
upon the parameter known as ON resistance given by

Ron = Rchannel =1/gd=L/CoxnW(Vgs-Vtn)

To decrease the Ron the width of the transistor has to be increased but that
increases the area of the chip in return.
Figure of Merit
It is defined as the ratio of Transconductance to the gate capacitance
Wo = gm/Cg
= n(Vgs-Vt)/L

Where gm =CoxW(Vgs-Vt)/Ln
Cg=CoxWL
Switching speed is dependent upon
Gate voltage above the threshold
Inversely as square of channel length. This supports CMOS scaling, i.e., when
channel length is reduced for a process the speed of the circuit increases by root
2 times.
Complementary CMOS Inverter - DC Characteristics
A complementary CMOS inverter is implemented as the series connection of a
PMOS and an NMOS , as shown in Figure 2.
To derive the DC transfer characteristics for the CMOS inverter, which depicts
the variation of the output voltage (Vout) as a function of the input voltage (Vin),
one can identify five following regions of operation for the n -transistor and p
-transistor.

Figure 2 A CMOS inverter shown with substrate Connections

Let Vtn and Vtp denote the threshold voltages of the n and p-devices
respectively. The following voltages at the gate and the drain of the two devices
(relative to their respective sources) are all referred with respect to the ground
(or VSS), which is the substrate voltage of the n -device, namely

Vgsn =VIN, Vdsn =Vout, Vsgp =VDD-Vin, and Vdsp =Vout -VDD.
The voltage transfer characteristic of the CMOS inverter is now derived with
reference to the following five regions of operation:
Region 1: the input voltage is in the range

. In this condition, the n -

transistor is off, while the p -transistor is in linear region (as

).

Figure 2.11: Variation of current in CMOS inverter with Vin

No actual current flows until Vin crosses Vtn , as may be seen from Figure 2.11.
The operating point of the p -transistor moves from higher to lower values of
currents in
linear zone. The output voltage is given by
Figure 2.12.

, as may be seen from

Region 2 : the input voltage is in the range

. The upper limit of Vin is
Vinv , the logic threshold voltage of the inverter. The logic threshold voltage or
the switching point voltage of an inverter denotes the boundary of "logic 1" and
"logic 0". It is the output voltage at which Vin = Vout . In this region, the n-

transistor moves into saturation, while the p-transistor remains in linear region.
The total current through the inverter increases, and the output voltage tends to
drop fast.

Figure 2.12 Transfer characteristics of the CMOS inverter

Region 3: In this region,
. Both the transistors are in saturation, the drain
current attains a maximum value, and the output voltage falls rapidly. The
inverter exhibits gain. But this region is inherently unstable. As both the
transistors are in saturation, equating their currents, one gets (as Vgsn=Vinv,
Vsgp=Vdd-Vinv).

Where
gets

and

. Solving for the logic threshold voltage Vinv, one

Where D is same as Tox ( thin oxide) and K=Cox/Tox and Cox=Eins Eo

Note that if

and

, then Vinv =0.5 VDD.

Where Vinv is also called Midpoint voltage or Switching threshold

Region 4: In this region,

. As the input voltage Vin is increased
beyond Vinv, the n -transistor leaves saturation region and enters linear region,
while the p -transistor continues in saturation. The magnitude of both the drain
current and the output voltage drops.
Region 5: In this region,
. At this point, the p -transistor is
turned off, and the n -transistor is in linear region, drawing a small current,
which falls to zero as Vin increases beyond VDD -| Vtp|, since the p -transistor
turns off the current
path. The output in this region is
.
As may be seen from the transfer curve in Figure 2.12, the transition from
"logic 1" state (represented by regions 1 and 2) to logic 0 state (represented
by regions 4 and 5) is quite steep. This characteristic guarantees maximum noise
immunity.
ratio: One can explore the variation of the transfer characteristic as a
function of the ratio
.
As noted from (2.15), the logic threshold voltage Vinv depends on the ratio
The

CMOS inverter with the ratio

=1 allows a capacitive load to charge and
discharge in equal times by providing equal current-source and current-sink
capabilities.
Consider the case of
>1. Keeping fixed, if one increases
impedance of the pull-down n -transistor decreases.

, then the

It conducts faster, leading to faster discharge of the capacitive load. This ensures
quicker fall of the output voltage Vout, as Vin increases from 0 volt onwards.
That is,
the transfer characteristic shifts leftwards. Similarly, for a CMOS inverter with
<1, the transfer curve shifts rightwards. This is portrayed in Figure 2.13.
Note: Noise margin is not in the syllabus but this is a hidden topic in CMOS
Inverter, However if JNTU asks then you can proceed with the explaination.
Noise Margin: is a parameter intimately related to the transfer characteristics.
It allows us to estimate the allowable noise voltage on the input of a gate so that
the output will not be affected.

Keypoint: If we have more noise Immunity it is good, If we get more noise then
even in the presence of more noise the output will not get effected.
Noise margin (also called noise immunity) is specified in terms of two
parameters - the low noise margin NML, and the high noise margin NMH.
Referring to Figure 2.14,
NMlis defined as the difference in magnitude between the maximum LOW input
voltage recognized by the driven gate and the maximum LOW output voltage of
the driving gate. That is,
NML =| VILmax - VOLmax |
Similarly, the value of NMH is the difference in magnitude between the
minimum HIGH output voltage of the driving gate and the minimum HIGH
input voltage recognizable by the driven gate. That is,
NMH =| VOHmin - VIHmin |
Where VIH min: Minimum HIGH input voltage

VIL max: Maximum LOW input voltage

VOH min: Minimum HIGH output voltage
VOL max: Maximum LOW output voltage

Figure 2.13 Variation of shape of transfer characteristic of the CMOS inverter

with the ratio

Figure 2.14 Definition of noise margin

Figure 2.14 illustrates the above four definitions.
Ideally, if one desires to have VIH =VIL, and VOL =VOH in the middle of the
logic swing, then the switching of states should be abrupt, which in turn
requires very high gain in the transition region.
To calculate VIL, the inverter is supposed to be in region 2 (referring to Figure
2.12) of operation, where the p -transistor is in linear zone while the n
-transistor is in saturation.
The parameter VIL is found out by considering the unity gain point on the
inverter transfer characteristic where the output makes a transition from VOH.
Similarly, the parameter VIH is found by considering the unity gain point at the
VOL end of the characteristic.

If the noise margins NMH or NML are reduced to a low value, then the gate may
be susceptible to switching noise that may be present at the inputs.
The net effect of noise sources and noise margins on cascaded gates must be
considered in estimating the overall noise immunity of a particular system. Not
infrequently, noise margins are compromised to improve speed.
PASS TRANSISTOR
Pass transistors are single MOSFET that passes the signal between the drain and
source terminals instead of fixed power supply value.
Pass Transistors can be used in transmission gates in most circuits. They require
less area and wiring, but cannot pass the entire voltage range. When choosing
between the two logics , NMOS are preferred for this application since the
larger electron mobility implies faster switching than could be obtained with
PMOS of the same size.
The switch is controlled by the gate voltage Vg which means Gate voltage is
used to make the transistor ON or OFF. If gate voltage is 0 then the transistor is
OFF and if the gate voltage is 1 the transistor is ON.
We will see the function of NMOS Pass transistor ( kindly refer page no.2)
As told earlier that source and drain are interchangeable for NMOS or PMOS
transistor.
Case (a) where the Gate voltage is high ( NMOS is on ) and the input voltage is
logic 0 then the output voltage is 0 ( That means when we are passing logic 0
from the input and the output is not degraded we are getting full output as 0.
Case (b) Where the Gate voltage is high ( NMOS is on again) and if we want to
pass high input then the output voltage will be degraded and the output voltage
is VddVth ( We wont get full Voltage swing) that means there is a threshold drop
( The capacitor charges upto Vdd and after this point it goes into cut off)
Note: Once the output reaches Vdd-Vth and if it falls below the threshold
voltage then the transistor cuts off.
For the below circuit, As the source can rise within a threshold voltage of the
gate, the output of several transistors in series is no more degraded than that of a
single transistors, However even if a degraded output drives the gate of another
transistor, the second transistor can produce an even further degraded output
which is shown in the next case.

Case (c ): If the NMOS transistors are cascaded as below and if we want to pass
high voltage then at each and every stage of the output you will get Vdd-Vth,
Vdd-2Vth, Vdd-3Vth and so on.

As per the above diagram we can see that the output voltage is getting degraded
as the transistors are getting cascaded that means the output is getting charged
upto Vdd-Vth and if the same voltage is been applied to the other transistor that
means the gate of the second transistor the output will further degrades, etc.
If we consider Vdd=5V, Vth=1V then the output voltage for the last transistor is
Vdd-3Vth =2V and if this 2V drives the other Inverter causes static power
consumption and the PMOS transistor will be weakly conducting forming a
path from Vdd to gnd and it reduces the noise margin and in order to maintain
we need to restore the logic.

Truth table of NMOS pass transistor with property

For PMOS Pass transistor Vx=min ( IVtpI, Va)

Pass transistor for PMOS

As per the above, Pass transistor for PMOS is also similar to NMOS, If the gate
voltage is high the PMOS is ON and when we want to pass 0 input voltage to the
output then the output will be I VtpI and if this voltage drops below Vtp then the
transistor cuts off. , Hence PMOS transistors only pull down to within a
threshold voltage above gnd.

Advantages of Pass transistors

1.Pass transistor is used to reduce the no. of transistors.
Pass transistor comes under switch based design where the MOSFET is used as
a switch. Which means with the help of one or 2 transistors we can make AND
gate, NAND gate, etc.
It is used to make Transmission gate.
4.Static power dissipation is unaffected
5.Potentially very efficient layouts results.
Very efficient in use of transistors.
If a gate based design contains 100s of transistors then by using Pass transistors
it can be reduced to 40 to 50.

Keypoints:
NMOS is an efficient transfer of 0 which means it can pass strong 0 efficiently
PMOS is an efficient transfer of 1 which means it can pass strong 1 efficiently.
Please refer to problems and solutions by Chandan kumar ( EDA and VLSI
Design)
NMOS INVERTER

NMOS Inverter is also called as NMOS for the above case ( If you want to use
this as an Inverter then it is possible with the above circuit)
NMOS Inverter with Resistive load in three different region.
When v1<Vtn, the transistor is in cut off and id=0, there is no voltage drop across
Rd and the output voltage is Vo=Vdd =Vds ( If you take KCL then Vo-Vdd/Rd=0
so Vdd=Vo or the voltage across drain and source of the NMOS )

When V1 >Vtn, the transistor is ON and it goes into linear mode and the
condition is Vds<Vgs-Vtn ( Refer to the conditions of Linear, Saturation and cut
off )

NMOS Inverter with resistive load in Cut off region

Transition Region

As the input voltage is further increases and voltage drop across the Rd become
sufficient to reduce the Vds such that Vds<Vgs-Vtn

Vo=Vdd-KnRd(V1-Vtn) ------------------Eqn 1
Vo=V1-Vtn ( At pinch off point or Transition point, where V1 is same as Vgs
and Vo=Vds )---Eqn 2
Equating 1 and 2 equations
V1-Vtn=Vdd-KnRd(V1-Vtn)

Taking RHS to LHS

2

V1+KnRd(V1-Vtn) -Vdd-Vtn or
2

KnRd (V1-Vtn) +(V1-Vtn)-Vdd

This is the equation for Transition region

The above diagram shows the curve for Cut off , Linear , Saturation and
Transition ( It is same as pinch off point (Vds=Vgs-Vtn) do not get confuse

NMOS Inverter in Saturation region

As the input is increased slightly above the Vtn, the transistor turns on and is in
the saturation region.
Kn is same as /2 and =CoxW/L
As we know the equation for current in saturation as
2

Id=/2(Vgs-Vt) which can be written as Id=Kn(Vgs-Vtn) =Kn (V1-Vtn)

Using KVL for the NMOS Inverter circuit we get the equation as Vo=Vdd-IdRd
Substituting the value of Id in the above equation

As the input voltage becomes greater than Vt, The Q point continues to move up
the loadline , the transistor becomes biased in the Non saturated region or
Linear region or Active region or Unsaturated region.
What is the equation of current in Linear
2

Ids={(Vgs-Vt) Vds-Vds /2)}

So it can be written as

Equation for Non saturation region is

NMOS Inverter with Enhancement Load

The condition for Enhancement load is Vgd=0 and Vgs=Vds because the gate
terminal is connected to Drain voltage
Vgs=Vg-Vs where Vg is same as Vd so Vgs=Vds
The conditions are Vgs=Vds<=Vtn and the drain current is zero( condition for Cut
off)

Vgs=Vds>Vtn , a nonzero drain current is induced in the device. ( This

condition is for saturation)

Explaination for the above:

For the above , The load is saturated so the current equation in saturation is
given as above
Vdsl=Vdd-Vo ( KVL)
Subtracting Vtn on both the sides Vdsl-Vtnl=Vdd-Vo-Vtnl----Eqn (3) We know
that Idl=0 Idl=KL(Vdsl-Vtnl)=0
Here l represents load and d represents driver
Now from Eqn (3)
Vdd-Vo-Vtnl=0

NMOS Inverter with Enhancement load biased in Non saturation region or

Linear region or Active region or Unsaturated region ( Below)

NMOS Inverter with Enhancement load where driver and Load transistor biased
in Saturation region ( Below)

NMOS Inverter with Enhancement load biased in Transition region(Below)

The loadlines for three basic types of Inverters are shown in the below
fig,superimposed on the drain characteristics of the driver transistor. The resistive
loadline exhibits linear characteristics, and its high output voltage is dependent
on drain resistance Rd.
An inverter with an enhancement load has a lower drain current for the same
value of Vds
An inverter with Depletion load shows a constant current over a wide range of

Vds, As a consequence of this characteristic, It will switch a capacitive load

more rapidly than the other two inverters. Also it exhibits a higher noise margin.
Depletion load inverters are used in ICs for high speed switching.
Determination of Pull up to Pull Down ratio ( Zpu/Zpd)for an NMOS
Inverter driven by another NMOS Inverter
Below figure shows that an Inverter driven from the output of another similar
inverter. Consider depletion mode transistor for which Vgs=0 under all conditions
and further assume that in order to cascade inverters without degradation of levels.

Vin=Vout=Vinv

For equal margins around the inverter threshold we set Vinv=0.5Vdd or Vdd/2 ,
At this point both the transistors are in saturation ( Recall CMOS Inverter where
at one point both the transistors will be on )
2
IDS= /2 (Vgs-Vt)
In depletion mode Vgs=0 so the above Equation becomes
2

IDS= WPU/LPU (0-Vt) since Vgs=0

and in Enhancement mode
2

IDS= WPD/LPD (VINV-Vtd) since Vgs=Vinv

Equating both the currents we get
2

WPD/LPD (VINV-Vtd) = WPU/LPU (0-Vt)

Where Wpd, Lpd, Wpu, Lpu are the widths , lengths of the pull down and pull
up transistors respectively, and Vt is for the Pull up transistor , Vtd is for pull
down transistor.

Zpd=Lpd/Wpd
Zpu=Lpu/Wpu

We have 1/Zpd (Vinv-Vt) =1/Zpu (-Vtd)

Solving the above equation for Vinv we get

Vinv=Vt-Vtd/Sqrt ( Zpu/Zpd)
Assuming typical values as Vt=0.2Vdd, Vtd=-0.6Vdd, Vinv=Vdd/2 for equal
margins
We get the values as
From the last equation
0.5=0.2+ 0.6/Sqrt ( Zpu/Zpd)
Sqrt ( Zpu/Zpd)=2
Zpu/Zpd=4/1 for an inverter directly driven by an inverter.
Determination of Pull up to Pull down ratio for an NMOS Inverter driven
through one or more pass transistor.
Previously we have seen that the Inverter being driven by another Inverter but
in this case we are driving an inverter with a pass transistor and then the
Inverter.
Assume that a low signal is been passed from an Inverter so that the output is
high and if this high signal is passed through a series of NMOS Pass transistor
then the output will be degraded and the output voltage will be Vdd-Vth.

Vtp =Threshold voltage for a pass transistor

We must now ensure that for this input voltage we get the same voltage which
we get for the Inverter 1 driven with input =Vdd.
Consider Inverter shown in the above diagram with Input =vdd, if the input is
Vdd, then pull down transistor T2 is conducting but with a drop across it.
Therefore it is in resistive or linear region represented by R1 shown ,
Meanwhile the Pull up transistor T1 is in saturation region and it is represented
with a current source as discussed earlier.
For the pull down transistor
2

Ids=K Wpd1/Lpd1 { (Vdd-Vt)Vds1-VVds1 /2}

Therefore R1=Vds1/Ids and if we substitute the value we get as
R1= 1/K (Lpd1/Wpd1) { 1/(Vdd-Vt-Vds1/2)
If Vds1 is small and Vds1 can be ignored so
R1=1/K ( Zpd1) {1/Vdd-Vt}
Now for Depletion mode Pull up in saturation with Vgs=0
2

I1= Ids=K Wpu1/Lpu1(-Vtd) /2

Now the voltage drop across R1 is
I1R1=Vout1
Therefore
2

Vout1=I1R1=Zpd1/Zpu1 {1/(vdd-Vt)}Vtd /2
Consider Inverter 2 when Input =Vdd-Vtp and as for inverter 1 R2= 1/K( Zpd2)
{1/(Vdd-Vtp)-Vt}
2

I2=K (1/Zpu2)(-Vtd) /2
2

When Vout2=I2R2=Zpd2/Zpu2 { 1/Vdd-Vtp-Vt} ( -Vtd) /2

If inverter 2 is to have the same output voltage then Vout1 should be equal to
Vout 2
Which is same as I1R1=I2R2
When we equate both the equations we get as Zpu2/Zpd2=Zpu1/Zpd1 ( VddVt)/(Vdd-Vtp-Vt)
If we take some typical values such as Vt=0.2Vdd , Vtp=-0.3Vdd then
Zpu2/Zpd2=Zpu1/Zpd1 ( Vdd-0.2Vdd)/(Vdd-0.3Vdd+0.2Vdd)
Zpu2/Zpd2=Zpu1(0.8/0.1)
Therefore the ratio is 8:1

Summary:
An Inverter driven directly from the output of another should have a ratio as

Zpu/Zpd ratio of 4/1

An Inverter driven through one or more pass transistor should have a
Zpu/Zpd ratio of 8/1