C2000 MCU 1-Day Workshop

Workshop Guide and Lab Manual

F28xMCUodw
Revision 4.2
January 2014

Technical Training
Organization

Workshop Topics

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Copyright 2009 2014 Texas Instruments Incorporated

Revision History
April 2009 Revision 1.0
October 2009 Revision 1.1
June 2010 Revision 2.0
December 2010 Revision 2.1
October 2011 Revision 3.0
February 2012 Revision 4.0
January 2013 Revision 4.1
January 2014 Revision 4.2

Mailing Address
Texas Instruments
Training Technical Organization
6500 Chase Oaks Blvd Building 2
M/S 8437
Plano, Texas 75023

C2000 MCU 1-Day Workshop

Workshop Topics

Workshop Topics
Workshop Topics......................................................................................................................................... 3
Workshop Introduction ............................................................................................................................... 4
Architecture Overview .............................................................................................................................. 11
Programming Development Environment................................................................................................. 16
Code Composer Studio ......................................................................................................................... 16
Linking Sections in Memory ................................................................................................................ 20
Lab 1: Linker Command File .................................................................................................................... 24
Peripheral Register Header Files ............................................................................................................. 29
Reset, Interrupts and System Initialization ............................................................................................... 39
Reset ..................................................................................................................................................... 39
Interrupts............................................................................................................................................... 44
Peripheral Interrupt Expansion (PIE) ................................................................................................... 47
Oscillator / PLL Clock Module ............................................................................................................ 52
Watchdog Timer Module ...................................................................................................................... 54
GPIO ..................................................................................................................................................... 56
Lab 2: System Initialization ...................................................................................................................... 60
Control Peripherals .................................................................................................................................. 65
ADC Module ........................................................................................................................................ 65
Pulse Width Modulation ....................................................................................................................... 69
ePWM ................................................................................................................................................... 71
eCAP .................................................................................................................................................... 87
eQEP ..................................................................................................................................................... 89
Lab 3: Control Peripherals ....................................................................................................................... 92
Flash Programming .................................................................................................................................. 98
Flash Programming Basics ................................................................................................................... 98
Programming Utilities and CCS Flash Programmer ........................................................................... 100
Code Security Module and Password ................................................................................................. 101
Lab 4: Programming the Flash ............................................................................................................... 104
The Next Step ....................................................................................................................................... 111
Training .............................................................................................................................................. 111
controlSUITE ..................................................................................................................................... 112
Development Tools............................................................................................................................. 113
C2000 Workshop Download Wiki ..................................................................................................... 116
Development Support ......................................................................................................................... 117
Notes: ...................................................................................................................................................... 118

C2000 MCU 1-Day Workshop

Workshop Introduction

Workshop Introduction
C2000 Microcontroller 1-Day Workshop

Texas Instruments
Technical Training
C2000 is trademarks of Texas Instruments. Copyright 2014 Texas Instruments. All rights reserved.

The objective of this workshop is to gain a fully understand and a complete working knowledge
of the C2000 microcontroller. This will be accomplished through detailed presentations and
hands-on lab exercises.
The workshop will start with the basic topics and progress to more advanced topics in a logical
flow such that each topic and lab exercise builds on the previous one presented. At the end of the
workshop, you should be confident in applying the skills learned in your product design.

C2000 MCU 1-Day Workshop

Workshop Introduction

C2000 MCU 1-Day Workshop Outline

Workshop

Introduction
Architecture Overview
Programming Development Environment

Lab: Linker command file

Peripheral

Register Header Files

Reset, Interrupts and System Initialization

Lab: Watchdog and interrupts

Control

Flash

Peripherals

Lab: Generate and graph a PWM waveform

Programming

Lab: Run the code from flash memory

The

Next Step

The outline for this workshop starts with an introduction covering the materials required and
provides a brief overview of the C2000 product family. Next, we will look at the architectural
details and discuss the block diagram, memory map, and peripherals. From there, we will move
to the programming development environment and gain the basic skills needed to use Code
Composer Studio, as well as learn about a linker command file.
Then we will have a lab exercise to practice the skills learned thus far. We will follow this with
the peripheral register header files. At this point, we have covered the basic foundation. Next,
we will explore the device and learn about reset, interrupts, and system initialization. In this lab
exercise, we will use the watchdog to generate a reset and interrupt, reinforcing what we have just
learned.
Then we will cover the control peripherals, which includes the ADC, ePWM, eCAP, and eQEP.
In this lab exercise, we will generate a PWM waveform, then feed it into the ADC, and graph it
using Code Composer Studio. Additionally, we will learn about the real-time mode emulation
features.
The next topic will be programming the flash. In this lab exercise, we will develop a complete
embedded system using the code from the previous lab exercises. Finally, in the Next Step, we
will discuss where you can find more information, allowing you to continue learning and
exploring on your own.

C2000 MCU 1-Day Workshop

Workshop Introduction

Required Workshop Materials

http://processors.wiki.ti.com/index.php/

C2000_Piccolo_OneDay_Workshop_Home_Page
F28069
Install
Run

controlSTICK kit

Code Composer Studio v5.5.0

the workshop installer

C2000 Microcontroller 1-Day Workshop-4.2-Setup.exe

Lab

Files / Solution Files

Student

Guide and Documentation

The materials required for this workshop are available using the links shown at the top of this
slide. Please be sure that you have the F28069 controlSTICK kit. The included jumper wire will
be needed for the lab exercises. Make sure that you have all of the software installed. The lab
directions are written based on the version of Code Composer Studio as shown on this slide. The
workshop installer will automatically install the lab files, solution files, workshop manual, and
documentation.

C2000 MCU 1-Day Workshop

Workshop Introduction

TI Embedded Processing Portfolio

TI Embedded Processors
Microcontrollers (MCUs)
16-bit ultralow power
MCUs

32-bit
real-time
MCUs

MSP430

C2000
Delfino
Piccolo

Up to
25 MHz
Flash
1 KB to 256 KB
Analog I/O, ADC
LCD, USB, RF
Measurement,
Sensing, General
Purpose

ARM-Based Processors
32-bit ARM
Cortex-M3
MCUs

Stellaris
ARM Cortex-M3

ARM
Cortex-A8
MPUs

Sitara
ARM Cortex-A8
& ARM9

Digital Signal Processors (DSPs)

DSP
DSP+ARM

C6000
DaVinci

Multi-core
DSP

Ultra
Low power
DSP

C6000

C5000

video processors

OMAP

300MHz to
Up to
300MHz to >1Ghz
>1GHz
100 MHz
+Accelerator
Cache
Flash
Flash, RAM
Cache,
RAM, ROM
8 KB to 256 KB
16 KB to 512 KB
RAM, ROM
USB, ENET
USB, ENET,
USB, CAN,
PWM, ADC,
MAC+PHY CAN,
PCIe, SATA, SPI
PCIe, EMAC
CAN, SPI, I2C
ADC, PWM, SPI
Motor Control,
Connectivity, Security, Industrial computing, Floating/Fixed Point
Video, Audio, Voice,
POS & portable
Digital Power,
Motion Control, HMI,
Lighting, Ren. Enrgy Industrial Automation
Security, Confer.
data terminals
40MHz to
300 MHz

24.000
MMACS
Cache
RAM, ROM
SRIO, EMAC
DMA, PCIe
Telecom T&M,
media gateways,
base stations

Up to 300 MHz
+Accelerator
Up to 320KB RAM
Up to 128KB ROM
USB, ADC
McBSP, SPI, I2C
Audio, Voice
Medical, Biometrics

Software & Development Tools

The Texas Instruments embedded processing portfolio covers a wide range of embedded
processors from microcontrollers, to ARM-based processors, to digital signal processors. Our
microcontrollers include the 16-bit ultra-low power MSP430 microcontroller family and, the 32bit real-time C2000 microcontroller family. Our ARM-based processors include the 32-bit ARM
Cortex M3 Stellaris microcontroller family, the ARM Cortex A8 Sitara microprocessor family,
and it also includes the OMAP devices, which incorporates a C6000 and ARM processor. Our
digital signal processors include the C6000 DaVinci, as well as multicore DSPs with up to 24
billion multiply accumulates per second. Additionally, there's an ultra-low power C5000 digital
signal processor family.

C2000 MCU 1-Day Workshop

Workshop Introduction

C2000 32-Bit Microcontrollers

C28x Piccolo MCUs
F2806x

C28x Delfino MCUs

C28x + Cortex-M3 MCUs

C2834x

F2803x
F2802x

Performance:

40-80MHz 28x CPU

Floating Point Unit (optional)
CLA Co-Processor (optional)
VCU Accelerator (optional)

Memory:

16KB-128KB Flash
6KB-100KB SRAM

Performance:

100-300MHz 28x CPU

Floating Point Unit

Memory:

Up to 512KB Flash
Up to 516KB SRAM

Key Peripherals:
Package:

176 QFP, 176 BGA, 179 u*BGA,

256 BGA

38 TSSOP, 48 QFP, 56 QFN, 64

QFP, 80 QFP, 100 QFP

Performance:

Dual Core
Up to 150MHz 28x CPU
Up to 100MHz ARM Cortex M3 CPU
Floating Point Unit
VCU Accelerator

Memory:

Key Peripherals:

ADC, PWM, QEP, DMA, SPI,

UART, I2C, CAN, EMIF

ADC, PWM, QEP, DMA, SPI,

UART, I2C, CAN, USB

F28M35x

F2833x

Package:

256KB-1MB Flash
Up to 132KB SRAM

Key Peripherals:

ADC, PWM, QEP, DMA, EMIF, SPI,

UART, I2C, CAN, USB, EMAC

Package:
144 QFP

150+ Devices, Software Compatibility

The C2000 family, which this workshop is based on, includes the C28x Piccolo, C28x Delfino,
and C28x + Cortex-M3 product lines. The Piccolo product line ranges in performance from 40
MHz to 90 MHz and has options for a floating point unit, control law accelerator coprocessor, a
Viterbi complex math CRC unit, and USB. The Delfino product line ranges in performance from
100 MHz to 300 MHz and features a floating point unit and some devices with an external
memory interface. The C28x + Cortex-M3 product line consists of a dual-system architecture,
incorporating a C28X CPU with performance up to 150 MHz and an ARM Cortex M3 CPU with
performance up to 100 MHz. In addition to floating point capabilities, it has a Viterbi complex
math CRC unit. The three product lines provide you with over 150 devices to choose from and
maintain software compatibility.

C2000 MCU 1-Day Workshop

Workshop Introduction

Broad C2000 Control Application Base

Motor Control

Renewable Energy

E-bike
Power Tools

Wind Power Inverters

White Goods

Solar Power Inverters

Industrial Drives
& Motion Control

Lighting

Digital Power

C2000

DC/DC
Converters

LED Street Lighting

Uninterruptable
Power Supplies

LED TV
Backlighting

Auto HID

Telecom / Server
AC/DC Rectifiers

Radar / Collision
Avoidance
Smart Metering

Hybrid Electric Vehicles

Power Line
Communication

Electric Power Steering

RF
Communication

Smart Grid & PLC

Automotive
3/14/2014

The C2000 product family has a very broad application base with target markets in motor control,
lighting, smart grid and power line communications, automotive, digital power, and renewable
energy.

C2000 Delfino / Piccolo Comparison

Clock
Flash / RAM

F2833x

F2803x

150 MHz

60 MHz

F2806x
90 MHz

128Kw / 34Kw

64Kw / 10Kw

128Kw / 50Kw

On-chip Oscillators

VREG / POR / BOR

SEQ - based

SOC - based

SOC - based

Analog COMP w/ DAC

FPU

6-Channel DMA

CLA

VCU

ePWM / HR ePWM

eCAP / HR eCAP

Watchdog Timer
12-bit ADC

/-

/-

eQEP

SCI / SPI / I2C

LIN

McBSP

USB

External Interface

When comparing the Delfino and Piccolo product lines, you will notice that the Piccolo F2806x

C2000 MCU 1-Day Workshop

Workshop Introduction

devices share many features with the Delfino product line. The Delfino product line is shown in
the table by the F2833x column; therefore, the F28069, being the most feature-rich Piccolo
device, was chosen as the platform for this workshop. The knowledge learned from this device
will be applicable to all C2000 product lines.

TMS320F28069 controlSTICK
On-board USB
JTAG Emulation

USB JTAG
Interface & Power

LED LD2
(GPIO34)

LED LD1
(Power)

TMS320F28069

Peripheral
Header Pins

The development tool for this workshop will be the TMS320F28069 controlSTICK kit. This
controlSTICK is a self-contained system that plugs into a free USB port on your computer. The
USB port provides power, as well as communicates to the onboard JTAG emulation controller.
LED LD1 illuminates when the board is powered, and LED LD2 is connected to GPIO34. We
will be using this LED as a visual indicator during the lab exercises. Some of the I/O lines from
the F28069 device are pinned out to the peripheral header. We will be using the included jumper
wire to connect various I/O lines on this header.

10

C2000 MCU 1-Day Workshop

Architecture Overview

Architecture Overview
TMS320F2806x Block Diagram
Program Bus
ePWM
Boot

DMA

Sectored

ROM

RAM

eCAP

6 Ch.

Flash

eQEP
DMA Bus

12-bit ADC

CLA Bus

McBSP

32x32 bit
Multiplier

R-M-W

FPU

Atomic
ALU

CLA

PIE
Interrupt
Manager

VCU

Register Bus

Watchdog

I2C
SCI

SPI

32-bit

CAN 2.0B

Timers
USB 2.0

CPU
Data Bus

GPIO

This block diagram represents an overview of all device features and is not specific to any one
device. The F28069 device is designed around a multibus architecture, also known as a modified
Harvard architecture. This can be seen in the block diagram by the separate program bus and data
bus, along with the link between the two buses. This type of architecture greatly enhances the
performance of the device.
In the upper left area of the block diagram, you will find the memory section, which consists of
the boot ROM, sectored flash, and RAM. Also, you will notice that the six-channel DMA has its
own set of buses.
In the lower left area of the block diagram, you will find the execution section, which consists of
a 32-bit by 32-bit hardware multiplier, a read-modify-write atomic ALU, a floating-point unit,
and a Viterbi complex math CRC unit. The control law accelerator coprocessor is an independent
and separate unit that has its own set of buses.
The peripherals are grouped on the right side of the block diagram. The upper set is the control
peripherals, which consists of the ePWM, eCAP, eQEP, and ADC. The lower set is the
communication peripherals and consists of the multichannel buffered serial port, I2C, SCI, SPI,
CAN, and USB.
The PIE block, or Peripheral Interrupt Expansion block, manages the interrupts from the
peripherals. In the bottom right corner is the general-purpose I/O. Also, the CPU has a watchdog
module and three 32-bit general-purpose timers available.

C2000 MCU 1-Day Workshop

11

Architecture Overview

TMS320F28069 Memory Map

0x000000
0x000400
0x000800
0x000D00
0x000E00

Data

Program

M0 SARAM (1Kw)
M1 SARAM (1Kw)
PIE Vectors
(256 w)

PF 0 (6Kw)

reserved

0x002000
0x005000
PF 3 (4Kw)
0x006000
PF 1 (4Kw)
0x007000
PF 2 (4Kw)
0x008000
L0 DPSARAM (2Kw)
0x008800
L1 DPSARAM (1Kw)
0x008C00
L2 DPSARAM (1Kw)
0x009000
L3 DPSARAM (4Kw)
0x00A000
L4 SARAM (8Kw)
0x00C000
L5 DPSARAM (8Kw)
0x00E000
L6 DPSARAM (8Kw)
0x010000
L7 DPSARAM (8Kw)
0x012000
L8 DPSARAM (8Kw)
0x014000

0x014000
0x3D7800
0x3D7C00
0x3D7C80
0x3D7CC0
0x3D8000

reserved
User OTP (1Kw)
reserved
ADC / OSC cal. data
reserved
FLASH (128Kw)

0x3F7FF8
0x3F8000

PASSWORDS (8w)

Boot ROM (32Kw)

0x3FFFC0
0x3FFFFF

BROM Vectors (64w)

Data

Program

DPSARAM L0, L1, L2 & L3

accessible by CPU & CLA
DPSARAM L5, L6, L7 & L8
accessible by DMA

CSM Protected:
L0, L1, L2, L3, L4,
OTP, FLASH,
ADC CAL,
Flash Regs in PF0

The F28069 utilizes a contiguous memory map, also known as a von-Neumann architecture. This
type of memory map lends itself well to higher-level languages. This can be seen by the labels
located at the top of the memory map where the memory blocks extend between both the data
space and program space.
At the top of the map, we have two blocks of RAM called M0 and M1. Then we see PF0 through
PF3, which are the peripheral frames. This is the area where you will find the peripheral
registers. Also in this space, you will find the PIE block. Memory blocks L0 through L8 are
grouped together. L0 through L3 are accessible by the CPU and CLA. L5 through L8 are
accessible by the DMA.
The user OTP is a one-time, programmable, memory block. TI reserves a small space in the map
for the ADC and oscillator calibration data. The flash block contains a section for passwords,
which are used by the code security module. The boot ROM and boot ROM vectors are located
at the bottom of the memory map.

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C2000 MCU 1-Day Workshop

Architecture Overview

96 dedicated PIE
vectors
No software decision
making required
Direct access to RAM
vectors
Auto flags update
Concurrent auto
context save

Peripheral Interrupts 12x8 = 96

Fast Interrupt Response Manager

PIE module
For 96
interrupts

28x CPU Interrupt logic

INT1 to
INT12

96

PIE

12 interrupts

IFR

IER

INTM

28x
CPU

Register
Map

Auto Context Save

T
ST0
AH
AL
PH
PL
AR1 (L)
AR0 (L)
DP
ST1
DBSTAT IER
PC(msw) PC(lsw)

The C2000 devices feature a very fast interrupt response manager using the PIE block. This
allows up to 96 possible interrupt vectors to be processed by the CPU. We will cover more
details about this in the reset, interrupts, and system initialization module.

Direct Memory Access (DMA)

PIE

ADC

DINTCH1-6

Result 0-15

L5 DPSARAM

McBSP-A

DMA

SysCtrlRegs.EPWMCNF.bit.CONCNF

6-channels

(maps ePWM to DMA bus or CLA bus)

Triggers

L6 DPSARAM
L7 DPSARAM
L8 DPSARAM

ADCINT1 / ADCINT2
MXEVTA / MREVTA
XINT1-3 / TINT0-2
ePWM1-6 (SOCA-B)
USB0EP1-3RX/TX
software

PWM1
PWM2
PWM3
PWM4
PWM5
PWM6

Transfers data between peripherals and/or

memory without intervention from the CPU
The DMA allows data to be transferred between peripherals and/or memory without intervention

C2000 MCU 1-Day Workshop

13

Architecture Overview

from the CPU. The DMA can read data from the ADC result registers, transfer to or from
memory blocks L5 through L8, transfer to or from the McBSP, and also modify registers in the
ePWM. Triggers are used to initiate the transfers, and when completed the DMA can generate an
interrupt.

Control Law Accelerator (CLA)

ADC

C28x CPU

&
CMP

PWM
CLA

An

independent 32-bit floating-point math

accelerator
Executes algorithms independently and in
parallel with the main CPU
Direct access to ePWM / HRPWM, eCAP, eQEP,
ADC result and comparator registers
Responds to peripheral interrupts
independent of the CPU
Frees up the CPU for other tasks
(communications and diagnostics)
The control law accelerator is an independent, 32-bit, floating-point, math accelerator. It
executes algorithms independently and in parallel with the CPU. It has direct access to the
ePWM, high-resolution PWM, eCAP, eQEP, ADC result and comparator registers. It responds to
peripheral interrupts independently of the CPU and frees up the CPU for other tasks, such as
communications and diagnostics.

14

C2000 MCU 1-Day Workshop

Architecture Overview

Viterbi, Complex Math, CRC Unit (VCU)

Extends C2000 instruction set to support:
Viterbi

operations

Decode

Complex
16-bit

for communications

math

fixed-point complex FFT (5 cycle butterfly)

used in spread spectrum communications, and many signal processing

algorithms

Complex

filters

used to improve data reliability, transmission distance, and power

efficiency

Power

Line Communications (PLC) and radar

applications

Cyclic

Redundancy Check (CRC)

Communications

and memory robustness checks

The Viterbi complex math CRC unit extends the C2000 instruction set to support Viterbi
operations used in communications; complex math, which includes complex FFTs and complex
filters, and is used in power line communications and radar applications; and cyclical redundancy
check, which is used in communications and memory robustness checks. Below lists a summary
of the major architectural features covered in this module.

Architecture Summary
High performance 32-bit CPU
32x32 bit or dual 16x16 bit MAC
IEEE single-precision floating point unit (FPU)
Hardware Control Law Accelerator (CLA)
Viterbi, complex math, CRC unit (VCU)
Atomic read-modify-write instructions
Fast interrupt response manager
128Kw on-chip flash memory
Code security module (CSM)
Control peripherals
12-bit ADC module
Comparators
Direct memory access (DMA)
Up to 54 shared GPIO pins
Communications peripherals

C2000 MCU 1-Day Workshop

15

Programming Development Environment

Programming Development Environment

Code Composer Studio

Code Composer Studio: IDE

Integrates: edit, code generation,

and debug

Single-click access using buttons

Powerful graphing/profiling tools

Automated tasks using Scripts

Built-in access to BIOS functions

Based on the Eclipse open source

software framework

Code Composer Studio is an integrated development environment that integrates the edit, code
generation, and debug process. It is simple to use, with single-click access to various functions,
and provides powerful debugging tools. Scripts automate tasks and BIOS is built-in. Code
Composer Studio is based on the Eclipse open source software framework.

16

C2000 MCU 1-Day Workshop

Programming Development Environment

Edit and Debug Perspective (CCSv5)

Each perspective provides a set of functionality aimed
at accomplishing a specific task

Edit Perspective

Displays views used

during code development

C/C++ project, editor, etc.

Debug Perspective

Displays views used for

debugging

Menus and toolbars

associated with debugging,
watch and memory
windows, graphs, etc.

Code Composer Studio has Edit and Debug perspectives. Each perspective provides a set of
functionality aimed at accomplishing a specific task. In the edit perspective, views used during
code development are displayed. In the debug perspective, views used during debug are
displayed.

C2000 MCU 1-Day Workshop

17

Programming Development Environment

CCSv5 Project
Project files contain:

List of files:

Source (C, assembly)

Libraries

DSP/BIOS configuration file

Linker command files

Project settings:

Build options (compiler,

assembler, linker, and TI-RTOS)

Build configurations

A project contains files, such as C and assembly source files, libraries, BIOS configuration files,
and linker command files. It also contains project settings, such as build options, which include
the compiler, assembler, linker, and BIOS, as well as build configurations.

Creating a New CCSv5 Project

1. Project Name, Location, and Device

File New CCS Project

2. Advanced Settings

3. Project Templates and Examples

To create a project in Code Composer Studio, you would click on File New CCS Project.

18

C2000 MCU 1-Day Workshop

Programming Development Environment

First, you would fill in the project name, the location, and the device. Then you would complete
the advanced settings and, finally, the project template. You will have a chance to try this in our
first lab exercise.

CCSv5 Build Options Compiler / Linker

Compiler

20 categories for code

generation tools
Controls many aspects of
the build process, such as:
Optimization level
Target device
Compiler / assembly / link
options

Linker

8 categories for linking

Specify various link

options

${PROJECT_ROOT}
specifies the current
project directory

After a project is created, the build options are configured. In our lab exercise, we will look at the
options for the compiler and linker.

C2000 MCU 1-Day Workshop

19

Programming Development Environment

Linking Sections in Memory

Sections
Global vars (.ebss)

Init values (.cinit)

int

x = 2;

int

y = 7;

void main(void)
{
long z;

All code consists of

different parts called
sections
All default section
names begin with .
The compiler has
default section names
for initialized and
uninitialized sections

z = x + y;
}
Local vars (.stack)

Code (.text)

All code consists of different parts called sections. All default section names begin with a dot and
are typically lower case. The compiler has default section names for initialized and uninitialized
sections. For example, x and y are global variables, and they are placed in the section .ebss.
Whereas 2 and 7 are initialized values, and they are placed in the section called .cinit. The local
variables are in a section .stack, and the code is placed in a section called .txt.

20

C2000 MCU 1-Day Workshop

Programming Development Environment

Compiler Section Names

Initialized Sections
Name
Description

Link Location

.text

code

FLASH

.cinit

initialization values for

FLASH

global and static variables

.econst

constants (e.g. const int k = 3;)

FLASH

.switch

tables for switch statements

FLASH

.pinit

tables for global constructors (C++)

FLASH

Uninitialized Sections
Name
Description

Link Location

.ebss

global and static variables

RAM

.stack

stack space

low 64Kw RAM

.esysmem memory for far malloc functions

RAM

Note: During development initialized sections could be linked to RAM since

the emulator can be used to load the RAM

This is a small list of compiler default section names. The top group is initialized sections, and
they are linked to flash. In our previous code example, we saw .txt was used for code, and .cinit
for initialized values. The bottom group is uninitialized sections, and they are linked to RAM.
Once again, in our previous example, we saw .ebss used for global variables and .stack for local
variables.

C2000 MCU 1-Day Workshop

21

Programming Development Environment

Placing Sections in Memory

Memory
0x00 0000

M0SARAM
(0x400)

0x00 0400

M1SARAM
(0x400)

Sections
.ebss
.stack

0x3E 8000

.cinit

FLASH
(0x10000)

.text

Next, we need to place the sections that were created by the compiler into the appropriate
memory spaces. The uninitialized sections, .ebss and .stack, need to be placed into RAM; while
the initialized sections, .cinit, and .txt, need to be placed into flash.

Linking

Memory description

How to place s/w into h/w

Link.cmd
.obj

Linker

.out

.map

The linker command file describes the physical hardware memory and specifies where the

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Programming Development Environment

sections are placed in the memory. The file created during the link process is a .out file. This is
the file that will be loaded into the microcontroller. As an option, we can generate a map file.
This map file will provide a summary of the link process, such as the absolute address and size of
each section.

Linker Command File

MEMORY
{
PAGE 0:
FLASH:

/* Program Memory */
origin = 0x3E8000, length = 0x10000

PAGE 1:
/* Data Memory */
M0SARAM: origin = 0x000000, length = 0x400
M1SARAM: origin = 0x000400, length = 0x400
}
SECTIONS
{
.text:>
.ebss:>
.cinit:>
.stack:>
}

FLASH
M0SARAM
FLASH
M1SARAM

PAGE
PAGE
PAGE
PAGE

=
=
=
=

0
1
0
1

A linker command file consists of two sections, a memory section and a sections section. In the
memory section, page 0 defines the program memory space, and page 1 defines the data memory
space. Each memory block is given a unique name, along with its origin and length. In the
sections section, the section is directed to the appropriate memory block. In the lab exercise, you
will have an opportunity to work with a linker command file.
Next, in the lab exercise, you will be working with a linker command file and will learn the basic
skills for using Code Composer Studio. You will set up a target configuration, create a project,
build a project, and step through the code.

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Lab 1: Linker Command File

Lab 1: Linker Command File

Objective
Use a linker command file to link the C program file (Lab1.c) into the system described below.

Lab 1: Linker Command File

Memory
on-chip
memory

F28069
System Description:
TMS320F28069

0x00 0000

M0SARAM
(0x400)

0x00 A000

0x00 0400

M1SARAM
(0x400)

0x00 C000 L5DPSARAM

(0x2000)
0x00 E000 L6DPSARAM
(0x2000)
0x01 0000 L7DPSARAM
(0x2000)
0x01 2000 L8DPSARAM
(0x2000)

0x00 8000 L0DPSARAM

(0x800)
0x00 8800 L1DPSARAM
(0x400)
0x00 8C00 L2DPSARAM
(0x400)
0x00 9000 L3DPSARAM
(0x1000)

L4SARAM
(0x2000)

All internal RAM

blocks allocated

Placement of Sections:
.text into RAM Block L4SARAM on PAGE 0 (program memory)
.cinit into RAM Block L4SARAM on PAGE 0 (program memory)
.ebss into RAM Block M0SARAM on PAGE 1 (data memory)
.stack into RAM Block M1SARAM on PAGE 1 (data memory)

Initial Hardware Set Up

Plug the F28069 controlSTICK into the computer USB port. This will power the controlSTICK
using the power supplied by the computer USB port. Additionally, this USB port will provide the
JTAG communication link between the device and Code Composer Studio.

Initial Software Set Up

Code Composer Studio must be installed in addition to the workshop files. A local copy of the
required controlSUITE files is included with the lab files. This provides portability, making the
workshop files self-contained and independent of other support files or resources. The lab
directions for this workshop are based on all software installed in their default locations.

Procedure

Start Code Composer Studio and Open a Workspace

1. Start Code Composer Studio (CCS) by double clicking the icon on the desktop or
selecting it from the Windows Start menu. When CCS loads, a dialog box will prompt
you for the location of a workspace folder. Use the default location for the workspace
and click OK.

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Lab 1: Linker Command File

This folder contains all CCS custom settings, which includes project settings and views
when CCS is closed so that the same projects and settings will be available when CCS is
opened again. The workspace is saved automatically when CCS is closed.
2. The first time CCS opens a Welcome to Code Composer Studio v5 page appears.
Close the page by clicking the X on the TI Resource Explorer tab. You should now
have an empty workbench. The term workbench refers to the desktop development
environment. Maximize CCS to fill your screen.
The workbench will open in the CCS Edit Perspective view. Notice the CCS Edit
icon in the upper right-hand corner. A perspective defines the initial layout views of the
workbench windows, toolbars, and menus which are appropriate for a specific type of
task (i.e. code development or debugging). This minimizes clutter to the user interface.
The CCS Edit Perspective is used to create or build projects. A CCS Debug
Perspective view will automatically be enabled when the debug session is started. This
perspective is used for debugging projects.

Setup Target Configuration

3. Open the emulator target configuration dialog box. On the menu bar click:
File New Target Configuration File
In the file name field type F28069_ctrlSTK.ccxml. This is just a descriptive name
since multiple target configuration files can be created. Leave the Use shared location
box checked and select Finish.
4. In the next window that appears, select the emulator using the Connection pull-down
list and choose Texas Instruments XDS100v1 USB Emulator. In the
Board or Device box type F28069 to filter the options. In the box below, check the
box to select controlSTICK Piccolo F28069. Click Save to save the
configuration, then close the F28069_ctrlSTK.ccxml setup window by clicking the X
on the tab.
5. To view the target configurations, click:
View Target Configurations
and click the plus sign (+) to the left of User Defined. Notice that the
F28069_ctrlSTK.ccxml file is listed and set as the default. If it is not set as the
default, right-click on the .ccxml file and select Set as Default. Close the Target
Configurations window by clicking the X on the tab.

Create a New Project

6. A project contains all the files you will need to develop an executable output file (.out)
which can be run on the MCU hardware. To create a new project click:
File New CCS Project
In the Project name field type Lab1. Uncheck the Use default location box. Click the
Browse button and navigate to:
C:\C28x\Labs\Lab1\Project

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Lab 1: Linker Command File

Click OK.
7. The next section selects the device. Select the Family using the pull-down list and
choose C2000. Set the Variant filter using the pull-down list to 2806x
Piccolo and choose the controlSTICK Piccolo F28069. Leave the
Connection box blank. We have already set up the target configuration.
8. Next, open the Advanced settings section and set the Linker command file to
<none>. We will be using our own linker command file, rather than the one supplied
by CCS. Leave the Runtime Support Library set to <automatic>. This will
automatically select the rts2800_fpu32.lib runtime support library for floating-point
devices.
9. Now open the Project templetes and examples section and select the Empty Project
template. Click Finish.
10. A new project has now been created. Notice the Project Explorer window
contains Lab1. The project is set Active and the output files will be located in the
Debug folder. At this point, the project does not include any source files. The next step
is to add the source files to the project.
11. To add the source files to the project, right-click on Lab1 in the Project Explorer
window and select:
Add Files
or click: Project Add Files
and make sure youre looking in C:\C28x\Labs\Lab1\Files. With the file type
set to view all files (*.*) select Lab1.c and Lab1.cmd then click Open. A File
Operation window will open, choose Copy files and click OK. This will add the
files to the project.
12. In the Project Explorer window, click the plus sign (+) to the left of Lab1 and
notice that the files are listed.

Project Build Options

13. There are numerous build options in the project. Most default option settings are
sufficient for getting started. We will inspect a couple of the default options at this time.
Right-click on Lab1 in the Project Explorer window and select Properties or
click:
Project Properties
14. A Properties window will open and in the section on the left under Build be sure that
the C2000 Compiler and C2000 Linker options are visible. Next, under C2000
Linker select the Basic Options. Notice that .out and .map files are being
specified. The .out file is the executable code that will be loaded into the MCU. The
.map file will contain a linker report showing memory usage and section addresses in
memory. Also notice the stack size is set to 0x300.
15. Under C2000 Compiler select the Processor Options. Notice the Use large
memory model and Unified memory boxes are checked. Next, notice the Specify
CLA support is set to cla0, the Specify floating point support is set to fpu32, and
the Specify VCU support is set to vcu0. Select OK to close the Properties window.

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Lab 1: Linker Command File

Linker Command File Lab1.cmd

16. Open and inspect Lab1.cmd by double clicking on the filename in the Project
Explorer window. Notice that the Memory{} declaration describes the system
memory shown on the Lab1: Linker Command File slide in the objective section of
this lab exercise. Memory blocks L3DPSARAM and L4SARAM have been placed in
program memory on page 0, and the other memory blocks have been placed in data
memory on page 1.
17. In the Sections{} area notice that the sections defined on the slide have been linked
into the appropriate memories. Also, notice that a section called .reset has been allocated.
The .reset section is part of the rts2800_fpu32.lib and is not needed. By putting the
TYPE = DSECT modifier after its allocation the linker will ignore this section and not
allocate it. Close the inspected file.

Build and Load the Project

18. Two buttons on the horizontal toolbar control code generation. Hover your mouse over
each button as you read the following descriptions:

Button
1
2

Name
Build
Debug

Description_____________________________________
Full build and link of all source files
Automatically build, link, load and launch debug-session

19. Click the Build button and watch the tools run in the Console window. Check for
errors in the Problems window (we have deliberately put an error in Lab1.c). When
you get an error, you will see the error message in the Problems window. Expand the
error by clicking on the plus sign (+) to the left of the Errors. Then simply double-click
the error message. The editor will automatically open to the source file containing the
error, with the code line highlighted with a question mark (?).
20. Fix the error by adding a semicolon at the end of the z = x + y statement. For
future knowledge, realize that a single code error can sometimes generate multiple error
messages at build time. This was not the case here.
21. Build the project again. There should be no errors this time.
22. CCS can automatically save modified source files, build the project, open the debug
perspective view, connect and download it to the target, and then run the program to the
beginning of the main function.
Click on the Debug button (green bug) or click Run Debug.
Notice the CCS Debug icon in the upper right-hand corner indicating that we are now in
the CCS Debug Perspective view. The program ran through the C-environment
initialization routine in the rts2800_fpu32.lib and stopped at main() in Lab1.c.

Debug Environment Windows

It is standard debug practice to watch local and global variables while debugging code. There
are various methods for doing this in Code Composer Studio. We will examine two of them
here: memory browser, and expressions.

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Lab 1: Linker Command File

23. Open a Memory Browser to view the global variable z.

Click: View Memory Browser on the menu bar.
Type &z into the address field, select Data memory page, and then select Go. Note
that you must use the ampersand (meaning address of) when using a symbol in a
memory browser address box. Also note that CCS is case sensitive.
Set the properties format to 16-Bit Hex TI Style in the browser. This will give you
more viewable data in the browser. You can change the contents of any address in the
memory browser by double-clicking on its value. This is useful during debug.
24. Notice the Variables window automatically opened and the local variables x and y are
present. The variables window will always contain the local variables for the code
function currently being executed.
(Note that local variables actually live on the stack. You can also view local variables in
a memory browser by setting the address to SP after the code function has been
entered).
25. We can also add global variables to the Expressions window if desired. Let's add the
global variable z.
Click the Expressions tab at the top of the window. In the empty box in the
Expression column (Add new expression), type z and then enter. An ampersand is not
used here. The expressions window knows you are specifying a symbol. (Note that the
expressions window can be manually opened by clicking: View Expressions on
the menu bar).
Check that the expressions window and memory browser both report the same value for
z. Try changing the value in one window, and notice that the value also changes in the
other window.

Single-stepping the Code

26. Click the Variables tab at the top of the window to watch the local variables. Singlestep through main() by using the <F5> key (or you can use the Step Into button on
the horizontal toolbar). Check to see if the program is working as expected. What is the
value for z when you get to the end of the program?

Terminate Debug Session and Close Project

27. The Terminate button will terminate the active debug session, close the debugger and
return CCS to the CCS Edit Perspective view.
Click: Run Terminate or use the Terminate icon:
28. Next, close the project by right-clicking on Lab1 in the Project Explorer window
and select Close Project.
End of Exercise

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Peripheral Register Header Files

Peripheral Register Header Files

Traditional Approach to C Coding
#define ADCCTL1

(volatile unsigned

int *)0x00007100

...
void main(void)
{
*ADCCTL1 = 0x1234;

//write entire register

*ADCCTL1 |= 0x4000;

//enable ADC module

Advantages

- Simple, fast and easy to type

- Variable names exactly match register names (easy
to remember)

Disadvantages

- Requires individual masks to be generated to

manipulate individual bits
- Cannot easily display bit fields in debugger window
- Will generate less efficient code in many cases

In the traditional approach to C coding, we used a #define to assign the address of the register and
referenced it with a pointer. The first line of code on this slide we are writing to the entire
register with a 16-bit value. The second line, we are ORing a bit field.
Advantages? Simple, fast, and easy to type. The variable names can exactly match the register
names, so it's easy to remember. Disadvantages? Requires individual masks to be generated to
manipulate individual bits, it cannot easily display bit fields in the debugger window, and it will
generate less efficient code in many cases.

C2000 MCU 1-Day Workshop

29

Peripheral Register Header Files

Structure Approach to C Coding

void main(void)
{
AdcRegs.ADCCTL1.all = 0x1234;

//write entire register

AdcRegs.ADCCTL1.bit.ADCENABLE = 1;

//enable ADC module

Advantages

- Easy to manipulate individual bits

- Watch window is amazing! (next slide)
- Generates most efficient code (on C28x)

Disadvantages

- Can be difficult to remember the structure names

(Editor Auto Complete feature to the rescue!)
- More to type (again, Editor Auto Complete feature
to the rescue)

The structure approach to C coding uses the peripheral register header files. First, a peripheral is
specified, followed by a control register. Then you can modify the complete register or selected
bits. This is almost self-commented code.
The first line of code on this slide we are writing to the entire register. The second line of code
we are modifying a bit field. Advantages? Easy to manipulate individual bits, it works great with
our tools, and will generate the most efficient code. Disadvantages? Can be difficult to
remember the structure names and more to type; however, the edit auto complete feature of Code
Composer Studio will eliminate these disadvantages.

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C2000 MCU 1-Day Workshop

Peripheral Register Header Files

Built-in Registers Window

With the traditional approach to coding using #define, we can only view the complete register
values. As an example, notice the control register ADCCTL1 has a value of 0x40E4. We would
need to refer to the reference guide to know the settings of the individual bit fields.

Expressions Window using Structures

With the structure approach, we can add the peripheral to an expressions window, allowing us to

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31

Peripheral Register Header Files

view, as well as modify individual bit fields in a register. No need for a reference guide to
identify the bit fields.

Structure Naming Conventions

The

F2806x header files define:

All

of the peripheral structures

All of the register names
All of the bit field names
All of the register addresses
PeripheralName.RegisterName.all

// Access full 16 or 32-bit register

PeripheralName.RegisterName.half.LSW

// Access low 16-bits of 32-bit register

PeripheralName.RegisterName.half.MSW

// Access high 16-bits of 32-bit register

PeripheralName.RegisterName.bit.FieldName

// Access specified bit fields of register

Notes: [1] PeripheralName are assigned by TI and found in the F2806x header files.
They are a combination of capital and small letters (i.e. CpuTimer0Regs).
[2] RegisterName are the same names as used in the data sheet.
They are always in capital letters (i.e. TCR, TIM, TPR,..).
[3] FieldName are the same names as used in the data sheet.
They are always in capital letters (i.e. POL, TOG, TSS,..).

The header files define all of the peripheral structures, all of the register names, all of the bit field
names, and all of the register addresses. The most common naming conventions used are
PeripheralName.RegisterName.all, which will access the full 16 or 32-bit register; and
PeripheralName.RegisterName.bit.FieldName, which will access the specified bit fields of a
register.

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Peripheral Register Header Files

Editor Auto Complete to the Rescue!

This demonstrates how the editor auto complete feature works. First, you type AdcRegs. Then,
when you type a . a window opens up, allowing you to select a control register. In this example
ADCCTL1 is selected. Then, when you type the . a window opens up, allowing you to select
all or bit. In this example bit is selected. Then, when you type the . a window opens up,
allowing you to select a bit field. In this example RESET is selected. And now, the structure is
completed.

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33

Peripheral Register Header Files

F2806x Header File Package

(http://www.ti.com, controlSUITE)

Contains

everything needed to use the

structure approach
Defines all peripheral register bits and
register addresses
Header file package includes:
\F2806x_headers\include

.h files

\F2806x_headers\cmd

linker .cmd files

\F2806x_examples

CCS examples

\doc

documentation

controlSUITE Header File Package located at C:\TI\controlSUITE\device_support\

The F2806x header file package contains everything needed to use the structure approach. It
defines all the peripheral register bits and register addresses. The header file package includes the
header files, linker command files, code examples, and documentation. The header file package
is available from controlSUITE.

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C2000 MCU 1-Day Workshop

Peripheral Register Header Files

Peripheral Structure .h files (1 of 2)

Contain bits field structure definitions for each peripheral register

F2806x_Adc.h
// ADC Individual Register Bit Definitions:
struct ADCCTL1_BITS {
Uint16 TEMPCONV:1;

// bits description
// 0 Temperature sensor connection

Uint16 VREFLOCONV:1; // 1 VSSA connection

Uint16 INTPULSEPOS:1; // 2 INT pulse generation control

Your C-source file (e.g., Adc.c)

#include F2806x_Device.h"
Void InitAdc(void)
{
/* Reset the ADC module */
AdcRegs.ADCCTL1.bit.RESET = 1;
/* configure the ADC register */
AdcRegs.ADCCTL1.all = 0x00E4;

Uint16 ADCREFSEL:1;

// 3 Internal/external reference select

Uint16 rsvd1:1;

// 4 reserved

Uint16 ADCREFPWD:1;

// 5 Reference buffers powerdown

Uint16 ADCBGPWD:1;

// 6 ADC bandgap powerdown

Uint16 ADCPWDN:1;

// 7 ADC powerdown

Uint16 ADCBSYCHN:5;

// 12:8 ADC busy on a channel

Uint16 ADCBSY:1;

// 13 ADC busy signal

Uint16 ADCENABLE:1;

// 14 ADC enable

Uint16 RESET:1;

// 15 ADC master reset

};

};

// Allow access to the bit fields or entire register:

union ADCCTL1_REG {
Uint16

all;

struct ADCCTL1_BITS bit;

};
// ADC External References & Function Declarations:
extern volatile struct ADC_REGS AdcRegs;

Next, we will discuss the steps needed to use the header files with your project. The .h files
contain the bit field structure definitions for each peripheral register.

Peripheral Structure .h files (2 of 2)

The

header file package contains a .h file for

each peripheral in the device
F2806x_Adc.h

F2806x_BootVars.h

F2806x_Cla.h

F2806x_Comp.h

F2806x_CpuTimers.h

F2806x_DevEmu.h

F2806x_Device.h

F2806x_Dma.h

F2806x_ECan.h

F2806x_ECap.h

F2806x_EPwm.h

F2806x_EQep.h

F2806x_Gpio.h

F2806x_I2c.h

F2806x_Mcbsp.h

F2806x_NmiIntrupt.h

F2806x_PieCtrl.h

F2806x_PieVect.h

F2806x_Sci.h

F2806x_Spi.h

F2806x_SysCtrl.h

F2806x_Usb.h

F2806x_XIntrupt.h

F2806x_Device.h
Main

include file
Will include all other .h files
Include this file (directly or indirectly)
in each source file:
#include

F2806x_Device.h

The header file package contains a .h file for each peripheral in the device. The
F2806x_Device.h file is the main include file. It will include all of the other .h files. There are

C2000 MCU 1-Day Workshop

35

Peripheral Register Header Files

three steps needed to use the header files. The first step is to include this file directly or indirectly
in each source files.

Global Variable Definitions File

F2806x_GlobalVariableDefs.c

Declares

a global instantiation of the structure

for each peripheral

Each

structure is placed in its own section using

a DATA_SECTION pragma to allow linking to the
correct memory (see next slide)
F2806x_GlobalVariableDefs.c
#include "F2806x_Device.h"

#pragma DATA_SECTION(AdcRegs,"AdcRegsFile");
volatile struct ADC_REGS AdcRegs;

Add

this file to your CCS project:

F2806x_GlobalVariableDefs.c
The global variable definition file declares a global instantiation of the structure for each
peripheral. Each structure is placed in its own section using a DATA_SECTION pragma to allow
linking to the correct memory. The second step for using the header files is to add
F2806x_GlobalVariableDefs.c file to your project.

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C2000 MCU 1-Day Workshop

Peripheral Register Header Files

Linker Command Files for the Structures

F2806x_nonBIOS.cmd and F2806x_BIOS.cmd
F2806x_GlobalVariableDefs.c
#include "F2806x_Device.h"

Links each structure to

the address of the
peripheral using the
structures named
section

non-BIOS and BIOS

versions of the .cmd file

Add one of these files to

your CCS project:

#pragma DATA_SECTION(AdcRegs,"AdcRegsFile");
volatile struct ADC_REGS AdcRegs;

F2806x_Headers_nonBIOS.cmd
MEMORY
{
PAGE1:
...
ADC:
...
}

origin=0x007100, length=0x000080

SECTIONS
{
...
AdcRegsFile:
...
}

F2806x_nonBIOS.cmd
or
F2806x_BIOS.cmd
>

ADC

PAGE = 1

The header file package has two linker command file versions; one for non-BIOS projects and
one for BIOS projects. This linker command file is used to link each structure to the address of
the peripheral using the structures named section. The third and final step for using the header
files is to add the appropriate linker command file to your project.

Peripheral Specific Examples

Example

projects for each peripheral

Helpful to get you started

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37

Peripheral Register Header Files

The peripheral register header file package includes example projects for each peripheral. This
can be very helpful to getting you started.

Peripheral Register Header Files

Summary
Easier

code development
Easy to use
Generates most efficient code
Increases effectiveness of CCS watch window
TI has already done all the work!
Use

the correct header file package for your device:

F2806x

F280x and F2801x

F2803x

F2804x

F2802x

F281x

F2833x and F2823x

Go to http://www.ti.com and enter controlSUITE in the keyword search box

In summary, the peripheral register header files allow for easier code development, they are easy
to use, generates the most efficient code, works great with Code Composer Studio, and TI has
already done the work for you. Just make sure to use the correct header file package for your
device.

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Reset, Interrupts and System Initialization

Reset, Interrupts and System Initialization

Reset

Reset Sources
Missing Clock Detect

F28x core

Watchdog Timer
Power-on Reset

XRS

Brown-out Reset
XRS pin active

To XRS pin

Logic shown is functional representation, not actual implementation

POR Power-on Reset generates a device reset during

power-up conditions
BOR Brown-out Reset generates a device reset if the

power supply drops below specification for the device

Note: Devices support an on-chip voltage regulator (VREG) to
generate the core voltage

There are various reset sources available for this device: an external reset pin, watchdog timer
reset, power-on reset which generates a device reset during power-up conditions, brownout reset
which generates a device reset if the power supply drops below specifications for the device, as
well as a missing clock detect reset. Additionally, the device incorporates an on-chip voltage
regulator to generate the core voltage.

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Reset, Interrupts and System Initialization

Reset Bootloader
Reset
ENPIE = 0
INTM = 1

YES
TRST = 1

Emulation Boot
Boot determined by
2 RAM locations:
EMU_KEY and EMU_BMODE

Reset vector
fetched from
boot ROM
0x3F FFC0

Emulator
Connected ?

NO
TRST = 0

Stand-alone Boot
Boot determined by
2 GPIO pins and
2 OTP locations:
OTP_KEY and OTP_BMODE

TRST = JTAG Test Reset

EMU_KEY & EMU_BMODE located in PIE at 0x0D00 & 0x0D01, respectively

OTP_KEY & OTP_BMODE located in OTP at 0x3D7BFB & 0x3D7BFE, respectively

After reset, the PIE block is disabled and the global interrupt line is disabled. The reset vector is
fetched from the boot ROM and the bootloader process begins.
Then the bootloader determines if the emulator is connected by checking the JTAG test reset line.
If the emulator is connected, we are in emulation boot mode. The boot is then determined by two
RAM locations named EMU_Key and EMU_BMODE, which are located in the PIE block. If the
emulator is not connected, we are in stand-alone boot mode. The boot is then determined by two
GPIO pins and two OTP locations named OTP_KEY and OTP_BMODE, which are located in
the OTP.

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C2000 MCU 1-Day Workshop

Reset, Interrupts and System Initialization

Emulation Boot Mode (TRST = 1)

Emulator Connected
If either EMU_KEY or EMU_BMODE
are invalid, the wait boot mode is
used. These values can then be
modified using the debugger and a
reset issued to restart the boot process

Emulation Boot
Boot determined by
2 RAM locations:
EMU_KEY and EMU_BMODE

EMU_KEY = 0x55AA ?

NO

Boot Mode
Wait

YES
EMU_BMODE =
0x0000
0x0001
0x0003
0x0004
0x0005
0x0006
0x0007
0x000A
0x000B
other

Boot Mode
Parallel I/O
SCI
GetMode
SPI
I2C
OTP
CAN
M0 SARAM
FLASH
Wait

OTP_KEY = 0x005A ?

NO

Boot Mode
FLASH

YES
OTP_BMODE =
0x0001
0x0004
0x0005
0x0006
0x0007
other

Boot Mode
SCI
SPI
I2C
OTP
CAN
FLASH

In emulation boot mode, first the EMU_KEY register is checked to see if it has a value of
0x55AA. If either EMU_KEY or EMU_BMODE are invalid, the wait boot mode is used. These
values can then be modified using the debugger and a reset issued to restart the boot process.
This can be considered the default on power-up. At this point, you would like the device to wait
until given a boot mode.
If EMU_KEY register has a value of 0x55AA, then the hex value in the EMU_BMODE register
determines the boot mode. The boot modes are parallel I/O, SCI, SPI, I2C, OTP, CAN,
M0SARAM, FLASH, and Wait. In addition, there is a GetMode, which emulates the stand-alone
boot mode.

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Stand-Alone Boot Mode (TRST = 0)

Emulator Not Connected

Stand-alone Boot
Boot determined by
2 GPIO pins and
2 OTP locations:

Note that the boot behavior for

unprogrammed OTP is the
FLASH boot mode

OTP_KEY and OTP_BMODE

OTP_KEY = 0x005A ?
GPIO
37
0
0
1
1

GPIO
34
0
1
0
1

NO

Boot Mode
FLASH

YES
Boot Mode
Parallel I/O
SCI
Wait
GetMode

OTP_BMODE =
0x0001
0x0004
0x0005
0x0006
0x0007
other

Boot Mode
SCI
SPI
I2C
OTP
CAN
FLASH

In stand-alone boot mode, GPIO pins 37 and 34 determine if the boot mode is parallel I/O, SCI,
or wait. The default unconnected pins would set the boot mode to GetMode. In GetMode, first
the OTP_KEY register is checked to see if it has a value of 0x005A. An unprogrammed OTP is
set to the FLASH boot mode, as expected.
If the OTP_KEY register has a value of 0x005A, then the hex value in the OTP_BMODE register
determines the boot mode. The boot modes are SCI, SPI, I2C, OTP, CAN, and FLASH.

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Reset Code Flow - Summary

0x000000

0x000000

M0 SARAM (1Kw)
0x3D7800

0x3D7800

OTP (1Kw)
0x3D8000
FLASH (128Kw)
0x3F7FF6

0x3F8000

Boot ROM (32Kw)

Boot Code
0x3FF75C

0x3FFFC0

RESET

Execution Entry
determined by
Emulation Boot Mode or
Stand-Alone Boot Mode

BROM vector (64w)

0x3FF75C

Bootloading
Routines
(SCI, SPI, I2C,
CAN, Parallel I/O)

In summary, the reset code flow is as follows: The reset vector is fetched from the boot ROM.
Then, the execution entry is determined by emulation boot mode or stand-alone boot mode. The
boot mode options are M0SARAM, OTP, FLASH, and boot loading routines.

After reset how do we get to main() ?

At

the code entry point, branch to _c_int00()

Part

of compiler runtime support library

Sets up compiler environment
Calls main()
CodeStartBranch.asm

.sect codestart
LB _c_int00

Linker .cmd

MEMORY
{
PAGE 0:
BEGIN_M0
}
SECTIONS
{
codestart
}

: origin = 0x000000, length = 0x000002

: > BEGIN_M0, PAGE = 0

Note: the above example is for boot mode set to M0 SARAM; to run out of Flash, the
codestart section would be linked to the entry point of the Flash memory block

After reset how do we get to main? When the bootloader process is completed, a branch to the

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compiler runtime support library is located at the code entry point. This branch to _c_int00 is
executed, then the compiler environment is set up, and finally main is called.

Interrupts

Interrupt Sources
Internal Sources
TINT2
TINT1
TINT0
ePWM, eCAP, eQEP,
ADC, SCI, SPI, I2C,
eCAN, McBSP,
DMA, CLA, WD

External Sources
XINT1 XINT3

F28x CORE
XRS
NMI
PIE
(Peripheral
Interrupt
Expansion)

INT1
INT2
INT3

INT12
INT13
INT14

TZx
XRS

The internal interrupt sources include the general purpose timers 0, 1, and 2, and all of the
peripherals on the device. External interrupt sources include the three external interrupt lines, the
trip zones, and the external reset pin. The core has 14 interrupt lines. As you can see, the number
of interrupt sources exceeds the number of interrupt lines on the core. The PIE, or Peripheral
Interrupt Expansion block, is connected to the core interrupt lines 1 through 12. This block
manages and expands the 12 core interrupt lines, allowing up to 96 possible interrupt sources.

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Maskable Interrupt Processing

Conceptual Core Overview

Core
Interrupt

(IFR)
Latch

INT1

INT2

INT14

(IER)
(INTM)
Switch Global Switch

F28x
Core

A valid signal on a specific interrupt line causes the latch

to display a 1 in the appropriate bit

If the individual and global switches are turned on the

interrupt reaches the core

It is easier to explain the interrupt processing flow from the core back out to the interrupt sources.
The INTM is the master interrupt switch. This switch must be closed for any interrupts to
propagate into the core. The next layer out is the interrupt enable register. The appropriate
interrupt line switch must be closed to allow an interrupt through. The interrupt flag register gets
set when an interrupt occurs. Once the core starts processing an interrupt, the INTM switch
opens to avoid nested interrupts and the flag is cleared.

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Core Interrupt Registers

Interrupt Flag Register (IFR)
15

14

RTOSINT DLOGINT

(pending = 1 / absent = 0)

13

12

11

10

INT14

INT13

INT12

INT11

INT10

INT9

INT8

INT7

INT6

INT5

INT4

INT3

INT2

INT1

Interrupt Enable Register (IER)

15

14

RTOSINT DLOGINT

(enable = 1 / disable = 0)

13

12

11

10

INT14

INT13

INT12

INT11

INT10

INT9

INT3

INT2

INT1

INT8

INT7

INT6

INT5

INT4

Interrupt Global Mask Bit (INTM)

Bit 0
INTM

ST1

(enable = 0 / disable = 1)

/*** Interrupt Enable Register ***/

extern cregister volatile unsigned int IER;
IER |= 0x0008;

//enable INT4 in IER

IER &= 0xFFF7;

//disable INT4 in IER

/*** Global Interrupts ***/

asm( CLRC INTM);

//enable global interrupts

asm( SETC INTM);

//disable global interrupts

The core interrupt registers consists of the interrupt flag register, interrupt enable register, and
interrupt global mask bit. Notice that the interrupt global mask bit is zero when enabled and one
when disabled. The interrupt enable register is managed by ORing and ANDing mask values.
The interrupt global mask bit is managed using inline assembly.

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Peripheral Interrupt Expansion (PIE)

Peripheral Interrupt Expansion - PIE

Interrupt Group 1

PIE module for 96 Interrupts

INT1.8

INT6.y interrupt group

INT7.y interrupt group

Core Interrupt logic

INT8.y interrupt group

INT9.y interrupt group

INT1 INT12

INT10.y interrupt group

12 Interrupts

INT11.y interrupt group

INT1

INTM

96

INT1.2

IER

INT3.y interrupt group

INT4.y interrupt group
INT5.y interrupt group

INT1.1

IFR

Peripheral Interrupts

12 x 8 = 96

INT1.y interrupt group

INT2.y interrupt group

PIEIFR1 PIEIER1

28x
Core

INT12.y interrupt group

INT13 (TINT1)
INT14 (TINT2)
NMI

We have already discussed the interrupt process in the core. Now we need to look at the
peripheral interrupt expansion block. This block is connected to the core interrupt lines 1 through
12. The PIE block consists of 12 groups. Within each group, there are eight interrupt sources.
Each group has a PIE interrupt enable register and a PIE interrupt flag register.
As you can see, the interrupts are numbered from 1.1 through 12.8, giving us a maximum of 96
interrupt sources. Interrupt lines 13, 14, and NMI bypass the PIE block.

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F2806x PIE Interrupt Assignment Table

INTx.8

INTx.7

INTx.6

INTx.5

INTx.4

INTx.3

INTx.2

INTx.1

INT1

WAKEINT

TINT0

ADCINT9

XINT2

XINT1

ADCINT2

ADCINT1

INT2

EPWM8
_TZINT

EPWM7
_TZINT

EPWM6
_TZINT

EPWM5
_TZINT

EPWM4
_TZINT

EPWM3
_TZINT

EPWM2
_TZINT

EPWM1
_TZINT

INT3

EPWM8
_INT

EPWM7
_INT

EPWM6
_INT

EPWM5
_INT

EPWM4
_INT

EPWM3
_INT

EPWM2
_INT

EPWM1
_INT

INT4

HRCAP2
_INT

HRCAP1
_INT

ECAP3
_INT

ECAP2
_INT

ECAP1
_INT

EQEP2
_INT

EQEP1
_INT

INT5

HRCAP4
_INT

HRCAP3
_INT

INT6

MXINTA

MRINTA

SPITX
INTB

SPIRX
INTB

SPITX
INTA

SPIRX
INTA

INT7

DINTCH6

DINTCH5

DINTCH4

DINTCH3

DINTCH2

DINTCH1

I2CINT2A

I2CINT1A

ECAN1
_INTA

ECAN0
_INTA

SCITX
INTB

SCIRX
INTB

SCITX
INTA

SCIRX
INTA

INT8
INT9
INT10

ADCINT8

ADCINT7

ADCINT6

ADCINT5

ADCINT4

ADCINT3

ADCINT2

ADCINT1

INT11

CLA1
_INT8

CLA1
_INT7

CLA1
_INT6

CLA1
_INT5

CLA1
_INT4

CLA1
_INT3

CLA1
_INT2

CLA1
_INT1

INT12

LUF

LVF

XINT3

The interrupt assignment table tells us the location for each interrupt source within the PIE block.
Notice the table is numbered from 1.1 through 12.8, perfectly matching the PIE block.

PIE Registers
PIEIFRx register
15 - 8

(x = 1 to 12)
7

reserved

INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1

PIEIERx register
15 - 8

(x = 1 to 12)
7

reserved

INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1

PIE Interrupt Acknowledge Register (PIEACK)

15 - 12

11

10

reserved

PIEACKx

PIECTRL register

15 - 1

PIEVECT

ENPIE

#include F2806x_Device.h
PieCtrlRegs.PIEIFR1.bit.INTx4 = 1;

//manually set IFR for XINT1 in PIE group 1

PieCtrlRegs.PIEIER3.bit.INTx2 = 1;

//enable EPWM2_INT in PIE group 3

PieCtrlRegs.PIEACK.all = 0x0004;

//acknowledge the PIE group 3

PieCtrlRegs.PIECTRL.bit.ENPIE = 1; //enable the PIE

The PIE registers consist of 12 PIE interrupt flag registers, 12 PIE interrupt enable registers, a
PIE interrupt acknowledge register, and a PIE control register. The enable PIE bit in the PIE

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control register must be set during initialization for the PIE block to be enabled.

PIE Block Initialization

Memory Map

Main.c
// CPU Initialization

InitPieCtrl();

PieVect.c

PieCtrl.c
2

// Initialize PIE_RAM

memcpy(
);

// Enable PIE Block

PieCtrlRegs.
PIECTRL.bit.
ENPIE=1;

PIE_VECT_TABLE
// Base Vectors

// Core INT1 re-map

// Core INT12 re-map

PIE RAM
Vectors
256w
(ENPIE = 1)

Boot ROM
Reset Vector
3

The interrupt vector table, as mapped in the PIE interrupt assignment table, is located in the
PieVect.c file. During initialization in main, we have a function call to PieCtrl.c. In this file, a
memory copy function copies the interrupt vector table to the PIE RAM and then sets ENPIE to
1, enabling the PIE block. This process is done to set up the vectors for interrupts.

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PIE Initialization Code Flow - Summary

RESET
<0x3F FFC0>

Reset Vector

Boot option determines

code execution entry point

<0x3F F75C> = Boot Code

CodeStartBranch.asm
.sect codestart
M0SARAM Entry Point
<0x00 0000> = LB _c_int00

Flash Entry Point

OR <0x3F 7FF6> = LB _c_int00

_c_int00:

rts2800_fpu32.lib
Interrupt

CALL main()
PIE Vector Table
Main.c
main()
{ initialization();
}

Initialization()
{
Load PIE Vectors
Enable the PIE
Enable PIEIER
Enable Core IER
Enable INTM
}

256 Word RAM

0x00 0D00 0DFF
DefaultIsr.c
interrupt void name(void)
{
}

In summary, the PIE initialization code flow is as follows. After the device is reset and executes
the boot code, the selected boot option determines the code entry point. This figure shows two
different entry points. The one on the left is for memory block M0, and the one on the right is for
flash.
In either case, CodeStartBranch.asm has a Long Branch to the entry point of the runtime
support library. After the runtime support library completes execution, it calls main. In main, we
have a function call to initialize the interrupt process and enable the PIE block. When an
interrupt occurs, the PIE block contains a vector to the interrupt service routine located in
DefaultIsr.c.

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Interrupt Signal Flow Summary

Peripheral Interrupt Expansion (PIE) Interrupt Group x
PIEIFRx
PIEIERx
INTx.y

Peripheral
Interrupt

PieCtrlRegs.PIEIERx.bit.INTxy = 1;

Core Interrupt Logic

Core
INTx

IFR

IER

INTM

IER |= 0x0001;
0x0FFF;

asm( CLRC INTM);

PIE Vector Table

DefaultIsr.c
interrupt void name(void)
{

}
INTx.y name

(For peripheral interrupts where x = 1 to 12, and y = 1 to 8)

In summary, the following steps occur during an interrupt process. First, a peripheral interrupt is
generated and the PIE interrupt flag register is set. If the PIE interrupt enable register is enabled,
then the core interrupt flag register will be set. Next, if the core interrupt enable register and
global interrupt mask is enabled, the PIE vector table will redirect the code to the interrupt service
routine.

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Oscillator / PLL Clock Module

F2806x Oscillator / PLL Clock Module

(lab file: SysCtrl.c)
WDCLKSRCSEL

Internal
OSC 1
(10 MHz)

OSC1CLK

0* WDCLK
1

Watchdog
Module

OSCCLKSRCSEL
OSCCLKSRC2

OSC2CLK

1
0*

0*
1

OSCCLK
(PLL bypass)

PLL

DIVSEL

MUX

Internal
OSC 2
(10 MHz)

XTAL

X1

X2

0*
1
XTAL OSC

CLKIN

VCOCLK

C28x
Core

SYSCLKOUT

XCLKINOFF

XCLKIN

1/n

DIV

EXTCLK

SYSCLKOUT

TMR2CLKSRCSEL

10
11 CPUTMR2CLK
01
00*
CPU
Timer 2

LOSPCP
LSPCLK
SCI, SPI
All other peripherals
clocked by SYSCLKOUT
* = default

The oscillator/PLL clock module has two internal, 10 MHz oscillators, and the availability of an
external oscillator or crystal. This provides redundancy in case an oscillator fails, as well as the
ability to use multiple oscillators. The asterisks in the multiplexers show the default settings.
This module has the capability to clock the watchdog, core, and CPU timer 2 from independent
clock sources, if needed. Next, we will look at the details for clocking the core.

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F2806x PLL and LOSPCP

(lab file: SysCtrl.c)

PLL
DIV
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
1xx11

VCOCLK

SysCtrlRegs.PLLSTS.bit.DIVSEL

MUX

OSCCLK
(PLL bypass)

1/n

CLKIN

C28x
Core

SysCtrlRegs.PLLCR.bit.DIV

CLKIN
OSCCLK / n * (PLL bypass)
OSCCLK x 1 / n
OSCCLK x 2 / n
OSCCLK x 3 / n
OSCCLK x 4 / n
OSCCLK x 5 / n
OSCCLK x 6 / n
OSCCLK x 7 / n
OSCCLK x 8 / n
OSCCLK x 9 / n
OSCCLK x 10 / n
OSCCLK x 11 / n
OSCCLK x 12 / n
OSCCLK x 13 / n
OSCCLK x 14 / n
OSCCLK x 15 / n
OSCCLK x 16 / n
OSCCLK x 17 / n
OSCCLK x 18 / n
reserved

SYSCLKOUT

LOSPCP

LSPCLK

SysCtrlRegs.LOSPCP.bit.LSPCLK
DIVSEL
0x
10
11
* default

n
/4 *
/2
/1

LSPCLK
000
001
010
011
100
101
110
111

Peripheral Clk Freq

SYSCLKOUT / 1
SYSCLKOUT / 2
SYSCLKOUT / 4 *
SYSCLKOUT / 6
SYSCLKOUT / 8
SYSCLKOUT / 10
SYSCLKOUT / 12
SYSCLKOUT / 14

LSBs in reg. others reserved

Input Clock Fail Detect Circuitry

PLL will issue a limp mode clock (1-4 MHz) if input
clock is removed after PLL has locked.
An internal device reset will also be issued (XRSn
pin not driven).

A clock source can be fed directly into the core or multiplied using the PLL. The PLL gives us
the capability to use the internal 10 MHz oscillator multiplied by 18/2, and run the device at the
full 90 MHz clock frequency. If the input clock is removed after the PLL is locked, the input
clock failed detect circuitry will issue a limp mode clock of 1 to 4 MHz. Additionally, an internal
device reset will be issued. The low-speed peripheral clock prescaler is used to clock some of the
communication peripherals.

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Watchdog Timer Module

Watchdog Timer
Resets

the C28x if the CPU crashes

Watchdog

counter runs independent of CPU

If counter overflows, a reset or interrupt is
triggered (user selectable)
CPU must write correct data key sequence
to reset the counter before overflow
Watchdog

must be serviced or disabled

within 131,072 WDCLK cycles after reset
This translates to 13.11 ms with a 10 MHz
WDCLK

The watchdog timer is a safety feature, which resets the device if the program runs away or gets
trapped in an unintended infinite loop.
The watchdog counter runs independent of the CPU. If the counter overflows, a reset or interrupt
is triggered. The CPU must write the correct data key sequence to reset the counter before it
overflows. The watchdog must be serviced or disabled within 131,072 watchdog clock cycles
after reset. This translates to 13.11 milliseconds with a 10 MHz watchdog clock.

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Watchdog Timer Module

(lab file: Watchdog.c)

WDCLK

/512

WDPS

WDOVERRIDE

Watchdog
Prescaler

WDDIS

8-bit Watchdog
Counter
CLR
WDRST

System
Reset

Output
Pulse
WDINT

WDCHK

55 + AA
Detector
Watchdog
Reset Key
Register

Good Key

/
/

Bad WDCHK Key

1 0 1

The watchdog clock is divided by 512 and prescaled, if desired. The watchdog disable switch
allows the watchdog to be enabled and disabled. The watchdog override switch is a safety
mechanism, and once closed, it can only be open by resetting the device.
During initialization, 101 is written into the watchdog check bit fields. Any other values will
cause a reset or interrupt. During run time, the correct keys must be written into the watchdog
key register before the watchdog counter overflows and issues a reset or interrupt. Issuing a reset
or interrupt is user-selectable.

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GPIO

F2806x GPIO Grouping Overview

(lab file: Gpio.c)

GPIO Port A Mux2

Register (GPAMUX2)
[GPIO 16 to 31]

GPIO Port B Mux2

Register (GPBMUX2)
[GPIO 48 to 63]

Qual

Input
GPIO Port B
Direction Register
(GPBDIR)
[GPIO 32 to 63]

ANALOG Port
Direction Register
(AIODIR)
[AIO 0 to 15]

Qual

ANALOG Port

ANALOG I/O Mux1

Register (AIOMUX1)
[AIO 0 to 15]

Input

GPIO Port B

Internal Bus

GPIO Port B Mux1

Register (GPBMUX1)
[GPIO 32 to 47]

GPIO Port A
Direction Register
(GPADIR)
[GPIO 0 to 31]

GPIO Port A

GPIO Port A Mux1

Register (GPAMUX1)
[GPIO 0 to 15]

Each general-purpose I/O pin has a maximum of four options, either general-purpose I/O or up to
three possible peripheral pin assignments. This is selected using the GPIO port multiplexer. If
the pin is set to GPIO, the direction register sets it as an input or an output. The input
qualification will be explained shortly.

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F2806x GPIO Pin Block Diagram

(lab file: Gpio.c)
Peripheral
1

I/O DIR Bit

0 = Input
1 = Output

GPxSET
GPxCLEAR
GPxTOGGLE

Peripheral
3

GPxDIR

10
11
00

GPxDAT

01

Out
I/O DAT
Bit (R/W)

Peripheral
2

In

GPxPUD

Input
Qualification
(GPIO 0-44)

Internal Pull-Up
0 = enable (default GPIO 12-58)
1 = disable (default GPIO 0-11)

GPxMUX1
GPxMUX2
MUX Control Bits *
00 = GPIO
01 = Peripheral 1
10 = Peripheral 2
11 = Peripheral 3

GPxQSEL1
GPxQSEL2
GPxCTRL

Pin
* See device datasheet for pin function selection matrices

This figure shows a single GPIO pin. If the pin is set as a GPIO by the GPIO multiplexer, the
direction will be set by the GPIO direction register. The GPIO data register will have the value of
the pin if set as an input or write the value of the data register to the pin if set as an output.
The data register can be quickly and easily modified using set, clear, or toggle registers. As you
can see, the GPIO multiplexer can be set to select up to three other possible peripheral pin
assignments. Also, the pin has an option for an internal pull-up.

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F2806x GPIO Input Qualification

pin

to GPIO and
peripheral
modules

Input
Qualification
SYSCLKOUT

Qualification available on ports A & B only

Individually selectable per pin

samples taken

no qualification (peripherals only)

sync to SYSCLKOUT only
qualify 3 samples
qualify 6 samples

AIO pins are fixed as

sync to SYSCLKOUT

T = qual period

The GPIO input qualification feature allows filtering out noise on a pin. The user would select
the number of samples and qualification period. Qualification is available on ports A and B only
and is individually selectable per pin.

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Lab 2: System Initialization

LAB2

files have been provided

LAB2 consists of two parts:
Part 1
Test behavior of watchdog when disabled and enabled
Part 2
Initialize peripheral interrupt expansion (PIE) vectors and
use watchdog to generate an interrupt
Modify,

build, and test code using Code

Composer Studio

This lab exercise consists of two parts. In the first part we will test the behavior of the watchdog
when disabled and enabled. In the second part we will initialize the peripheral interrupt
expansion vectors and use the watchdog to generate an interrupt.

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Lab 2: System Initialization

Objective
The objective of this lab is to perform the processor system initialization. Additionally, the
peripheral interrupt expansion (PIE) vectors will be initialized and tested. The system
initialization for this lab will consist of the following:

Setup the clock module PLL, LOSPCP = /4, low-power modes to default values, enable all
module clocks

Disable the watchdog clear WD flag, disable watchdog, WD prescale = 1

Setup the watchdog and system control registers DO NOT clear WD OVERRIDE bit,
configure WD to generate a CPU reset

Setup the shared I/O pins set all GPIO pins to GPIO function (e.g. a "00" setting for GPIO
function, and a 01, 10, or 11 setting for peripheral function)

The first part of the lab exercise will setup the system initialization and test the watchdog
operation by having the watchdog cause a reset. In the second part of the lab exercise the PIE
vectors will be tested by using the watchdog to generate an interrupt. This lab will make use of
the F2806x C-code header files to simplify the programming of the device, as well as take care of
the register definitions and addresses. Please review these files, and make use of them in the
future, as needed.

Procedure

Open the Project

1. A project named Lab2 has been created for this lab. Open the project by clicking on
Project Import Existing CCS Eclipse Project. The Import
window will open then click Browse next to the Select search-directory box.
Navigate to: C:\C28x\Labs\Lab2\Project and click OK. Then click Finish to
import the project.
2. In the Project Explorer window, click the plus sign (+) to the left of Lab2 to view
the project files. All Build Options have been configured for this lab. The files used in
this lab are:
CodeStartBranch.asm
DefaultIsr_2.c
DelayUs.asm
F2806x_DefaultIsr.h
F2806x_GlobalVariableDefs.c
F2806x_Headers_nonBIOS.cmd
Gpio.c

60

Lab.h
Lab_2_3.cmd
Main_2.c
PieCtrl.c
PieVect.c
SysCtrl.c
Watchdog.c

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Lab 2: System Initialization

Modified Memory Configuration

3. Open and inspect the linker command file Lab_2_3.cmd. Notice that the user defined
section codestart is being linked to a memory block named BEGIN_M0. The
codestart section contains code that branches to the code entry point of the project. The
bootloader must branch to the codestart section at the end of the boot process. Recall that
the emulation boot mode "M0 SARAM" branches to address 0x000000 upon bootloader
completion.
The linker command file (Lab_2_3.cmd) has a new memory block named BEGIN_M0:
origin = 0x000000, length = 0x0002, in program memory. Additionally, the existing
memory block M0SARAM in data memory has been modified to avoid overlaps with this
new memory block.
4. In the linker command file, notice that RESET in the MEMORY section has been defined
using the (R) qualifier. This qualifier indicates read-only memory, and is optional. It
will cause the linker to flag a warning if any uninitialized sections are linked to this
memory. The (R) qualifier can be used with all non-volatile memories (e.g., flash, ROM,
OTP), as you will see in a later lab exercise.

System Initialization
5. Open and inspect SysCtrl.c. Notice that the PLL and module clocks have been
enabled.
6. Open and inspect Watchdog.c. Notice that the watchdog control register (WDCR) is
configured to disable the watchdog, and the system control and status register (SCSR) is
configured to generate a reset.
7. Open and inspect Gpio.c. Notice that the shared I/O pins have been set to the GPIO
function, except for GPIO0 which will be used in the next lab exercise. Close the
inspected files.

Build and Load

8. Click the Build button and watch the tools run in the Console window. Check for
errors in the Problems window.
9. Click the Debug button (green bug). The CCS Debug Perspective view should
open, the program will load automatically, and you should now be at the start of
main().
10. After CCS loaded the program in the previous step, it set the program counter (PC) to
point to _c_int00. It then ran through the C-environment initialization routine in the
rts2800_fpu32.lib and stopped at the start of main(). CCS did not do a device
reset, and as a result the bootloader was bypassed.
In the remaining parts of this lab exercise, the device will be undergoing a reset due to the
watchdog timer. Therefore, we must configure the device by loading values into
EMU_KEY and EMU BMODE so the bootloader will jump to M0 SARAM at address
0x000000. Set the bootloader mode using the menu bar by clicking:
Scripts EMU Boot Mode Select EMU_BOOT_SARAM

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If the device is power cycled between lab exercises, or within a lab exercise, be sure to
re-configure the boot mode to EMU_BOOT_SARAM.

Run the Code Watchdog Reset

11. Place the cursor in the main loop section (on the asm( NOP); instruction line)
and right click the mouse key and select Run To Line. This is the same as setting a
breakpoint on the selected line, running to that breakpoint, and then removing the
breakpoint.
12. Place the cursor on the first line of code in main() and set a breakpoint by double
clicking in the line number field to the left of the code line. Notice that line is
highlighted with a blue dot indicating that the breakpoint has been set. (Alternately, you
can set a breakpoint on the line by right-clicking the mouse and selecting Breakpoint
(Code Composer Studio) Breakpoint). The breakpoint is set to prove
that the watchdog is disabled. If the watchdog causes a reset, code execution will stop at
this breakpoint.
13. Run your code for a few seconds by using the Resume button on the toolbar, or by
using Run Resume on the menu bar (or F8 key). After a few seconds halt your
code by using the Suspend button on the toolbar, or by using Run Suspend on
the menu bar (or Alt-F8 key). Where did your code stop? Are the results as expected? If
things went as expected, your code should be in the main loop.
14. Switch to the CCS Edit Perspective view by clicking the CCS Edit icon in the upper
right-hand corner. Modify the InitWatchdog() function to enable the watchdog
(WDCR). In Watchdog.c change the WDCR register value to 0x00A8. This will
enable the watchdog to function and cause a reset. Save the file.
15. Click the Build button. Select Yes to Reload the program automatically. Switch
back to the CCS Debug Perspective view by clicking the CCS Debug icon in the
upper right-hand corner.
16. Like before, place the cursor in the main loop section (on the asm( NOP);
instruction line) and right click the mouse key and select Run To Line.
17. Run your code. Where did your code stop? Are the results as expected? If things went
as expected, your code should have stopped at the breakpoint. What happened is as
follows. While the code was running, the watchdog timed out and reset the processor.
The reset vector was then fetched and the ROM bootloader began execution. Since the
device is in emulation boot mode (i.e. the emulator is connected) the bootloader read the
EMU_KEY and EMU_BMODE values from the PIE RAM. These values were
previously set for boot to M0 SARAM bootmode by CCS. Since these values did not
change and are not affected by reset, the bootloader transferred execution to the
beginning of our code at address 0x000000 in the M0SARAM, and execution continued
until the breakpoint was hit in main( ).

Setup PIE Vector for Watchdog Interrupt

The first part of this lab exercise used the watchdog to generate a CPU reset. This was tested
using a breakpoint set at the beginning of main(). Next, we are going to use the watchdog

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to generate an interrupt. This part will demonstrate the interrupt concepts learned in this
module.
18. Switch to the CCS Edit Perspective view by clicking the CCS Edit icon in the upper
right-hand corner. Notice that the following files are included in the project:
DefaultIsr_2.c
PieCtrl.c
PieVect.c
19. In Main_2.c, uncomment the code used to call the InitPieCtrl() function. There
are no passed parameters or return values, so the call code is simply:
InitPieCtrl();
20. Using the PIE Interrupt Assignment Table shown in the slides find the location for the
watchdog interrupt, WAKEINT. This is used in the next step.
PIE group #:

# within group:

21. In main() notice the code used to enable global interrupts (INTM bit), and in
InitWatchdog() the code used to enable the WAKEINT interrupt in the PIE
(using the PieCtrlRegs structure) and to enable core INT1 (IER register).
22. Modify the system control and status register (SCSR) to cause the watchdog to generate
a WAKEINT rather than a reset. In Watchdog.c change the SCSR register value to
0x0002. Save the modified files.
23. Open and inspect DefaultIsr_2.c. This file contains interrupt service routines. The
ISR for WAKEINT has been trapped by an emulation breakpoint contained in an inline
assembly statement using ESTOP0. This gives the same results as placing a breakpoint
in the ISR. We will run the lab exercise as before, except this time the watchdog will
generate an interrupt. If the registers have been configured properly, the code will be
trapped in the ISR.
24. Open and inspect PieCtrl.c. This file is used to initialize the PIE RAM and enable
the PIE. The interrupt vector table located in PieVect.c is copied to the PIE RAM to
setup the vectors for the interrupts. Close the modified and inspected files.

Build and Load

25. Click the Build button and select Yes to Reload the program automatically.
Switch to the CCS Debug Perspective view by clicking the CCS Debug icon in the
upper right-hand corner.

Run the Code Watchdog Interrupt

26. Place the cursor in the main loop section, right click the mouse key and select Run
To Line.
27. Run your code. Where did your code stop? Are the results as expected? If things went
as expected, your code should stop at the ESTOP0 instruction in the WAKEINT ISR.

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Terminate Debug Session and Close Project

28. Terminate the active debug session using the Terminate button. This will close the
debugger and return CCS to the CCS Edit Perspective view.
29. Next, close the project by right-clicking on Lab2 in the Project Explorer window
and select Close Project.
End of Exercise
Note: By default, the watchdog timer is enabled out of reset. Code in the file
CodeStartBranch.asm has been configured to disable the watchdog. This can be
important for large C code projects (ask your instructor if this has not already been
explained). During this lab exercise, the watchdog was actually re-enabled (or disabled
again) in the file Watchdog.c.

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Control Peripherals
ADC Module

ADC Module Block Diagram

ADCINA0
ADCINA1

S/H
A

MUX
A

ADCINB0
ADCINB1

MUX

ADCINA7

S/H
B

MUX
B

Result
MUX

SOCx

ADCINB7
ADC full-scale
input range is
0 to 3.3V

12-bit A/D
Converter

ADC
EOCx
Generation
Logic

CHSEL

SOCx Signal

RESULT0
RESULT1
RESULT2

RESULT15
ADC
ADCINT1-9
Interrupt
Logic
ADCINT1

TRIGSEL
TRIGSEL
TRIGSEL
TRIGSEL

CHSEL
CHSEL
CHSEL
CHSEL

ACQPS
ACQPS
ACQPS
ACQPS

SOC15 TRIGSEL CHSEL ACQPS

SOCx Configuration Registers

SOCx Triggers

ADCINT2
SOC0
SOC1
SOC2
SOC3

Software
CPU Timer (0,1,2)
EPWMxSOCA (x = 1 to 8)
EPWMxSOCB (x = 1 to 8)
External Pin
(GPIO/XINT2_ADCSOC)

The ADC module is based around a 12-bit converter. There are 16 input channels and 16 result
registers. The SOC configuration registers select the trigger source, channel to convert, and the
acquisition prescale window size. The triggers include software by selecting a bit, CPU timers 0,
1 and 2, EPWMA and EPWMB 1 through 8, and an external pin. Additionally, ADCINT 1 and 2
can be fed back for continuous conversions.
The ADC module can operate in sequential sampling mode or simultaneous sampling mode. In
simultaneous sampling mode, the channel selected on the A multiplexer will be the same channel
on the B multiplexer. The ADC interrupt logic can generate up to nine interrupts. The results for
SOC 0 through 15 will appear in result registers 0 through 15.

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Example ADC Triggering (sequential sampling)

Sample A2 B3 A7 when ePWM1 SOCB is generated and then generate ADCINT1:
SOCB (ETPWM1)

SOC0

Channel
A2

Sample
7 cycles

Result0

no interrupt

SOC1

Channel
B3

Sample
10 cycles

Result1

no interrupt

SOC2

Channel
A7

Sample
8 cycles

Result2

ADCINT1

Then after above, sample A0 B0 A5 continuously and generate ADCINT2:

Software Trigger

ADCINT2

SOC3

Channel
A0

Sample
10 cycles

Result3

no interrupt

SOC4

Channel
B0

Sample
15 cycles

Result4

no interrupt

SOC5

Channel
A5

Sample
12 cycles

Result5

ADCINT2

The top example on this slide shows channels A2, B3, and A7 being converted with a trigger
from EPWM1SOCB. After A7 is converted, ADCINT1 is generated.
The bottom examples extends this with channels A0, B0, and A5 being converted initially with a
software trigger. After A5 is converted, ADCINT2 is generated, which is fed back as a trigger to
start the process again.

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Example ADC Triggering (simultaneous sampling)

Sample all channels continuously and provide Ping-Pong interrupts to CPU/system:
Software Trigger

SOC0

Channel
A0:B0

Sample
7 cycles

Result0
Result1

no interrupt

SOC2

Channel
A1:B1

Sample
7cycles

Result2
Result3

no interrupt

SOC4

Channel
A2:B2

Sample
7 cycles

Result4
Result5

no interrupt

SOC6

Channel
A3:B3

Sample
7 cycles

Result6
Result7

ADCINT1

SOC8

Channel
A4:B4

Sample
7 cycles

Result8
Result9

no interrupt

SOC10

Channel
A5:B5

Sample
7 cycles

Result10
Result11

no interrupt

SOC12

Channel
A6:B6

Sample
7 cycles

Result12
Result13

no interrupt

SOC14 Channel

Sample
7 cycles

Result14
Result15

ADCINT2

ADCINT2

A7:B7

The example on this slide shows channels A/B 0 through 7 being converted in simultaneous
sampling mode, triggered initially by software. After channel A/B three is converted, ADCINT1
is generated. After channel A/B seven is converted, ADCINT2 is generated and fed back to start
the process again. ADCINT1 and ADCINT2 are being used as ping-pong interrupts.

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Comparator

A0
B0
A1
B1
A2
B2

AIO2
AIO10

10-bit
DAC

COMP1

AIO4
AIO12

10-bit
DAC

COMP2

AIO6
AIO14

10-bit
DAC

COMP3

COMP1OUT

A3
B3
A4
B4

COMP2OUT

ADC

A5
B5
A6
B6

COMP3OUT

A7
B7

This device has three analog comparators that share the input pins with the analog-to-digital
converter module. If neither the ADC or comparator input pins are needed, the input pins can be
used as analog I/O pins. As you can see, one of the inputs to the comparator comes directly from
the input pin, and the other input can be taken from the input pin or the 10-bit digital-to-analog
converter. The output of the comparator is fed into the ePWM digital compare sub-module.

ADC Control Registers (file: Adc.c)

ADCTRL1

ADCSOCxCTL

(Sampling Mode Register)

sequential sampling / simultaneous sampling

INTSELxNy

(Interrupt SOC Selection 1 and 2 Registers)

selects ADCINT1 / ADCINT2 trigger for SOCx

ADCSAMPLEMODE

(SOC0 to SOC15 Control Registers)

trigger source
channel
acquisition sampling window

ADCINTSOCSELx

(ADC Control Register 1)

module reset, ADC enable

busy/busy channel
reference select
Interrupt generation control

(Interrupt x and y Selection Registers)

EOC0 EOC15 source select for ADCINT1-9

ADCRESULTx

(ADC Result 0 to 15 Registers)

Note: refer to the reference guide for a complete listing of registers

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The previous slide is a brief overview covering a few of the ADC control registers. It can be used
as a reference during the lab exercise.

Pulse Width Modulation

What is Pulse Width Modulation?

PWM

is a scheme to represent a
signal as a sequence of pulses
fixed

carrier frequency
fixed pulse amplitude
pulse width proportional to
instantaneous signal amplitude
PWM energy original signal energy

Original Signal

PWM representation

Pulse width modulation, or PWM, is a technique used to represent a signal as a sequence of

pulses. A PWM waveform has a fixed carrier frequency, fixed pulse amplitude, and the pulse
width is proportional to the instantaneous signal amplitude.

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Why use PWM with Power

Switching Devices?

Desired output currents or voltages are known

Power switching devices are transistors
Difficult

to control in proportional region

Easy to control in saturated region

PWM is a digital signal easy for MCU to output

DC Supply

DC Supply

?
Desired
signal to
system

Unknown Gate Signal

PWM
PWM approx.
of desired
signal

Gate Signal Known with PWM

Power-switching devices are difficult to control in the proportional region but are easy to control
in the saturation and cutoff region. Since PWM is a digital signal and easy for microcontrollers to
generate, it is ideal for use with power-switching devices.

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ePWM

ePWM Module Signals and Connections

ePWMx-1

GPIO
MUX
eQEP1
SYSCTRL
CPU

TZ1 TZ3

EPWMxSYNCI

EPWMxINT

EQEP1ERR TZ4
CLOCKFAIL TZ5

EPWMxTZINT

EPWMxA

ePWMx

EPWMxB

PIE
GPIO
MUX

EMUSTOP TZ6

COMP

EPWMxSOCA
COMPxOUT

EPWMxSOCB

ADC

EPWMxSYNCO

ePWMx+1

An ePWM module can be synchronized with adjacent ePWM modules. The generated PWM
waveforms are available as outputs on the GPIO pins. Additionally, the EPWM module can
generate ADC starter conversion signals and generate interrupts to the PIE block. External trip
zone signals can trip the output and generate interrupts, too. The outputs of the comparators are
used as inputs to the digital compare sub-module. Next, we will look at the internal details of the
ePWM module.

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ePWM Block Diagram

Clock
Prescaler

TBCLK

Shadowed

Shadowed

Compare
Register

Compare
Register

16-Bit
Time-Base
Counter

EPWMxSYNCI

Compare
Logic

EPWMxSYNCO

Period
Register

Action
Qualifier

Dead
Band

EPWMxA

Shadowed

PWM
Chopper

Trip
Zone
EPWMxB

SYSCLKOUT

TZy

Digital
Compare

TZ1-TZ3

COMPxOUT

The ePWM, or enhanced PWM block diagram, consists of a series of sub-modules. In this
section, we will learn about the operation and details of each sub-module.

ePWM Time-Base Sub-Module

Clock
Prescaler

TBCLK

Shadowed

Shadowed

Compare
Register

Compare
Register

16-Bit
Time-Base
Counter

EPWMxSYNCI

EPWMxSYNCO

Compare
Logic

Period
Register
Shadowed

Action
Qualifier

Dead
Band

EPWMxA

PWM
Chopper

Trip
Zone
EPWMxB

SYSCLKOUT

TZy

Digital
Compare

TZ1-TZ3

COMPxOUT

In the time-base sub-module, the clock prescaler divides down the device core system clock and
clocks the 16-bit time-base counter. The time-base counter is used to generate asymmetrical and

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symmetrical waveforms using three different count modes: count-up mode, countdown mode, and
count up and down mode. A period register is used to control the maximum count value.
Additionally, the time-base counter has the capability to be synchronized and phase-shifted with
other ePWM units.

ePWM Time-Base Count Modes

TBCTR
TBPRD
Asymmetrical
Waveform
Count Up Mode
TBCTR
TBPRD
Asymmetrical
Waveform
Count Down Mode
TBCTR
TBPRD
Symmetrical
Waveform
Count Up and Down Mode

The upper two figures show the time-base counter in the count-up mode and countdown mode.
These modes are used to generate asymmetrical waveforms. The lower figure shows the timebase counter in the count up and down mode. This mode is used to generate symmetrical
waveforms.

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ePWM Phase Synchronization

Ext. SyncIn
Phase
=0

SyncIn

En

o o

EPWM1A

o
CTR=zero o
CTR=CMPB o o
o
X
SyncOut

Phase
=120

EPWM1B
To eCAP1
SyncIn

SyncIn

En

o o

=120

EPWM2A

o
CTR=zero o
CTR=CMPB o o
o
X

EPWM2B

SyncOut

Phase
=240

SyncIn

En

o o

o
o
o o
o

CTR=zero
CTR=CMPB
X

=120
EPWM3A
EPWM3B
=240

SyncOut

If needed, an ePWM module can be synchronized with adjacent ePWM modules.

Synchronization is based on a synch-in signal, time-base counter equals zero, or time-base
counter equals compare B register. Additionally, the waveform can be phase-shifted.

ePWM Compare Sub-Module

Clock
Prescaler

TBCLK

Shadowed

Shadowed

Compare
Register

Compare
Register

16-Bit
Time-Base
Counter

EPWMxSYNCI

EPWMxSYNCO

Compare
Logic

Period
Register
Shadowed

Action
Qualifier

Dead
Band

EPWMxA

PWM
Chopper

Trip
Zone
EPWMxB

SYSCLKOUT

TZy

Digital
Compare

TZ1-TZ3

COMPxOUT

The compare sub-module uses two compare registers to detect time-base count matches. These

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compare match events are fed into the action qualifier sub-module. Notice that the output of this
block feeds two signals into the action qualifier.

ePWM Compare Event Waveforms

TBCTR
TBPRD
CMPA
CMPB

. .. ..
.
. .
. . . . .

= compare events are fed to the Action Qualifier Sub-Module

Asymmetrical
Waveform

Count Up Mode

TBCTR
TBPRD
CMPA
CMPB

.. .. ..
. .. .. ..

Asymmetrical
Waveform

Count Down Mode

TBCTR
TBPRD
CMPA
CMPB

..
..
.
.
.. ... ..

Symmetrical
Waveform

Count Up and Down Mode

The figures above show the compare matches that are fed into the action qualifier. Notice that
with the count up and countdown mode, there are matches on the up-count and down-count.

ePWM Action Qualifier Sub-Module

Clock
Prescaler

TBCLK

Shadowed

Shadowed

Compare
Register

Compare
Register

16-Bit
Time-Base
Counter

EPWMxSYNCI

EPWMxSYNCO

Compare
Logic

Period
Register
Shadowed

Action
Qualifier

Dead
Band

EPWMxA

PWM
Chopper

Trip
Zone
EPWMxB

SYSCLKOUT

TZy

Digital
Compare

TZ1-TZ3

COMPxOUT

The action qualifier sub-module uses the inputs from the compare logic and time-base counter to

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generate various actions on the output pins. These first few modules are the main components
used to generate a basic PWM waveform.

ePWM Action Qualifier Actions

for EPWMA and EPWMB

S/W
Force

Time-Base Counter equals:

EPWM
Output
Actions

Zero

CMPA

CMPB

TBPRD

SW
X

Z
X

CA
X

CB
X

P
X

Do Nothing

SW

CA

CB

Clear Low

SW

CA

CB

Set High

SW
T

Z
T

CA
T

CB
T

P
T

Toggle

This table shows the various action qualifier compare-match options for when the time-base
counter equals zero, compare A match, compare B match, and period match. Based on the
selected match option, the output pins can be configured to do nothing, clear low, set high, or
toggle. Also, the output pins can be forced to any action using software.

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ePWM Count Up Asymmetric Waveform

with Independent Modulation on EPWMA / B
TBCTR
TBPRD

CMPA

CMPB

. .
.

P
X

CB
X

CA

P
X

CB
X

CA

P
X

P
X

CB

CA
X

P
X

CB

CA
X

P
X

EPWMA

EPWMB

The next few figures show how the action qualifier uses the compare matches to modulate the
output pins. Notice that the output pins for EPWMA and EPWMB are completely independent.
Here, on the EPWMA output, the waveform will be set high on zero match and clear low on
compare A match. On the EPWMB output, the waveform will be set high on zero match and
clear low on compare B match.

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Control Peripherals

ePWM Count Up Asymmetric Waveform

with Independent Modulation on EPWMA
TBCTR

CMPB

CMPA

TBPRD

CA

CA

CB

.
CB

EPWMA
Z
T

Z
T

Z
T

EPWMB

This figure has the EPWMA output set high on compare A match and clear low on compare B
match, while the EPWMB output is configured to toggle on zero match.

ePWM Count Up-Down Symmetric

Waveform
TBCTR
TBPRD
CMPB

CMPA

with Independent Modulation on EPWMA / B

...
.
.
CA

CA

...

CA

CA

EPWMA
CB

CB

CB

CB

EPWMB

Here you can see that we can have different output actions on the up-count and down-count using
a single compare register. So, for the EPWMA and EPWMB outputs, we are setting high on the

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compare A and B up-count matches and clearing low on the compare A and B down-down
matches.

ePWM Count Up-Down Symmetric

Waveform
with Independent Modulation on EPWMA

TBCTR
TBPRD
CMPB

CMPA

..
.
CA

..
.

CA

CB

CB

EPWMA
Z

EPWMB

And finally, again using different output actions on the up-count and down-count, we have the
EPWMA output set high on the compare A up-count match and clear low on the compare B
down-count match. The EPWMB output will clear low on zero match and set high on period
match.

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ePWM Dead-Band Sub-Module

Clock
Prescaler

TBCLK

Shadowed

Shadowed

Compare
Register

Compare
Register

16-Bit
Time-Base
Counter

EPWMxSYNCI

EPWMxSYNCO

Compare
Logic

Period
Register
Shadowed

Action
Qualifier

Dead
Band

EPWMxA

PWM
Chopper

Trip
Zone
EPWMxB

SYSCLKOUT

TZy

Digital
Compare

TZ1-TZ3

COMPxOUT

The dead-band sub-module provides a means to delay the switching of a gate signal, thereby
allowing time for gates to turn off and preventing a short circuit.

Motivation for Dead-Band

supply rail

gate signals are

complementary PWM

to power
switching
device

Transistor gates turn on faster than they shut off

Short circuit if both gates are on at same time!

To explain further, power-switching devices turn on faster than they shut off. This issue would
momentarily provide a path from supply rail to ground, giving us a short circuit. The dead-band

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Control Peripherals

sub-module alleviates this issue.

ePWM Chopper Sub-Module

Clock
Prescaler

TBCLK

Shadowed

Shadowed

Compare
Register

Compare
Register

16-Bit
Time-Base
Counter

EPWMxSYNCI

Compare
Logic

EPWMxSYNCO

Action
Qualifier

Period
Register

Dead
Band

EPWMxA

PWM
Chopper

Shadowed

Trip
Zone
EPWMxB

SYSCLKOUT

TZy

Digital
Compare

TZ1-TZ3

COMPxOUT

The PWM chopper sub-module uses a high-frequency carrier signal to modulate the PWM
waveform. This is used with pulsed transformer-based gate drives to control power-switching
elements.

ePWM Chopper Waveform

Used with pulse transformer-based gate drivers to control power switching elements
EPWMxA
EPWMxB
CHPFREQ
EPWMxA

EPWMxB

OSHT

EPWMxA

Programmable
Pulse Width
(OSHTWTH)

Sustaining
Pulses

With One-Shot Pulse on EPWMxA and/or EPWMxB

As you can see in this figure, a high-frequency carrier signal is ANDed with the ePWM outputs.

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Control Peripherals

Also, this circuit provides an option to include a larger, one-shot pulse width before the sustaining
pulses.

ePWM Digital Compare and Trip-Zone

Sub-Modules
Clock
Prescaler

TBCLK

Shadowed

Shadowed

Compare
Register

Compare
Register

16-Bit
Time-Base
Counter

EPWMxSYNCI

EPWMxSYNCO

Compare
Logic

Period
Register
Shadowed

Action
Qualifier

Dead
Band

EPWMxA

PWM
Chopper

Trip
Zone
EPWMxB

SYSCLKOUT

TZy

Digital
Compare

TZ1-TZ3

COMPxOUT

The trip zone and digital compare sub-modules provide a protection mechanism to protect the
output pins from abnormalities, such as over-voltage, over-current, and excessive temperature
rise.

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Digital Compare Sub-Module Signals

DCAH

TZ1

Digital Trip
Event A1
Compare

DCAEVT1

blanking
TZ2
DCAL

TZ3

Time-Base Sub-Module
Generate PWM Sync
Event-Trigger Sub-Module
Generate SOCA
Trip-Zone Sub-Module
Trip PWMA Output

Digital Trip
Event A2
Compare

Generate Trip Interrupt

DCAEVT2

COMP1OUT
DCBH

COMP2OUT

Digital Trip
Event B1
Compare

DCBEVT1

blanking

COMP3OUT
DCBL

Digital Trip
Event B2
Compare

Time-Base Sub-Module
Generate PWM Sync
Event-Trigger Sub-Module
Generate SOCB
Trip-Zone Sub-Module
Trip PWMB Output
Generate Trip Interrupt

DCBEVT2

DCTRIPSEL

TZDCSEL

DCACTL / DCBCTL

The inputs to the digital compare sub-module are the trip zone pins and the analog comparator
outputs. This module generates compare events that can generate a PWM sync, generate an ADC
start of conversion, trip a PWM output, and generate a trip interrupt. Optional blinking can be
used to temporarily disable the compare action in alignment with PWM switching to eliminate
noise effects.

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Control Peripherals

Trip-Zone Features
Trip-Zone has a fast, clock independent logic path to high-impedance
the EPWMxA/B output pins
Interrupt latency may not protect hardware when responding to over
current conditions or short-circuits through ISR software
Supports:

#1) one-shot trip for major short circuits or over

current conditions
#2) cycle-by-cycle trip for current limiting operation

Over
Current
Sensors
COMPxOUT
TZ1
TZ2
TZ3
TZ4
TZ5
TZ6

eQEP1
SYSCTRL
CPU

CPU
core

Digital
Compare

P
W
M

EPWMxA
EPWMxTZINT

O
U
T
P
U
T
S

Cycle-by-Cycle
Mode
EQEP1ERR

EPWMxB

One-Shot

CLOCKFAIL

Mode

EMUSTOP

The PWM trip zone has a fast, clock-independent logic path to the PWM output pins where the
outputs can be forced to high impedance. Two actions are supported: One-shot trip for major
short circuits or over-current conditions, and cycle-by-cycle trip for current limiting operation.

ePWM Event-Trigger Sub-Module

Clock
Prescaler

TBCLK

Shadowed

Shadowed

Compare
Register

Compare
Register

16-Bit
Time-Base
Counter

EPWMxSYNCI

EPWMxSYNCO

Compare
Logic

Period
Register
Shadowed

Action
Qualifier

Dead
Band

EPWMxA

PWM
Chopper

Trip
Zone
EPWMxB

SYSCLKOUT

TZy

Digital
Compare

TZ1-TZ3

COMPxOUT

The event-trigger sub-module is used to provide a triggering signal for interrupts and the start of

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Control Peripherals

conversion for the ADC.

ePWM Event-Trigger Interrupts and SOC

TBCTR
TBPRD
CMPB

CMPA

.. .

...

EPWMA
EPWMB
CTR = 0
CTR = PRD
CTR = 0 or PRD
CTRU = CMPA
CTRD = CMPA
CTRU = CMPB
CTRD = CMPB

Event-trigger interrupts and start of conversions can be generated on counter equals zero, counter
equal period, counter equal zero or period, counter up equal compare A, counter down equal
compare A, counter up equal compare B, counter down equal compare B. Notice counter up and
down are independent and separate.

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Control Peripherals

Hi-Resolution PWM (HRPWM)

PWM Period

Regular
PWM Step
(i.e. 11.1 ns)

Device Clock
(i.e. 90 MHz)
HRPWM divides a clock
cycle into smaller steps
called Micro Steps
(Step Size ~= 150 ps)

ms

ms

ms

ms

ms

ms

Calibration Logic

Calibration Logic tracks the

number of Micro Steps per
clock to account for
variations caused by
Temp/Volt/Process

HRPWM
Micro Step (~150 ps)

Significantly increases the resolution of conventionally derived digital PWM

Uses 8-bit extensions to Compare registers (CMPxHR), Period register
(TBPRDHR) and Phase register (TBPHSHR) for edge positioning control
Typically used when PWM resolution falls below ~9-10 bits which occurs at
frequencies greater than ~180 kHz (with system clock of 90 MHz)
Not all ePWM outputs support HRPWM feature (see device datasheet)

The high-resolution PWM feature significantly increases the resolution of conventionally-derived

PWM. High-resolution PWM divides a clock cycle into smaller steps called micro steps. The
step size is approximately 150 picoseconds. This is typically used when PWM resolution falls
below approximately 9 or 10 bits, which occurs at frequencies greater than approximately 180
kHz with a system clock of 90 MHz.

ePWM Control Registers (file: EPwm.c)

TBCTL

CMPCTL

(Trip-Zone Control)

enable /disable; action (force high / low / high-Z /nothing)

ETSEL

(Digital Compare Trip Select)

Digital compare A/B high/low input source select

TZCTL

(PWM-Chopper Control)

enable / disable; chopper CLK freq. & duty cycle; 1-shot pulse width

DCTRIPSEL

(Dead-Band Control)

in/out-mode (disable / delay PWMxA/B); polarity select

PCCTL

(Action Qualifier Control Output A/B)

action on up/down CTR = CMPA/B, PRD, 0 (nothing/set/clear/toggle)

DBCTL

(Compare Control)

compare load mode; operating mode (shadow / immediate)

AQCTLA/B

(Time-Base Control)

counter mode (up, down, up & down, stop); clock prescale; period shadow
load; phase enable/direction; sync select

(Event-Trigger Selection)

interrupt & SOCA/B enable / disable; interrupt & SOCA/B select

Note: refer to the reference guide for a complete listing of registers

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The previous slide is a brief overview covering a few of the ePWM control registers. It can be
used as a reference during the lab exercise.

eCAP

Capture Module (eCAP)

Timer
Trigger
pin
Timestamp
Values

The

eCAP module timestamps transitions on a

capture input pin
Can

be used to measure the time width of a pulse

t1
t2

Auxiliary

PWM generation

The capture module allows time-based logging of external signal transitions on the capture input
pins.

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Control Peripherals

eCAP Module Block Diagram Capture Mode

CAP1POL

Polarity
Select 1

Capture 1
Register

32-Bit
Time-Stamp
Counter
Capture 3
Register

Event Logic

CAP2POL

Capture 2
Register

Polarity
Select 2

PRESCALE

CAP3POL

Event
Prescale

Polarity
Select 3

ECAPx
pin

SYSCLKOUT
CAP4POL

Polarity
Select 4

Capture 4
Register

The capture module features a 32-bit time-stamp counter to minimize rollover. Each module has
four capture registers. Polarity can be set to trigger on rising or falling edge, and trigger events
can be pre-scaled. The capture module can operate in absolute time-stamp mode or difference
mode where the counter resets on each capture.

eCAP Module Block Diagram APWM Mode

Shadowed

immediate
mode

32-Bit
Time-Stamp
Counter

Period
Register
(CAP1)

Period
Register
(CAP3)

PWM
Compare
Logic

shadow
mode

ECAP
pin

SYSCLKOUT
immediate
mode

Compare
Register
(CAP2)
Shadowed

88

Compare
Register
(CAP4)

shadow
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Control Peripherals

If the capture module is not used, it can be configured as an asynchronous PWM module.

eQEP

What is an Incremental Quadrature

Encoder?
A digital (angular) position sensor
photo sensors spaced /4 deg. apart
slots spaced deg. apart

/4

light source (LED)

Ch. A
Ch. B
shaft rotation
Incremental Optical Encoder

Quadrature Output from Photo Sensors

The QEP circuit decodes and counts the quadrature encoded input pulses. This circuit can be
used to interface with an optical encoder to get position and speed information from a rotating
machine.

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Control Peripherals

How is Position Determined from

Quadrature Signals?
Position resolution is /4 degrees

(A,B) =

(00) (11)
(10) (01)

Ch. A

increment
counter

00

decrement
counter

10

Illegal
Transitions;
generate
phase error
interrupt

11

Ch. B
01
Quadrature Decoder
State Machine

Using a quadrature decoder state machine, we can determine if the counter is incrementing or
decrementing, and therefore know if the disc is moving clockwise or counterclockwise.

eQEP Module Connections

Ch. A

Quadrature
Capture

Ch. B

EQEPxA/XCLK
32-Bit Unit
Time-Base

EQEPxB/XDIR
QEP
Watchdog

SYSCLKOUT

Quadrature
Decoder

EQEPxI

Index

EQEPxS

Strobe

from homing sensor

Position/Counter
Compare

The QEP module features a direct interface to encoders. In addition to channels A and B being
used for rotational directional information, the index can be used to determine rotational speed,

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Control Peripherals

and the strobe can be used for position from a homing sensor.
Next, in this lab exercise, a 2 kHz, 25 percent duty cycle PWM waveform will be generated by
ePWM1. The waveform will be fed into ADC channel A0 using the jumper wire. The ADC is
being triggered by ePWM2 at a rate of 50 kHz. After each conversion, the CPU will copy the
results into a circular buffer. Using Code Composer Studio, we will view the waveform in the
time domain and frequency domain. Additionally, we will experiment with the real-time
emulation features.

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Lab 3: Control Peripherals

Lab 3: Control Peripherals

Objective
The objective of this lab is to demonstrate and become familiar with the operation of the on-chip
analog-to-digital converter and ePWM. ePWM1A will be setup to generate a 2 kHz, 25% duty
cycle symmetric PWM waveform. The waveform will then be sampled with the on-chip analogto-digital converter and displayed using the graphing feature of Code Composer Studio. The
ADC has been setup to sample a single input channel at a 50 kHz sampling rate and store the
conversion result in a buffer in the MCU memory. This buffer operates in a circular fashion, such
that new conversion data continuously overwrites older results in the buffer.
Two ePWM modules have been configured for this lab exercise:
ePWM1A PWM Generation

Used to generate a 2 kHz, 25% duty cycle symmetric PWM waveform

ePWM2 ADC Conversion Trigger

Used as a timebase for triggering ADC samples (period match trigger SOCA)

Lab 3: Control Peripherals

ePWM1
TB Counter
Compare
Action Qualifier

connector
wire

ADC
RESULT0

CPU copies
result to
buffer during
ADC ISR

data
memory

ADCINA0

...

ePWM2 triggering
ADC on period match
using SOCA trigger every
20 s (50 kHz)

View ADC
buffer PWM
Samples

ePWM2

Code Composer
Studio

The software in this exercise configures the ePWM modules and the ADC. It is entirely interrupt
driven. The ADC end-of-conversion interrupt will be used to prompt the CPU to copy the results
of the ADC conversion into a results buffer in memory. This buffer pointer will be managed in a
circular fashion, such that new conversion results will continuously overwrite older conversion
results in the buffer. The ADC interrupt service routine (ISR) will also toggle LED LD2 on the
TMS320F28069 controlSTICK as a visual indication that the ISR is running.

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Notes

ePWM1A is used to generate a 2 kHz PWM waveform

Program performs conversion on ADC channel A0 (ADCINA0 pin)

ADC conversion is set at a 50 kHz sampling rate

ePWM2 is triggering the ADC on period match using SOCA trigger

Data is continuously stored in a circular buffer

Data is displayed using the graphing feature of Code Composer Studio

ADC ISR will also toggle the LED LD2 as a visual indication that it is running

Procedure

Open the Project

1. A project named Lab3 has been created for this lab. Open the project by clicking on
Project Import Existing CCS Eclipse Project. The Import
window will open then click Browse next to the Select search-directory box.
Navigate to: C:\C28x\Labs\Lab3\Project and click OK. Then click Finish to
import the project.
2. In the Project Explorer window, click the plus sign (+) to the left of Lab3 to view
the project files. All Build Options have been configured for this lab. The files used in
this lab are:
Adc.c
CodeStartBranch.asm
DefaultIsr_3_4.c
DelayUs.asm
EPwm.c
F2806x_DefaultIsr.h
F2806x_GlobalVariableDefs.c
F2806x_Headers_nonBIOS.cmd

Gpio.c
Lab.h
Lab_2_3.cmd
Main_3.c
PieCtrl.c
PieVect.c
SysCtrl.c
Watchdog.c

Setup GPIO and ePWM1

Note: DO NOT make any changes to Gpio.c and EPwm.c ONLY INSPECT
3. Open and inspect Gpio.c by double clicking on the filename in the project window.
Notice that the shared I/O pin in GPIO0 has been set for the ePWM1A function. Next,
open and inspect EPwm.c and see that the ePWM1 has been setup to implement the
PWM waveform as described in the objective for this lab. Notice the values used in the
following registers: TBCTL (set clock prescales to divide-by-1, no software force, sync
and phase disabled), TBPRD, CMPA, CMPCTL (load on 0 or PRD), and AQCTLA (set
on up count and clear on down count for output A). Software force, deadband, PWM
chopper and trip action has been disabled. (Note that the last steps enable the timer count
mode and enable the clock to the ePWM module). See the global variable names and
values that have been set using #define in the beginning of the Lab.h file. Notice that
ePWM2 has been initialized earlier in the code for the ADC. Close the inspected files.

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Lab 3: Control Peripherals

Build and Load

4. Click the Build button and watch the tools run in the Console window. Check for
errors in the Problems window.
5. Click the Debug button (green bug). The CCS Debug Perspective view should
open, the program load automatically, and you should now be at the start of Main(). If
the device has been power cycled since the last lab exercise, be sure to configure the boot
mode to EMU_BOOT_SARAM using the Scripts menu.

Run the Code PWM Waveform

6. Open a memory browser window to view some of the contents of the ADC results buffer.
To open a memory browser window click: View Memory Browser on the menu
bar. The address label for the ADC results buffer is AdcBuf (type &AdcBuf) in the
Data memory page. Select Go to view the contents of the ADC result buffer.
Note: Exercise care when connecting any wires, as the power to the controlSTICK is on, and
we do not want to damage the controlSTICK! Details of pin assignments can be found
on the last page of this lab exercise.
7. Using a connector wire provided, connect the PWM1A (pin # 17) to ADCINA0 (pin # 3)
on the controlSTICK.
8. Run your code for a few seconds by using the Resume button on the toolbar, or using
Run Resume on the menu bar. After a few seconds halt your code by using the
Suspend button on the toolbar, or by using Run Suspend on the menu bar. Verify
that the ADC result buffer contains the updated values.
9. Open and setup a graph to plot a 50-point window of the ADC results buffer.
Click: Tools Graph Single Time and set the following values:
Acquisition Buffer Size

50

DSP Data Type

16-bit unsigned integer

Sampling Rate (Hz)

50000

Start Address

AdcBuf

Display Data Size

50

Time Display Unit

Select OK to save the graph options.

10. The graphical display should show the generated 2 kHz, 25% duty cycle symmetric
PWM waveform. The period of a 2 kHz signal is 500 s. You can confirm this by
measuring the period of the waveform using the measurement marker mode graph
feature. In the graph window toolbar, left-click on the ruler icon with the red arrow.
Note when you hover your mouse over the icon, it will show Toggle Measurement

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Marker Mode. Move the mouse to the first measurement position and left-click.
Again, left-click on the Toggle Measurement Marker Mode icon. Move the
mouse to the second measurement position and left-click. The graph will automatically
calculate the difference between the two values taken over a complete waveform period.
When done, clear the measurement points by right-clicking on the graph and select
Remove All Measurement Marks (or Ctrl+Alt+M).

Frequency Domain Graphing Feature of Code Composer Studio

11. Code Composer Studio also has the ability to make frequency domain plots. It does this
by using the PC to perform a Fast Fourier Transform (FFT) of the data. Let's make a
frequency domain plot of the contents in the ADC results buffer (i.e. the PWM
waveform).
Click: Tools Graph FFT Magnitude and set the following values:
Acquisition Buffer Size

50

DSP Data Type

16-bit unsigned integer

Sampling Rate (Hz)

50000

Start Address

AdcBuf

Data Plot Style

Bar

FFT Order

10

Select OK to save the graph options.

12. On the plot window, hold the mouse left-click key and move the marker line to observe
the frequencies of the different magnitude peaks. Do the peaks occur at the expected
frequencies?

Using Real-time Emulation

Real-time emulation is a special emulation feature that allows the windows within Code
Composer Studio to be updated at up to a 10 Hz rate while the MCU is running. This not
only allows graphs and watch windows to update, but also allows the user to change values in
watch or memory windows, and have those changes affect the MCU behavior. This is very
useful when tuning control law parameters on-the-fly, for example.
13. The memory and single time graph windows displaying AdcBuf should still be open. The
connector wire between PWM1A (pin # 17) and ADCINA0 (pin # 3) should still be
connected. In real-time mode, we will have our window continuously refresh at the
default rate. To view the refresh rate click:
Window Preferences
and in the section on the left select the Code Composer Studio category. Click the plus
sign (+) to the left of Code Composer Studio and select Debug. In the section on the
right notice the default setting:
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Lab 3: Control Peripherals

Continuous refresh interval (milliseconds) = 500

Click OK.
Note: Decreasing the Continuous refresh interval causes all enabled continuous refresh
windows to refresh at a faster rate. This can be problematic when a large number of
windows are enabled, as bandwidth over the emulation link is limited. Updating too
many windows can cause the refresh frequency to bog down. In this case you can just
selectively enable continuous refresh for the individual windows of interest.
14. Next we need to enable the graph window for continuous refresh. Select the Single
Time graph. In the graph window toolbar, left-click on the yellow icon with the arrows
rotating in a circle over a pause sign. Note when you hover your mouse over the icon, it
will show Enable Continuous Refresh. This will allow the graph to
continuously refresh in real-time while the program is running.
15. Enable the memory window for continuous refresh using the same procedure as the
previous step.
16. Run the code and watch the windows update in real-time mode. Click:
Scripts Realtime Emulation Control Run_Realtime_with_Reset
17. Carefully remove and replace the connector wire from ADCINA0 (pin # 3). Are the
values updating as expected?
18. Fully halt the CPU in real-time mode. Click:
Scripts Realtime Emulation Control Full_Halt

Terminate Debug Session and Close Project

19. Terminate the active debug session using the Terminate button. This will close the
debugger and return CCS to the CCS Edit Perspective view.
20. Next, close the project by right-clicking on Lab3 in the Project Explorer window
and select Close Project.

Optional Exercise
You might want to experiment with this code by changing some of the values or just modify the
code. Try generating another waveform of a different frequency and duty cycle. Also, try to
generate complementary pair PWM outputs. Next, try to generate additional simultaneous
waveforms by using other ePWM modules. Hint: dont forget to setup the proper shared I/O pins,
etc. (This optional exercise requires some further working knowledge of the ePWM.
Additionally, it may require more time than is allocated for this lab. Therefore, you may want to
try this after the class).
End of Exercise

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Lab Reference: F28069 controlSTICK Header Pin Diagram

ADC-A6
COMP3 (+VE)

ADC-A2
COMP1 (+VE)

ADC-A0

3V3

ADC-A4
COMP2 (+VE)

ADC-B1

EPWM-4B
GPIO-07

TZ1
GPIO-12

10

11

12

SCL-A
GPIO-33

ADC-B6
COMP3 (-VE)

EPWM-4A
GPIO-06

ADC-A1

13

14

15

16

SDA-A
GPIO-32

ADC-B0

EPWM-3B
GPIO-05

5V0
(Disabled by
Default)

17

18

19

20

EPWM-1A
GPIO-00

ADC-B4
COMP2 (-VE)

EPWM-3A
GPIO-04

SPISOMI-A
GPIO-17

21

22

23

24

EPWM-1B
GPIO-01

ADC-A5

EPWM-2B
GPIO-03

SPISIMO-A
GPIO-16

25

26

27

28

SPISTE-A
GPIO-19

ADC-B2
COMP1 (-VE)

EPWM-2A
GPIO-02

GND

29

30

31

32

SPICLK-A
GPIO-18

GPIO-34
(LED)

PWM1A-DAC
(Filtered)

GND

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Flash Programming

Flash Programming
Flash Programming Basics

Flash Programming Basics

The device CPU performs the flash programming

The CPU executes Flash utility code from RAM that reads the Flash
data and writes it into the Flash
We need to get the Flash utility code and the Flash data into RAM
FLASH
Flash
Utility
Code

Emulator

CPU

JTAG
RAM
SCI

Flash
Data

I2C
CAN

ROM

SPI

Bootloader

RS232

GPIO
TMS320F2806x

The CPU itself performs the flash programming. The flash utility code is loaded into RAM and
executed. It then reads the flash data and writes it into the flash memory. The flash utility code
and the flash data can be loaded into the RAM directly using JTAG or through the ROM
bootloader using SCI, SPI, I2C, CAN, or GPIO.

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Flash Programming Basics

Sequence

of steps for Flash programming:

Algorithm

Function

1. Erase

- Set all bits to zero, then to one

2. Program

- Program selected bits with zero

3. Verify

- Verify flash contents

Minimum

Erase size is a sector (8Kw or 16Kw)

Minimum Program size is a bit!
Important not to lose power during erase step:
If CSM passwords happen to be all zeros, the
CSM will be permanently locked!
Chance of this happening is quite small! (Erase
step is performed sector by sector)
There are three steps for flash programming. First, erase, which sets all bits to zero and then one.
Second, program, which programs selected bits with zero. And third, verify, which verifies the
flash contents.
The minimum erase size is a sector. The minimum program size is a bit. Be sure not to lose
power during erase step. Doing so may permanently lock the flash.

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Flash Programming

Programming Utilities and CCS Flash Programmer

Flash Programming Utilities

JTAG Emulator Based

SCI Serial Port Bootloader Based

Code-Skin (http://www.code-skin.com)
Elprotronic FlashPro2000

Production Test/Programming Equipment Based

Code Composer Studio on-chip Flash programmer

BlackHawk Flash utilities (requires Blackhawk emulator)
Elprotronic FlashPro2000
Spectrum Digital SDFlash JTAG (requires SD emulator)
Signum System Flash utilities (requires Signum emulator)

BP Micro programmer
Data I/O programmer

Build your own custom utility

Can use any of the ROM bootloader methods

Can embed flash programming into your application
Flash API algorithms provided by TI

* TI web has links to all utilities (http://www.ti.com/c2000)

There is a wide variety of flash programming utilities available. They include JTAG emulators,
SCI serial port bootloaders, production test/programming equipment, and building your own
custom utilities with flash API algorithms provided by TI. The TI website has links to all utilities
available.

CCS On-Chip Flash Programmer

On-Chip Flash programmer is integrated into the CCS debugger

100

Tools On-Chip Flash

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Flash Programming

The on-chip flash programmer is integrated into the CCS debugger. The programmer lets you
configure the device clock configuration and specify flash program settings, such as eraseprogram-verify, select sectors to erase, set the code security password, as well as frequency test,
depletion recovery, and calculate check sum. These options are available in the Debug
perspective by clicking tools On-Chip Flash.

Code Security Module and Password

Code Security Module (CSM)

Access to the following on-chip memory is restricted:

0x000A80

Flash Registers

0x008000
0x008800
0x008C00
0x009000
0x00A000
0x00C000
0x3D7800
0x3D7C00
0x3D7C80
0x3D7CC0
0x3D8000
0x3F7FF8
0x3F8000

L0 DPSARAM (2Kw)
L1 DPSARAM (1Kw)
L2 DPSARAM (1Kw)
L3 DPSARAM (4Kw)
L4 DPSARAM (8Kw)
reserved
User OTP (1Kw)
reserved
ADC / OSC cal. data
reserved
FLASH (128Kw)
PASSWORDS (8w)

Data reads and writes from restricted memory are only

allowed for code running from restricted memory
All other data read/write accesses are blocked:
JTAG emulator/debugger, ROM bootloader, code running in
external memory or unrestricted internal memory

The code security module prevents reverse engineering and protects valuable intellectual
property. Once a user-define password is stored in flash, data reads and writes from restricted
memory are only allowed from code running from restricted memory. All other data read-write
accesses are blocked. This includes JTAG emulated debugger, ROM bootloader, code running in
external memory, or unrestricted internal memory.

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Flash Programming

CSM Password
0x3D8000

FLASH (128Kw)
0x3F7FF8

128-bit

CSM Password
Locations (PWL)
0x3F7FF8 - 0x3F7FFF

128-Bit Password

user defined password is stored in Flash

128-bit

KEY registers are used to lock and unlock

the device
Mapped

in memory space 0x00 0AE0 0x00 0AE7

Registers EALLOW protected

The code security module 128-bit user-define password is stored in flash starting at address
0x3F7FF8. The 128-bit key registers are used to lock and unlock the device. The key registers
are mapped in memory space 0x000AE0 through 0x000AE7, and they are EALLOW protected.

CSM Password Match Flow

Start

Is PWL =
all 0s?

Yes

Device permanently locked

No
Flash device
secure after
reset or runtime

Is PWL =
all Fs?

Yes

No
Do dummy reads of PWL
0x3F 7FF8 0x3F 7FFF

Write password to KEY registers

0x00 0AE0 0x00 0AE7
(EALLOW) protected

Correct
password?

Yes

Device unlocked
User can access onchip secure memory

No

The password match flow is as follows: Flash is secured after reset or run-time. A dummy read

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Flash Programming

of the passwords is performed. If the passwords are all 0s, then the device is permanently
locked. If the passwords are all Fs, then the device is unlocked. If neither case, then the
passwords are written into the key registers until the correct password is written to unlock the
device. All new devices are shipped with passwords set to Fs, and the device is unlocked.

Next, in the lab exercise, we will program and execute code from the on-chip flash memory. This
device has been designed for stand-alone operation in an embedded system. Using the on-chip
flash eliminates the need for external, nonvolatile memory or a host processor from which to
bootload. The step required to properly configure the software for execution from internal flash
memory will be covered.

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Lab 4: Programming the Flash

Lab 4: Programming the Flash

Objective
The objective of this lab is to program and execute code from the on-chip flash memory. The
TMS320F28069 device has been designed for standalone operation in an embedded system.
Using the on-chip flash eliminates the need for external non-volatile memory or a host processor
from which to bootload. In this lab, the steps required to properly configure the software for
execution from internal flash memory will be covered.

Lab 4: Programming the Flash

data
memory

ADC

ePWM1
TB Counter
Compare
Action Qualifier

ADCINA0

RESULT0

ePWM2 triggering
ADC on period match
using SOCA trigger every
20 s (50 kHz)

ePWM2

Objective:

Program system into Flash Memory

Learn use of CCS Flash Programmer

DO NOT PROGRAM PASSWORDS

...

CPU copies
result to
buffer during
ADC ISR

connector
wire

View ADC
buffer PWM
Samples

Code Composer
Studio

Procedure

Open the Project

1. A project named Lab4 has been created for this lab. Open the project by clicking on
Project Import Existing CCS Eclipse Project. The Import
window will open then click Browse next to the Select search-directory box.
Navigate to: C:\C28x\Labs\Lab4\Project and click OK. Then click Finish to
import the project.
2. In the Project Explorer window, click the plus sign (+) to the left of Lab4 to view
the project files. All Build Options have been configured for this lab. The files used in
this lab are:

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Adc.c
CodeStartBranch.asm
DefaultIsr_3_4.c
DelayUs.asm
EPwm.c
F2806x_DefaultIsr.h
F2806x_GlobalVariableDefs.c
F2806x_Headers_nonBIOS.cmd
Flash.c

Gpio.c
Lab.h
Lab_4.cmd
Main_4.c
Passwords.asm
PieCtrl.c
PieVect.c
SysCtrl.c
Watchdog.c

Link Initialized Sections to Flash

Initialized sections, such as code and constants, must contain valid values at device power-up.
Stand-alone operation of an F28069 embedded system means that no emulator is available to
initialize the device RAM. Therefore, all initialized sections must be linked to the on-chip flash
memory.
Each initialized section actually has two addresses associated with it. First, it has a LOAD
address which is the address to which it gets loaded at load time (or at flash programming time).
Second, it has a RUN address which is the address from which the section is accessed at runtime.
The linker assigns both addresses to the section. Most initialized sections can have the same
LOAD and RUN address in the flash. However, some initialized sections need to be loaded to
flash, but then run from RAM. This is required, for example, if the contents of the section needs
to be modified at runtime by the code.
3. Open and inspect the linker command file Lab_4.cmd. Notice that a memory block
named FLASH_ABCDEFGH has been been created at origin = 0x3D8000, length =
0x01FF80 on Page 0. This flash memory block length has been selected to avoid
conflicts with other required flash memory spaces. See the reference slide at the end of
this lab exercise for further details showing the address origins and lengths of the various
memory blocks used.
4. In Lab_4.cmd the following compiler sections have been linked to on-chip flash
memory block FLASH_ABCDEFGH:
Compiler Sections:
.text

.cinit

.const

.econst

.pinit

.switch

Copying Interrupt Vectors from Flash to RAM

The interrupt vectors must be located in on-chip flash memory and at power-up needs to be
copied to the PIE RAM as part of the device initialization procedure. The code that performs this
copy is located in InitPieCtrl(). The C-compiler runtime support library contains a
memory copy function called memcpy() which will be used to perform the copy.
5. Open and inspect InitPieCtrl() in PieCtrl.c. Notice the memcpy() function used to
initialize (copy) the PIE vectors. At the end of the file a structure is used to enable the
PIE.

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Lab 4: Programming the Flash

Initializing the Flash Control Registers

The initialization code for the flash control registers cannot execute from the flash memory (since
it is changing the flash configuration!). Therefore, the initialization function for the flash control
registers must be copied from flash (load address) to RAM (run address) at runtime. The memory
copy function memcpy() will again be used to perform the copy. The initialization code for the
flash control registers InitFlash() is located in the Flash.c file.
6. Open and inspect Flash.c. The C compiler CODE_SECTION pragma is used to place
the InitFlash() function into a linkable section named secureRamFuncs.
7. The secureRamFuncs section will be linked using the user linker command file
Lab_4.cmd. Open and inspect Lab_4.cmd. The secureRamFuncs will load to
flash (load address) but will run from L4SARAM (run address). Also notice that the
linker has been asked to generate symbols for the load start, load end, and run start
addresses.
While not a requirement from a MCU hardware or development tools perspective (since
the C28x MCU has a unified memory architecture), historical convention is to link code
to program memory space and data to data memory space. Therefore, notice that for the
L4SARAM memory we are linking secureRamFuncs to, we are specifiying PAGE
= 0 (which is program memory).
8. Open and inspect Main_4.c. Notice that the memory copy function memcpy() is being
used to copy the section secureRamFuncs, which contains the initialization
function for the flash control registers.
9. The following line of code in main() is used call the InitFlash() function. Since
there are no passed parameters or return values the code is just:
InitFlash();
at the desired spot in main().

Code Security Module and Passwords

The CSM module provides protection against unwanted copying (i.e. pirating!) of your code from
flash, OTP memory, and the L0, L1, L2, L3 and L4 RAM blocks. The CSM uses a 128-bit
password made up of 8 individual 16-bit words. They are located in flash at addresses 0x3F7FF8
to 0x3F7FFF. During this lab, dummy passwords of 0xFFFF will be used therefore only
dummy reads of the password locations are needed to unsecure the CSM. DO NOT PROGRAM
ANY REAL PASSWORDS INTO THE DEVICE. After development, real passwords are
typically placed in the password locations to protect your code. We will not be using real
passwords in the workshop.
The CSM module also requires programming values of 0x0000 into flash addresses 0x3F7F80
through 0x3F7FF5 in order to properly secure the CSM. Both tasks will be accomplished using a
simple assembly language file Passwords.asm.
10. Open and inspect Passwords.asm. This file specifies the desired password values
(DO NOT CHANGE THE VALUES FROM 0xFFFF) and places them in an initialized

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section named passwords. It also creates an initialized section named csm_rsvd

which contains all 0x0000 values for locations 0x3F7F80 to 0x3F7FF5 (length of 0x76).
11. Open Lab_4.cmd and notice that the initialized sections for passwords and
csm_rsvd are linked to memories named PASSWORDS and CSM_RSVD,
respectively.

Executing from Flash after Reset

The F28069 device contains a ROM bootloader that will transfer code execution to the flash after
reset. When the boot mode selection is set for Jump to Flash mode, the bootloader will branch
to the instruction located at address 0x3F7FF6 in the flash. An instruction that branches to the
beginning of your program needs to be placed at this address. Note that the CSM passwords
begin at address 0x3F7FF8. There are exactly two words available to hold this branch
instruction, and not coincidentally, a long branch instruction LB in assembly code occupies
exactly two words. Generally, the branch instruction will branch to the start of the Cenvironment initialization routine located in the C-compiler runtime support library. The entry
symbol for this routine is _c_int00. Recall that C code cannot be executed until this setup routine
is run. Therefore, assembly code must be used for the branch. We are using the assembly code
file named CodeStartBranch.asm.
12. Open and inspect CodeStartBranch.asm. This file creates an initialized section
named codestart that contains a long branch to the C-environment setup routine.
This section has been linked to a block of memory named BEGIN_FLASH.
13. In the earlier lab exercises, the section codestart was directed to the memory
named BEGIN_M0. Open and inspect Lab_4.cmd and notice that the section
codestart will now be directed to BEGIN_FLASH. Close the inspected files.
On power up the reset vector will be fetched and the ROM bootloader will begin execution. If
the emulator is connected, the device will be in emulator boot mode and will use the EMU_KEY
and EMU_BMODE values in the PIE RAM to determine the bootmode. This mode was utilized
in an earlier lab. In this lab, we will be disconnecting the emulator and running in stand-alone
boot mode (but do not disconnect the emulator yet!). The bootloader will read the OTP_KEY
and OTP_BMODE values from their locations in the OTP. The behavior when these values have
not been programmed (i.e., both 0xFFFF) or have been set to invalid values is boot to flash
bootmode.

Build Lab.out
14. Click the Build button to generate the Lab.out file to be used with the CCS Flash
Programmer. Check for errors in the Problems window.

Programming the On-Chip Flash Memory

In CCS the on-chip flash programmer is integrated into the debugger. When the program is
loaded CCS will automatically determine which sections reside in flash memory based on the
linker command file. CCS will then program these sections into the on-chip flash memory.
Additionally, in order to effectively debug with CCS, the symbolic debug information (e.g.,
symbol and label addresses, source file links, etc.) will automatically load so that CCS knows

C2000 MCU 1-Day Workshop

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Lab 4: Programming the Flash

where everything is in your code. Clicking the Debug button in the CCS Edit Perspective
will automatically launch the debugger, connect to the target, and program the flash memory in a
single step.
15. Program the flash memory by clicking the Debug button (green bug). (If needed,
when the Progress Information box opens select Details >> in order to watch
the programming operation and status). After successfully programming the flash
memory the Progress Information box will close.

Running the Code Using CCS

16. Reset the CPU using the Reset CPU button or click:
Run Reset Reset CPU
The program counter should now be at address 0x3FF75C in the Disassembly window,
which is the start of the bootloader in the Boot ROM. If needed, click on the View
Disassembly button in the window that opens, or click View Disassembly.
17. Under Scripts on the menu bar click:
EMU Boot Mode Select EMU_BOOT_FLASH.
This has the debugger load values into EMU_KEY and EMU_BMODE so that the
bootloader will jump to "FLASH" at address 0x3F7FF6.
18. Single-Step by using the <F5> key (or you can use the Step Into button on the
horizontal toolbar) through the bootloader code until you arrive at the beginning of the
codestart section in the CodeStartBranch.asm file. (Be patient, it will take about
125 single-steps). Notice that we have placed some code in CodeStartBranch.asm
to give an option to first disable the watchdog, if selected.
19. Step a few more times until you reach the start of the C-compiler initialization routine at
the symbol _c_int00.
20. Now do Run Go Main. The code should stop at the beginning of your
main()routine. If you got to that point succesfully, it confirms that the flash has been
programmed properly, that the bootloader is properly configured for jump to flash mode,
and that the codestart section has been linked to the proper address.
21. You can now run the CPU, and you should observe the LED on the controlSTICK
blinking. Try resetting the CPU, select the EMU_BOOT_FLASH boot mode, and then
hitting run (without doing all the stepping and the Go Main procedure). The LED should
be blinking again.
22. Halt the CPU.

Terminate Debug Session and Close Project

23. Terminate the active debug session using the Terminate button. This will close the
debugger and return CCS to the CCS Edit Perspective view.
24. Next, close the project by right-clicking on Lab4 in the Project Explorer window
and select Close Project.

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Lab 4: Programming the Flash

Running the Code Stand-alone Operation (No Emulator)

25. Close Code Composer Studio.
26. Disconnect the controlSTICK from the computer USB port.
27. Re-connect the controlSTICK to the computer USB port.
28. The LED should be blinking, showing that the code is now running from flash memory.
End of Exercise

C2000 MCU 1-Day Workshop

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Lab 4: Programming the Flash

Lab 4 Reference: Programming the Flash

Flash Memory Section Blocks

origin =
0x3D 8000

FLASH
length = 0x1FF80
page = 0

Lab_4.cmd
SECTIONS
{

0x3F 7F80

0x3F 7FF6

CSM_RSVD

codestart

length = 0x76
page = 0

passwords :> PASSWORDS, PAGE = 0

csm_rsvd

BEGIN_FLASH

:> BEGIN_FLASH, PAGE = 0

:> CSM_RSVD,

PAGE = 0

length = 0x2
page = 0
0x3F 7FF8

PASSWORDS
length = 0x8
page = 0

Startup Sequence from Flash Memory

0x3D 8000

_c_int00

FLASH (128Kw)

rts2800_ml.lib

0x3F 7FF6

LB
_c_int00
Passwords (8w)

0x3F 8000

Boot ROM (32Kw)

Boot Code

user code sections

main ( )
{

0x3F F75C

{SCAN GPIO}

BROM vector (32w)

0x3F F75C
0x3F FFC0
1

RESET

110

C2000 MCU 1-Day Workshop

The Next Step

The Next Step

Training

C2000 MCU Multi-day Training Course

TMS320F2806x Workshop Outline
- Architectural Overview
- Programming Development Environment
- Peripheral Register Header Files
- Reset and Interrupts
- System Initialization
- Analog-to-Digital Converter
- Control Peripherals
- Numerical Concepts

In-depth hands-on
TMS320F28069 Design
and Peripheral
Training

- Direct Memory Access (DMA)

- Control Law Accelerator (CLA)
- Viterbi, Complex Math, CRC Unit (VCU)
- System Design
- Communications
- DSP/BIOS
- Support Resources

The C2000 Microcontroller Multi-day Workshop is a hands-on technical course taught by

qualified Texas Instruments instructors. It provides further in-depth training covered in much
greater detail of the topics shown in the outline on this slide. Please check the TI website for the
workshop schedule and enrollment information.

C2000 MCU 1-Day Workshop

111

The Next Step

controlSUITE

controlSUITE

ControlSUITE is a single portal for all C2000 software and has been designed to minimize
software development time. Included in controlSUITE are device-specific drivers and support
software, as well as complete system design examples used in sophisticated applications.
ControlSUITE is a one-stop, single centralized location to find all of your C2000 software needs.
Download controlSUITE from the TI website.

112

C2000 MCU 1-Day Workshop

The Next Step

Development Tools

C2000 Experimenters Kits

F28069, F28035, F28027, F28335, F2808, C28343, C28346, F28M35, F28377D

Experimenter Kits include

Part Number:
TMDSDOCK28069
TMDSDOCK28035
TMDSDOCK28027
TMDSDOCK28335
TMDSDOCK2808
TMDSDOCKH52C1
TMDSDOCK28377D
JTAG emulator required for:
TMDSDOCK28343
TMDSDOCK28346-168

controlCARD
USB docking station
C2000 Applications Software CD
with example code and full
hardware details
Code Composer Studio

Docking station features

Access to controlCARD signals

Breadboard areas
Onboard USB JTAG Emulation

JTAG emulator not required

Available through TI authorized

distributors and the TI eStore

The C2000 development kits are designed to be modular and robust. These kits are complete,
open source, evaluation and development tools where the user can modify both the hardware and
software to best fit their needs.
The various Experimenters Kits shown on this slide include a specific controlCARD and
Docking Station. Most have onboard USB JTAG emulation and no external emulator or power
supply is required. However, where noted, the kits based on a DIMM-168 controlCARD include
a 5-volt power supply and require an external JTAG emulator.

C2000 MCU 1-Day Workshop

113

The Next Step

F28335 Peripheral Explorer Kit

Experimenter Kit includes

Peripheral Explorer features

TMDSPREX28335

ADC input variable resistors

GPIO hex encoder & push buttons
eCAP infrared sensor
GPIO LEDs, I2C & CAN connection
Analog I/O (AIC+McBSP)

Onboard USB JTAG Emulation

F28335 controlCARD
Peripheral Explorer baseboard
C2000 Applications Software CD with
example code and full hardware details
Code Composer Studio

JTAG emulator not required

Available through TI authorized

distributors and the TI eStore

The Peripheral Explorer Kit provides a simple way to learn and interact with all F28335
peripherals. It includes onboard USB JTAG emulation.

C2000 controlSTICK Evaluation Tool

F28069, F28027

Low-cost USB evaluation tool

Onboard JTAG Emulation

Access to controlSTICK signals

C2000 Applications Software

CD with example code and full
hardware details

Code Composer Studio

Available through TI authorized

distributors and the TI eStore

Part Number:

TMDX28069USB
TMDS28027USB

JTAG emulator not required

The controlSTICK is an entry-level evaluation kit. It is a simple, stand-alone tool that allows
users to learn the device and software quickly and easily.

114

C2000 MCU 1-Day Workshop

The Next Step

C2000 LaunchPad Evaluation Kit

F28027, F28027F

Low-cost evaluation kit

F28027 standard version

F26027F version with InstaSPIN-FOC

Various BoosterPacks available

Onboard JTAG Emulation

Part Number:

LAUNCHXL-F28027
LAUNCHXL-F28027F

JTAG emulator not required

Access to LaunchPad signals

C2000 Applications Software
with example code and full
hardware details in available in
controlSUITE
Code Composer Studio
Available through TI authorized
distributors and the TI eStore

The LaunchPad is a low-cost evaluation kit. Like the controlSTICK, it is a simple, stand-alone
tool that allows users to learn the device and software quickly and easily. Additionally, various
BoosterPacks are available.

C2000 controlCARD Application Kits

Developers Kit for Motor Control,

PFC, High Voltage, Digital Power,
Renewable Energy, LED Lighting, etc.
Kits includes

Software download includes

controlCARD and application specific

baseboard
Code Composer Studio
Complete schematics, BOM, gerber
files, and source code for board and
all software
Quickstart demonstration GUI for
quick and easy access to all board
features
Fully documented software specific to
each kit and application

See www.ti.com/c2000 for other kits

and more details
Available through TI authorized
distributors and the TI eStore

The controlCARD based Application Kits demonstrate the full capabilities of the C2000 device in

C2000 MCU 1-Day Workshop

115

The Next Step

an application. All kits are completely open source with full documentation.

C2000 Workshop Download Wiki

C2000 Workshop Download Wiki

http://www.ti.com/hands-on-training
Please be sure to visit the C2000 Workshop Download Wiki. Here, you will find all of the
materials for the C2000 One-day Workshop and the C2000 Multi-day Workshop, as well as the
C2000 archived workshops, which include support for the F2407, F2812, F2808, and F28335
device families.

116

C2000 MCU 1-Day Workshop

The Next Step

Development Support

For More Information . . .

USA Product Information Center (PIC)

Phone: 800-477-8924 or 512-434-1560

E-mail: [email protected]

TI E2E Community (videos, forums, blogs)

Embedded Processor Wiki

http://www.ti.com/training

TI eStore

http://processors.wiki.ti.com

TI Training

http://e2e.ti.com

http://estore.ti.com

TI website

http://www.ti.com

For more information and support, you can contact the product information center, visit the TI
E2E community, embedded processor Wiki, TI training web page, TI eStore, and the TI website.
Thank you for attending this C2000 Microcontroller One-Day Workshop. We hope it was
beneficial to you. For more technical information on the C2000 devices, please consider taking a
multi-day hands-on workshop.

C2000 MCU 1-Day Workshop

117

Notes:

Notes:

118

C2000 MCU 1-Day Workshop