An Quadrants I and III

APPLICATION NOTE
TRIAC DRIVE CIRCUIT

FOR OPERATION IN QUADRANTS I AND III
Ph. RABIER
New triacs with high commutation and dv/dt
performances are now available on the market.
To drive the triac in the 2nd and 3rd quadrants a

discharge capacitor is used as shown in figure 3.
Generally these triacs are only triggerable in the

3 first quadrants (case of SNUBBERLESS and
LOGIC LEVEL triacs) as shown in figure 1.
Figure 3 : Basic diagram of the trigger.
This paper describes a trigger circuit supplying a

negative gate current for quadrants II and III
implemented in a system using a positive power
supply.
SNUBBERLESS
TRIAC
Without a new design, just by adding a capacitor

and a diode new W series triacs can replace
conventional triac.
Figure 1 : The quadrants of a W series triac.
LOAD
+ Vcc
LINE
R2
C
R1
R3
Tr
IA
03PHR 160
++
+
2
nd
1/ Principle :
1 st
rd
- The transistor is switched off, capacitor C is

charged through resistance R2 and diode D.
IG
th
The diode is used to avoid a capacitor load

current through the gate of the triac. A schottky
diode could be used to improve the voltage drop
level lower than the gate non trigger voltage
(VGD).
NOT TRIGGERABLE
01PHR160
I - PRINCIPLE :
Figure 2 shows the schematic of a system with a
sensor, logic and positive power supply (with
respect to the anode 1 of the triac).
Figure 2 : Synoptical diagram of a classical
system.
- When the triac is triggered, the transistor Tr is

switched on, C is discharged through R1 and Tr
and a negative current flows through the gate of
the triac.
The capacitor C acts as a differentiation. We
have to consider different parameters to define
all the components :
- The gate trigger current of the triac (IGT)
- The time duration of the gate current
+V cc
LOAD
- The latching current (IL) especially for small or

inductive loads.
SUPPLY
LINE
SENSOR
LOGIC
TRIGGER
02PHR160
AN440/0592
1/5
APPLICATION NOTE
The gate pulse is shown in Figure 5 :
2/ Review :
Dfinition of the latching current (IL) :
The IL of a triac is the minimum value of the
main current which allows the component to
remain in the conducting state after the gate
current IG has been removed.
Figure 5 : Gate pulse.

IG
That is to say the gate current has to be higher

than IGT until the main current reaches the
latcing current.
Example : for the CW SNUBBERLESS triac :
Q1 - Q3 : ILmax = 50 mA
Q2 : ILmax = 80 mA
With : gate pulse duration of 20s at Tj = 25C
IL max is specified in the CW series triac data
sheet.
Statistically, for BW series triacs we can use the
K ratio
K = ILmax/IGTmax
K = 2,3
Two solutions are possible :
- Triggering with a delay after zero voltage
crossing such that the main current is higher
than IL.
- Triggering at zero voltage crossing with a long
discharge time in order to have no problem with
IL .
II - THE CASE WITH A RESISTIVE LOAD :
t2
t
IGM/2
IGM
05PHR160
t1 calculation :
The triac has to be triggered when the main
current is higher than the latching current, that is
to say t1min is :
IL max
1
t1 = arcsin
2
IRMS
where = 2 . .
IRMS : minimum RMS current in the worst case
(depending on line and load dispersion).
The curve given shows the minimum time versus
IRMS current through the anode (figure 6).
Figure 6 : t1 time versus IRMS for different

latching currents.
1/ First solution: delayed pulse current (figure 4).

Figure 4 : Triggering with delay t1 after zero
crossing.
ANODE
CURRENT
50mA/DIV
GATE
The gate current calculation :
CURRENT
IGT is the maximum gate trigger current specified

in the data sheet. To ensure a good safety
margin and good triggering we have chosen I G =
2.IGT with a pulse duration t2 higher than 20s.
20mA/DIV
0.1ms/DIV
04PHR160
2/5
APPLICATION NOTE
All the components can be defined by the
following formulae :
Figure 8 : Triggering at zero voltage.

ANODE
R1max = (VCC - VGK - VCE)/(2.IGT)
CURRENT
with VGK = 2 V at IG = 2.IGT
50mA/DIV
Cmin = t2/(R1.log2) with t2 = 20s

R2max = 0,001/C
Curve 7 gives the minimum capacitance versus
supply voltage for different sensitivity.
GATE
CURRENT
Figure 7 : Capacitance value versus supply

voltage for different sensitivity.
20mA/DIV
0.2ms/DIV
08PHR160
Note : In figure 8, the pulse through the

transistor base is cancelled before the capacitor
is fully discharged to save energy.
All the components can be defined by the
following formulae :
IL
1
t2 min = arcsin
+ 20s
I
RMS
R1max = (VCC-VGK-VCE)/(2.IGT)
Cmin = t2/(R1.log2)
In this way the RMS current is lower than the full
wave current, the RMS current/full wave current
ratio is :
K2 = 1 2 .
t1
T
.sin ( 4
t1
)
T
R2max = 0,001/C
In this way the RMS current is equal to the full
wave current.
The calculation gives for a 6 Amps CW triac with

a 2 Amps sine current and with an IL = 80 mA.
t1 = 90s
K = 0,99
That means the losses are lower than 1%.
2/ Second solution : Wide current pulse at zero

crossing.
It consists of triggering the triac at zero voltage
crossing voltage as shown in figure 8.
3/5
APPLICATION NOTE
3/ Comparison between these two solutions :
in the following table for 3 differents cases
The calculation of all the components is shown
Figure 9 : Component values for 3 differents cases : triac used : BTA08-600CW (IGT = 35 mA)
IRMS = 2 A
VCC = 5 V
IRMS = 5 A
VCC = 10 V
with delay
at zero
crossing
with delay
IRMS = 5 A
VCC = 5 V
at zero
crossing
with delay
at zero
crossing
t1 min (s)
36
91
36
t2 min (s)
20
56
20
111
20
56
R1 max ()
105
105
34
34
34
34
C min (F)
0.275
0.77
0.85
4.7
0.85
2.37
R2 max ()
3.7
1.3
1.18
0.212
1.18
0.42
III - CASE OF INDUCTIVE LOAD :

With an inductive load another problem occurs :
the problem of the phase lag between load
current and load voltage.
If the phase lag is not constant a gate pulse train

can be used, the calculation parameters are the
same, except for R2 : the capacitor C has to be
charged between 2 pulses so the equation is :
R2=(time between 2 pulses)/(5xC)
It can be solved by taking into account :

- the maximum phase lag to define a delay time
td.
- the latching current to define the time t1
- the inductance to define the time t2= V/L at the
moment when the triac is fired (t2 > 20s) to
have an anode current higher than the latching
current IL.
The figure 10 shows the anode current and the
gate current in the triac, is the case of an
inductive load.
Figure 10 : Current through an inductive load.
IV - THE CASE OF A SMALL LOAD :

This trigger circuit can not be effectively used to
drive small loads (like valves, fan etc...) because
the latching current value is not very small
compared to the load current. In this case a DC
gate current is needed.
V - CONCLUSION :
In the case of controllers supplied by positive
voltage this solution allows of the replacement of
conventional triacs used in the 1st and 4th
quadrants by SNUBBERLESS or LOGIC LEVEL
triacs triggerable only in the 3 first quadrants
without a new design but only by adding a
capacitor and a diode.
Line voltage
Anode current
Two configurations are possible :
IL
t
t2
IG
td
t1
t
IGT
2IGT
10PHR160
4/5
First solution : Triggering after the zero voltage

crossing.
Advantage : capacitor value lower than 1F.
Disadvantage : the need to have a delay after
the zero voltage crossing (delay system
needed).
Second solution : Triggering at zero voltage
crossing.
Advantage : 100% of the power used in the
load.
Disadvantage : capacitor value of a few
microfarads.
APPLICATION NOTE
With inductive loads (motor, transformer, etc...) a
pulse train can be used because of the phase
lag between current and voltage.
With small loads (valve, fan,...) a DC gate
current has to be used to drive the triac because
of the latching current.
In case of logic or transistor failure, the capacitor

C operates as an open circuit for DC current and
avoids all triggering. This factor acts as a safety
feature.
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for
the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its
use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.
Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied.
SGS-THO MSON Microelectronics products are not authorized for use as critical components in life support devices or systems without
express written approval of SGS-THOMSON Microelectronics.
1995 SGS-THOMSON Microelectronics - Printed in Italy - All rights reserved.

SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
5/5
This datasheet has been download from:

www.datasheetcatalog.com
Datasheets for electronics components.

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APPLICATION NOTE

TRIAC DRIVE CIRCUIT

To drive the triac in the 2nd and 3rd quadrants a

Generally these triacs are only triggerable in the

Figure 3 : Basic diagram of the trigger.

This paper describes a trigger circuit supplying a

Without a new design, just by adding a capacitor

- The transistor is switched off, capacitor C is

The diode is used to avoid a capacitor load

- When the triac is triggered, the transistor Tr is

- The latching current (IL) especially for small or

Figure 5 : Gate pulse.

That is to say the gate current has to be higher

Figure 6 : t1 time versus IRMS for different

1/ First solution: delayed pulse current (figure 4).

The gate current calculation :

IGT is the maximum gate trigger current specified

Figure 8 : Triggering at zero voltage.

R1max = (VCC - VGK - VCE)/(2.IGT)

with VGK = 2 V at IG = 2.IGT

Cmin = t2/(R1.log2) with t2 = 20s

Figure 7 : Capacitance value versus supply

Note : In figure 8, the pulse through the

The calculation gives for a 6 Amps CW triac with

2/ Second solution : Wide current pulse at zero

The calculation of all the components is shown

III - CASE OF INDUCTIVE LOAD :

If the phase lag is not constant a gate pulse train

It can be solved by taking into account :

IV - THE CASE OF A SMALL LOAD :

Two configurations are possible :

First solution : Triggering after the zero voltage

In case of logic or transistor failure, the capacitor

1995 SGS-THOMSON Microelectronics - Printed in Italy - All rights reserved.

This datasheet has been download from:

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